testchipintroductionver學習課程

1、ContentsqTest Chip Design & Layout FEOL Device related Design Rule related Reliability related Module check related Analog related SRAM BEOL Design Rule related Reliability related Module check related Analog related第1頁/共81頁第一頁，編輯于星期日：點 十四分。1. Introduction Tech. Spec.Device work; DR&EDR pass

2、 Test Product Work; Reli. Pass Pilot Production Test Chip Technology Development Flow第2頁/共81頁第二頁，編輯于星期日：點 十四分。FEOL Related for Base Line check第3頁/共81頁第三頁，編輯于星期日：點 十四分。2. Transistor matrix(1/3) q Purpose: SPICE model extraction Tr. characterization check, such as short channel effect, narrow width ef

3、fect.qContents: Low voltage Nch/Pch Tr. Medium voltage Nch/Pch Tr. Low/MV voltage native Tr. (Channel length dependence & channel width dependence.) HV Tr.Device Related 第4頁/共81頁第四頁，編輯于星期日：點 十四分。2. Transistor matrix(2/3)CL180G 1.8V Nch,Pch Tr. Matrix0.11101000.1110100Length(um)Width(um)Device Re

4、lated 第5頁/共81頁第五頁，編輯于星期日：點 十四分。2. Transistor matrix(3/3) Layout StyleDevice Related Use min. rule to draw except:pAdd dummy poly beside gate To make sure the poly CD in dense areapDraw pick-up ring surround Transistor a. dense active; b. Poly CD uniformity on both active and STIpPin-out with wide me

5、tal reduce parasitical resistor to avoid impacting Transistor performance, especially on drain and sourcepAvoid using single CT/Via to connect out 第6頁/共81頁第六頁，編輯于星期日：點 十四分。2. Resistance (Poly, Diffusion, Nwell, etc) (1/3)q Purpose: Device performance check Characterize EDR, such as sheet resistance,

6、 2dw(depletion width), variation Use it to check silicide module and dose condition with electrical performanceq Contents: Poly with/without silicide (L dependence/ W dependence) Diffusion with/without silicide (L dependence/ W dependence) Nwell on active/under Field HRPoly ResistanceDevice Related

7、第7頁/共81頁第七頁，編輯于星期日：點 十四分。2. Resistance (Poly, Diffusion, Nwell, etc) (2/3)Device Related 2dWy = 19.322x - 3.8172y = 18.968x - 2.955y = 20.365x - 4.0571-10-50510152025303540-0.500.511.522.5WIaverage*100000第8頁/共81頁第八頁，編輯于星期日：點 十四分。2. Resistance (3/3) Layout StyleDevice Related Use min. rule to draw ex

8、cept:pAdd dummy beside under-test-Res. To make sure the CD in dense areapIf the width is less than CT+2x(extension of CT), use dog-bone to design. Otherwise use rectangle shape to designpLength definition: pDog-bone: space between two shoulderspRectangle: Space between Contacts on two terminals.pSB

9、resistance: SB width parallel to length of under-test-Res.pDesign different width to extract 2dw. The width variations should contains min. rule, wide width and medium between these two. At least three points.pUse wide width to design different length to extract effective length. 第9頁/共81頁第九頁，編輯于星期日：

10、點 十四分。3. CapacitorDevice Related qPurpose: Device performance check Characterize EDR, such as normalized capacitance Check dielectric thickness by terms of conversion from capacitanceExtract parasitical capacitance, such as fringe capacitance of Gate, junction capacitance.q Contents: Gate Cap. (area

11、/periphery)Junction Cap. (area/periphery) NWC Cap. PiP/MiP/MiM第10頁/共81頁第十頁，編輯于星期日：點 十四分。3. CapacitorDevice Related MIM Capacitance Bias VoltageMIM Capacitance Bias Voltagedependencedependence4.70E-114.70E-114.70E-114.71E-114.71E-114.71E-114.71E-114.71E-114.72E-114.72E-114.72E-11-12-9-6-3036912Vbias

12、(v)Capacitance (F)第11頁/共81頁第十一頁，編輯于星期日：點 十四分。3. Capacitor Layout StyleDevice Related Draw Guide Line:pUse Area/Periphery two shapes to extract Area capacitance and fringe capacitance respectivelypUse min. rule to design gate length/gate space on periphery capacitorpThe finger number should be calcul

13、ated from estimated capacitor to make it testable.第12頁/共81頁第十二頁，編輯于星期日：點 十四分。Design Rule Related pa-1 rule:pNwell resistance to check depletion width (2dw)pProcess capabilitypa-2/a-3 rule:pIsolation check with using comb type and VT2pa-4/a-7 rule:pJunction BV checkpa-5/a-6 rule:pIsolation check with

14、 using L shape1. Nwell第13頁/共81頁第十三頁，編輯于星期日：點 十四分。Design Rule Related pa-2/a-3 rule:pIsolation check with using comb typepBoth nwell strip space but also end of line space to must use same rule to check (A split)pIsolation check with using VT2 typepPoly gate is must, and metal gate is optionComb Type

15、AAVT2 with poly strip第14頁/共81頁第十四頁，編輯于星期日：點 十四分。Design Rule Related pa-4/a-7 rule:pUse diode structure to check BVpFix B (generally use looser and safe rule), A variation to check the BV sensitivitypFix A (generally use looser and safe rule), B variation to check BF sensitivitypPdiff surrounding Nwe

16、ll rectangle can check process margin resulting from misalignmentNwellNdiffPdiffABNdiffNwellPdiffPdiffPwellPwellAB第15頁/共81頁第十五頁，編輯于星期日：點 十四分。Design Rule Related pa-5/a-6 rule:pUse L shape to check isolationpUse L shape can monitor both X and Y direction misalignmentpFix A, B variation is to check nw

17、ell to ndiff in pwell isolation. (between terminal 1 and 3)pFix B, A variation is to check pwell to pdiff in nwell isolation (between terminal 2 and 4)pFix A+B (both use min. rule, 1.2x min. rule, 1.5xmin. rule), nwell boundary move is to check process margin with simulating misalignmentNwellPdiffNd

18、iffPdiffNdiffNwellPdiffPdiffPwellPwellABPdiffNdiffPdiffNdiff1234第16頁/共81頁第十六頁，編輯于星期日：點 十四分。Design Rule Related pc-1 rule:pdiffusion resistance to check silicide formationpProcess capability/ Technology featurepc-2/c-3 rule:pIsolation check with using comb type and VT2pc-4a/c-4b rule:pProcess capabil

19、ity/ Technology featurepc-4b is to perform latch-up rulepc-6 rule: unknownpc-7 rule: for meeting implant rule, related to n-5/n-11 or p-5/p-112. Active第17頁/共81頁第十七頁，編輯于星期日：點 十四分。Design Rule Related pc-1 rule:pCheck diffusion resistance stability while use min. width rulepSerpentine strip (snake shap

20、e) to check continuity as well as silicide formationpMin. pitch, 1.5 x pitch, 2 x pitch, however width = min. rulepFix pitch (min. rule), width increase while space decrease at same timepSEM is option to check profile第18頁/共81頁第十八頁，編輯于星期日：點 十四分。Design Rule Related pc-2 rule:pIsolation check with Comb

21、 typepIsolation check with VT2 structurepPoly gate (Poly bulk and Poly strip)pMetal gateGate PolySTIActiveActive0.2umLDDDIFF第19頁/共81頁第十九頁，編輯于星期日：點 十四分。Design Rule Related pn-1/n-2 rule:pProcess capability/ Technology featurepn-4/n-5 rule: unknownpn-17 rule:pNP hole, process capabilitypn-14 rule: pMa

22、ke sure all poly will be implanted by N type although it will suffer process variationpUse poly resistor structure to check. With SB is betterpn-15/n-16 rule:pCheck transistor performance3. NP第20頁/共81頁第二十頁，編輯于星期日：點 十四分。Design Rule Related pn-3/n-9 rule:pRule define: NP/PP layer CD variation + NP/PP

23、overlay margin + process marginpCan use diffusion resistor to check, with SB is betterpMore narrow width, the better. But min. width is not recommended because of worse process control. pDo not recommend to using dog-bone typepMinimize the connection resistancepAll of above will bring noise to data

24、analysispA for n-3 rule check, and B for n-9 rule checkPPNPAB第21頁/共81頁第二十一頁，編輯于星期日：點 十四分。Design Rule Related pn-6 rule:pRule define: S/D widthpCheck Transistor performancexPW距離一定xPWType1Type2第22頁/共81頁第二十二頁，編輯于星期日：點 十四分。Design Rule Related pn-12/n-13 rule:pButting case is to check silicide formationp

25、Use kelvin method to measure following structuresNPPPNwellANdiffNwellPdiffANdiff第23頁/共81頁第二十三頁，編輯于星期日：點 十四分。Design Rule Related pn-15/n-16 rule:pCheck transistor performancepChoosing narrow width is betterpType 1 is to check effective width after suffer counter doping at the edge of transistor pType

26、 2 is to check how to impact transistor performance by implant diffusion on PolypGeneric MOS is surface channel will suffer this issueNdiffN+ PolyP+ PolyP+ will diffuse to NPoly regionPwellType2Type1第24頁/共81頁第二十四頁，編輯于星期日：點 十四分。Design Rule Related pd-1/d-3a rule:pProcess capability/ Technology featur

27、epUse Resistor, Open/Short to checkpd-2/d-3 rule:pTransistor performancepSilicide formationpd-4 rule:pLeakage pathpd-6 rule: pPhoto effect, line end shortenpPhysical check/ Transistor performancepd-5/d-8 rulepTransistor performance under narrow width/short channel effectpd-13/d-a rule:pPhoto effect,

28、 hard to control CDpd-14 rule:pMatch the clear ratio on mask to perform stable photo/etch rate.4. PolyPoly CD check第25頁/共81頁第二十五頁，編輯于星期日：點 十四分。Design Rule Related pd-1 rule:pProcess capability/ Technology featurepUse Resistor to checkpUse Kelvin to convert from resistance to electrical CDpAdd dummy

29、poly at single side or both sidepDense, semi-dense, isolated are mustMin. WidthPolyForce 2Force 1Sense 1Sense 3Dummy PolyPoly CD check第26頁/共81頁第二十六頁，編輯于星期日：點 十四分。Design Rule Related pd-2/d-3 rule:pTransistor performancepSilicide formation: Resistance uniformity, Transistor performance degradationATr

30、ansistorResistor (G-G type)ABTransistorDrainSourceParasitical Res.第27頁/共81頁第二十七頁，編輯于星期日：點 十四分。Design Rule Related pd-3a rule:pComb type to check poly short with/without topographypPoly short on active (silicide effect)pPoly short on FieldpPoly short on active line (topography effect)pVary poly space

31、 with fixed poly line, vary poly line with fixed poly spacePoly short on active linePoly short on active第28頁/共81頁第二十八頁，編輯于星期日：點 十四分。Design Rule Related pd-4 rule:pCheck BV/leakage between Gate Poly and diffusionNdiffPwellA第29頁/共81頁第二十九頁，編輯于星期日：點 十四分。Design Rule Related pd-6 rule: (endcap)pTransistor

32、 performance VT variation, bad uniformity, leakage issuepGenerally impact short Poly gate moreATransistorShorteningAt edge part, Poly CD will be less than design value 第30頁/共81頁第三十頁，編輯于星期日：點 十四分。Design Rule Related pd-13 rule: p45 degree poly CD controlpMinimize the length Mobility difference on ver

33、tical/horizontal and 45 degree. Hard to simulate by modelingpType 1: Keep the total width, vary the length of 45 degree gate poly to compare the VT/Ion parameterspType 2: Rotate regular transistor by 45 degree to compare these twoCurrent flowType 1Regular positionType 245 degree position第31頁/共81頁第三十

34、一頁，編輯于星期日：點 十四分。Design Rule Related pe-2a/e-2b rule:pComes from module (photo) issuepSince the hold is too small, light diffraction will result in mis-open between contact region under a certain CT array. So space must be enlarged from 0.25um to 0.28umpe-4 rulepMisalignment will result in contact et

35、ch on side wall of gate poly, even land on poly. It will lead to high leakage, even short to poly line.pe-5/e-7 rule:pMisalignment will result in contact etch on the boundary of actve and STI. Leads to high leakage at edge.pe-6 rule:pLanding on poly marginpCan use misalignment CT chain to check5. Co

36、ntact第32頁/共81頁第三十二頁，編輯于星期日：點 十四分。Design Rule Related pe-1 rule:pDepends on the thickness of dielectric and process capability, such as etch selectivity rate, photo profilepGenerally use chain and SEM to checkpLayout requirementpDo contact hole size splitpUse stagger to place contact array for easy F

37、A experiment.第33頁/共81頁第三十三頁，編輯于星期日：點 十四分。Design Rule Related pe-2a/e-2b rule:pComes from module (photo) issuepSince the hold is too small, light diffraction will result in mis-open between contact region under a certain CT array. So space must be enlarged from 0.25um to 0.28umpGenerally use physical

38、 check to confirm the rulepHow to prevent:pEnlarge spacepUse PSM (phase shift mask)Unexpected exposed regionBPSGUnexpected exposed region第34頁/共81頁第三十四頁，編輯于星期日：點 十四分。Design Rule Related pe-3 rule:pIf active is out of poly region, e-3 = e-4 + e-6pIf active is under poly region, the check structure is

39、shown belowpMeasure Poly to sub leakage along with contact to active space variationpAlso can check TDDB to verify the contact plasma damage to oxide STIActiveASTIoxide第35頁/共81頁第三十五頁，編輯于星期日：點 十四分。Design Rule Related pe-4 rule:pMisalignment will result in contact etch on side wall of gate poly, even

40、land on poly. It will lead to high leakage, even short to poly line.AoxideActiveSTISTILDDspacer lost第36頁/共81頁第三十六頁，編輯于星期日：點 十四分。Design Rule Related pe-5 rule:pMisalignment will result in contact etch on the boundary of actve and STI. Leads to high leakage at edgepContact etch will eliminate SiO2. If

41、 contact to STI edge space is not enough, contact etch will dig into STI boundary and silicide will flow in as well. It induces leakage path, even worsen isolation (VT2)pThis margin check result can also implement to SRAM designpAnother approach of checking extension rule is to use misalignment CT c

42、hain. (landing performance)AActiveSTISTISTI lostSilicide formation第37頁/共81頁第三十七頁，編輯于星期日：點 十四分。Reliability Related pAll kinds of transistor, such as LV, MV, Low VT, High VT, need to do HCI/NBTI checkpHCI is for all NMOS, and NBTI is for all PMOSpLayout guide line:pAll rule is based on JDEC standard c

43、riterionpSingle MOS with gate diode and individual pin-out terminals, drain, gate, source and bulkpSample account: No special requirementpW= 10um, Length = Min. rule + two split (margin check)pOther rules can refer to transistor layout design1. Device第38頁/共81頁第三十八頁，編輯于星期日：點 十四分。Reliability Related p

44、Different oxide thickness needs relevant GOI/TDDB/QBD structures to monitorpLayout Guide Line:pDraw wide metal (as wide as possible) to pin out Gate terminalpBulk type area = 500um x 500um; Edge pattern: Efficient length 5m per wafer (necessary) pBoth N type and P type are necessarypSample requireme

45、nt: (*: N and P type)pBulk=10cm2 3lots Diff area 2* Shot quantitypPoly edge=100m 3lots Poly perimeter Poly quantity 2* Shot quantitypField edge=100m 3lots Diff perimeter Diffusion quantity 2* Shot quantity2. Oxide reliability GOI/ TDDB/ QBD第39頁/共81頁第三十九頁，編輯于星期日：點 十四分。Reliability Related 3. Antenna (

46、1/3)q Purpose: Antenna ratio measurementq Contents: CT/Via antenna Metal/poly antenna(for Capacitance)Metal/Poly antenna(for Transistor) Antenna Tr. Diode protect Diode area v.s. exemptible antenna ratio 第40頁/共81頁第四十頁，編輯于星期日：點 十四分。Reliability Related 3. Antenna (2/3)Antenna Ratio: AR 1M for 0.25um,

47、2M for 0.18um)Analog Related 第49頁/共81頁第四十九頁，編輯于星期日：點 十四分。3. SRAM - SchematicAnalog Related BL1BL1BBL2BWL1WL2BL2第50頁/共81頁第五十頁，編輯于星期日：點 十四分。3. SRAM - LayoutAnalog Related Draw Guide Line:pHigh DensitypN/P ratiopLayout in symmetric to minimize mismatchpChallenge process marginpManual OPCMetal CrossPoly

48、 Cross第51頁/共81頁第五十一頁，編輯于星期日：點 十四分。3. SRAM - DesignAnalog Related pThe SNM (static-noise-margin) indicates the stability of SRAM CellpN/P ratiopLayout in symmetric to minimize mismatchpChallenge process marginpManual OPCStandby mode (assuming V1=0 and V2=VDD第52頁/共81頁第五十二頁，編輯于星期日：點 十四分。4. ESD Protecti

49、onqPurpose: To provide an appropriate ESD device to protect ICsqContents: Whats ESD ESD design concept I/O TypeAnalog Related 第53頁/共81頁第五十三頁，編輯于星期日：點 十四分。4. ESD qWhats ESD:qElectro-Static DischargeqElectro-Static Sourceq Triboelectricq Inductionq Photoelectric effectq Particle Beamq Freezingq Analog

50、 Related 第54頁/共81頁第五十四頁，編輯于星期日：點 十四分。4. ESD q Typical ESD VoltageAnalog Related 靜電產(chǎn)生方式靜電電壓相對濕度20%相對濕度80%在乙烯基材質(zhì)的地板走動120.25在人造地毯上走動351.5拿起聚乙烯塑料袋200.6在地毯上拖動合成樹脂材質(zhì)的盒子181.5去除PC板上的透明膠布121.5PC板上的薄膜163啟動真空焊接劑去除機81噴電路冷凝噴霧劑155單位：KV 溫度：21度第55頁/共81頁第五十五頁，編輯于星期日：點 十四分。4. ESD q Design ConceptAnalog Related VdsIds

51、Vt1Vt2, It2VspHigher Trigger Can not protect internal devicesLower Holding Suffer latch-up riskVT2 requires to be higher than VT1 turn on uniformly 第56頁/共81頁第五十六頁，編輯于星期日：點 十四分。4. ESD qConventional ESD deviceq The purpose of SB on drainq Current flowq Avoid current crowding in LDD regionq Increase Ro

52、n to lead VT2 higher than VT1Analog Related GGNMOS with SBN+ (P+)N+ (P+)PW (NW)+ V0 V (VDD)Gate0 V (VDD)DrainSourceSilicideNon-SilicideWidth0 VRsubIsub第57頁/共81頁第五十七頁，編輯于星期日：點 十四分。4. ESD - I/O Type q Inputq Outputq Analog I/OqTolerance I/O use pure LV MOS to realize MV inputAnalog Related CMOS output

53、 buffersInternal circuitPADNchPchInternal circuitCMOS input buffersNchPADRPchSecondary ProtectionInternal circuit - drainNchPADPchSecondary ProtectionNormal NchInternal circuitCMOS Tolerance InputStacked NchPADRPchSecondary ProtectionFloating NwellVDD第58頁/共81頁第五十八頁，編輯于星期日：點 十四分。BEOL Related for Base

54、 Line check第59頁/共81頁第五十九頁，編輯于星期日：點 十四分。Design Rule Related pf-1/f-2 rule:pMetal thickness; Process capability/ Technology featurepf-2w rule:pPhoto effectpHillock effect at feet of wide metalpf-3a/f-3b rule:pProcess marginpLine end shorteningpf-4 rule:pPhoto effect min. island1. Metal and Contact第60頁

55、/共81頁第六十頁，編輯于星期日：點 十四分。Design Rule Related pf-1/f-2 rule:pProcess capability/ Technology featurepType 1: Use serpentine/comb type to check open/short without topographypKeep width (min. rule), pitch variation to perform dense, semi-dense, isolated metal linepFix pitch, vary width to check process第61

56、頁/共81頁第六十一頁，編輯于星期日：點 十四分。Design Rule Related pf-1/f-2 rule:pType 2: Open/short with topographypExample: Metal 3 open/short (meander folk), AA/Poly/Metal1/Metal2 under it.pType 3: Line end short checkType 2Type 3第62頁/共81頁第六十二頁，編輯于星期日：點 十四分。Design Rule Related pf-2w rule:pPhoto effectpHillock effect a

57、t feet of wide metal caused by inner stress releaseHillock leads to be shortWide metalnarrow metal第63頁/共81頁第六十三頁，編輯于星期日：點 十四分。Design Rule Related pf-3a/f-3b rule:pType 1: test open/short between two layer metals to check upper metal misalignment第64頁/共81頁第六十四頁，編輯于星期日：點 十四分。Design Rule Related pf-3a/f

58、-3b rule:pType 2: test open/short between two layer metals to lower metal misalignment第65頁/共81頁第六十五頁，編輯于星期日：點 十四分。Design Rule Related pf-3a/f-3b rule:pType 3: Via/Contact chain with misalignment manuallypVia/contact misalignment (only via/contact shift)pUpper metal misalignment (only upper metal shi

59、ft)pLower metal misalignment (only lower metal shift)Via shiftUpper metal shift第66頁/共81頁第六十六頁，編輯于星期日：點 十四分。Design Rule Related pf-3a/f-3b rule:pLayout requirement:pEach column of misalignment patterns repeat 10 times with stepping 0.1um along vertical direction, which in turn result in convenient FA

60、 experiment on it.pDense, semi-dense, isolated via/contact chain are mustpThe isolated Misalignment patterns (X direction pitch = 3um) follow the connection manner of dense type.pOnly one parameter is varied at one time. pDraw via/contact chain as large as possiible第67頁/共81頁第六十七頁，編輯于星期日：點 十四分。Design Rule Relat