儀表放大器的內(nèi)部構(gòu)造 英文翻譯版

1、儀表放大器的內(nèi)部構(gòu)造一種簡單的可實(shí)現(xiàn)放大功能的減法運(yùn)算放大器圖21 由運(yùn)放A1組成的差分放大器功能結(jié)構(gòu)圖由圖21我們可以看出，這是一種提高差模增益的最簡單最實(shí)用的方法。如果R1=R3、R2=R4Vout=（VIN2-VIN1）盡管這種集成放大電路具有放大功能，而且在放大差模信號的同時(shí)可抑制共模信號，但他仍然存在著局限性。首先，反相輸入阻抗太低而且不相等，在放大電路中，運(yùn)方A1的輸入阻抗為100K,而運(yùn)方A2的輸入電阻為200K，是A1的兩倍。所以，當(dāng)在一輸入端加正電壓而另一端接地時(shí)，由于輸入電阻獲得的電壓不同而導(dǎo)致電流不同（信號源電阻上電流的不同會(huì)導(dǎo)致共模抑制比的降低）。此外，這個(gè)電路要求電阻

2、對R1/R2和R3/R4之間有非常相近的匹配，否則，每個(gè)輸入端的增益就會(huì)不同這就會(huì)直接影響共模抑制比。例如，增益為1，所有等價(jià)電阻中即使有一個(gè)電阻出現(xiàn)0.1的匹配誤差，也會(huì)使共模抑制比降到66dB的水平，阻值每偏差100共模抑制比就會(huì)降低6dB。盡管存在這些問題，這種通常被稱為差分放大器或減法器的基本放大電路，作為構(gòu)建模塊，經(jīng)常應(yīng)用于那些高性能放大器中。作為一個(gè)具有獨(dú)立功能的電路，差分放大器在影像設(shè)備和其他高速設(shè)備或具有低頻率高共模抑制比的設(shè)備中具有非常高的實(shí)用性。在具有高共模電壓的電路中，輸入電阻用來分壓及用作放大器的保護(hù)電路。某些通用差分放大器，如具有模擬裝置的AD620，就在其設(shè)計(jì)中使用

3、了經(jīng)過簡單變換的差分放大器，這就使得集成電路可以處理比其本身電壓還要高的共模輸入電壓。例如，當(dāng)電源提供15V的電壓時(shí)，AD620能以高達(dá)270V的共模電壓來放大信號。在差分放大電路的前面增加一個(gè)具有高輸入阻抗的緩沖放大器，可以有效地提高儀表放大器的性能，電路圖如圖22所示。圖22具有緩沖電路的差分放大器因?yàn)榉糯箅娐肪哂泻芨叩妮斎胱杩梗?，信號源的輸入阻抗對放大電路的共模抑制比影響不大。用兩個(gè)運(yùn)方組成一個(gè)具有兩輸入端的緩沖放大器是相當(dāng)合適的，因?yàn)閮蓚€(gè)運(yùn)方不僅可以改善電路的溫度，而且可以節(jié)省電路板空間，盡管電阻值不同，但這一電路和圖23所示電路有著相同的放大功能。圖23帶有控制增益的緩沖放大器結(jié)

4、構(gòu)的差分放大器圖23所示是經(jīng)過進(jìn)一步改進(jìn)的電路，現(xiàn)在輸入緩沖電路用來控制電路的增益，使電路具有更高的靈活性。如果電阻R5R8,R6=R7,并且前面的電阻R1=R3,R2=R4,那么Vout（）(1)當(dāng)圖23所示電路中運(yùn)方A1和A2同等的提高他們的差模增益時(shí)，共模增益也會(huì)隨之提高。三運(yùn)方放大電路圖24所示電路圖為放大電路的改進(jìn)版，并且已經(jīng)成為儀表放大器中最受歡迎的配置，這一經(jīng)典運(yùn)算放大電路是圖23所示電路智能化的改進(jìn)，同以前的電路一樣，圖24所示電路中的運(yùn)方A1和A2用來緩沖輸入電壓。但是，在電路配置中，將電阻R連接在兩個(gè)緩沖放大電路之間，來代替電阻R和R，這樣在電阻R上就會(huì)出現(xiàn)差模電壓（因?yàn)樵?/p>

5、兩放大器連接點(diǎn)處的電壓與它的正極輸入電壓是相等的）。因?yàn)榉糯笃鞯妮斎腚妷海ㄔ谶\(yùn)方A1和A2的輸出端）分別不同的分擔(dān)在電阻R R和R三個(gè)電阻之上，所以差模增益可以僅由電阻R來改變。圖24典型三運(yùn)放結(jié)構(gòu)的儀表放大器用這種連接方法還有另一個(gè)優(yōu)勢：一旦差分放大電路設(shè)置好了與之匹配的電阻，那么改變增益時(shí)不需要匹配其他電阻。如果電阻R5 = R6、 R1 = R3,、R2 = R4。那么Vout= (VIN2 VIN1) (1 + 2)因?yàn)殡娮鑂G兩端電壓等于VIN,通過電阻RG的電流I=。所以，運(yùn)方A1和A2控制著放大電路的增益和輸入信號的放大。但是，當(dāng)在放大器的輸入端加上共模電壓時(shí)，由于電阻RG兩端的

6、電壓相等，電阻上將沒有電流通過。因?yàn)闆]有電流通過RG，(也沒有電流通過R5和R6),運(yùn)方A1和A2起到了。所以，共模信號在通過放大器時(shí)會(huì)受到抑制，而差模信號會(huì)放大為原來的(1 + )倍。理論上，這意味著，使用者可以在不增加共模增益和誤差的情況下獲取想要得到的增益（由電阻RG決定的）。因?yàn)椴钅Ｐ盘柕玫椒糯螅材Ｐ盘枦]有放大，共模抑制比得到提高。因此，在理論上說，共模抑制比和增益成正比增加一個(gè)非常有用的特點(diǎn)。最后，由于電路配置成對稱性，輸入放大器產(chǎn)生的的共模誤差會(huì)在輸出放大器那里得到補(bǔ)償。這包括像共模抑制比頻率這樣的誤差。這些特性說明了這種配置為什么這樣流行。三運(yùn)放的設(shè)計(jì)思路對于構(gòu)建三運(yùn)放結(jié)構(gòu)放

7、大電路來說，以下兩種選擇都是可行的:使用FET（場效應(yīng)晶體放大器）或具有雙端輸入運(yùn)算放大器。FET放大器的偏置電流很低，并且非常適用于具有高輸入阻抗(>)的信號源。相對于雙極放大器來說，F(xiàn)ET放大器具有較低的共模抑制，較高的補(bǔ)償電壓和補(bǔ)償電流，在給定電壓范圍的情況下也可以提供更高擺率。輸出感測端和參考端的設(shè)置使得用戶可以改變反饋回路和地線連接，輸出感測端可以由外部驅(qū)動(dòng)，用來伺服應(yīng)用和調(diào)節(jié)運(yùn)方A3的增益。同樣，參考終端的設(shè)置使得運(yùn)方A3可以運(yùn)用外部的補(bǔ)償電壓。為能正常的運(yùn)轉(zhuǎn)，將輸出感測端和輸出終端連接在一起，就像參考終端和接地端一樣。雙極輸入放大器比起FET放大器，具有較高的共模抑制、較低

8、的輸入補(bǔ)償電壓和電流。超級雙極輸入放大器兼有眾多FET和雙極放大器的優(yōu)點(diǎn)，而且比之FET有著更低的偏置電流。那些粗心的設(shè)計(jì)者運(yùn)用三運(yùn)方設(shè)計(jì)的作品都有一個(gè)共同的缺陷，那就是當(dāng)運(yùn)放在高增益狀態(tài)運(yùn)行時(shí)會(huì)出現(xiàn)共模電壓幅值減小的情況。圖25是三運(yùn)放工作在增益為1000時(shí)的電路圖。在這一例子中，當(dāng)輸出放大器提供單一增益時(shí)，運(yùn)放A1和A2的增益為1000。這就意味著每個(gè)運(yùn)放的輸出端電壓為輸入電壓峰峰值X1000再加上任一輸入端的共模電壓（不管差模信號和共模信號是否以單一增益通過）的0.5倍。所以，如果一個(gè)10mv的差模信號作用于輸入端，加上共模電壓，輸出電壓為5V，A2的輸出電壓為-5V。如果給放大器加一個(gè)

9、15V電壓，通常情況下會(huì)消減為7V或7V多一點(diǎn)。因此，允許8V的共模電壓通過但不能超過12V，這是一種非常典型的單一增益，高增益或是低供給電壓會(huì)進(jìn)一步減小共模電壓幅值。圖25具有減小共模抑制功能的三運(yùn)放儀表放大器基本的兩運(yùn)放儀表放大器圖26所示電路是一種典型的兩運(yùn)放儀表放大器，它具有明顯的優(yōu)勢，只需要兩個(gè)而不是三個(gè)運(yùn)放。并且低耗能低功耗。但是，同三運(yùn)放的設(shè)計(jì)相比，兩運(yùn)放放大電路的非對稱式拓?fù)浣Y(jié)構(gòu)導(dǎo)致了幾個(gè)不利結(jié)果，最糟糕的就是低交流共模增益，這就使得這個(gè)電路沒多少利用價(jià)值。電路的調(diào)節(jié)作用是 Vout（）(1)（因?yàn)镽=R、R=R）此放大器的輸入阻抗很高，而且是對稱的，所以信號源的輸出阻抗可以不

10、對稱。放大電路的輸入偏置電流由兩個(gè)運(yùn)放的同相輸入端對輸入電流的需求所決定，而且，輸入電流相當(dāng)?shù)停@是很典型的。這種放大電路也有不少弱點(diǎn)。首先，對單一的增益不能很好的控制；其次，因?yàn)殡娐返脑鲆嫦喈?dāng)?shù)停沟霉材ｋ妷悍翟龃?；再者，共模抑制也很低，這是由運(yùn)放輸入端電壓Vin1和Vin2相位變化不相等引起的，輸入信號只有在通過運(yùn)放A1后才能和運(yùn)放A2輸入端電壓Vin2相減，所以，運(yùn)放A1輸出電壓會(huì)有些微的延遲或有部分電壓在傳輸中損耗。圖26具有兩運(yùn)放結(jié)構(gòu)的儀表放大器兩運(yùn)放儀表放大器電路通常的最小增益是5，因?yàn)檫@樣就使得電路對交流共模輸入電壓幅值要求很寬松，并且，其充足的帶寬可滿足很多方面的應(yīng)用。雙輸入

11、端放大器的使用使得共模電壓幅值擴(kuò)展到了-VS，這樣就增大了其輸出電壓的范圍(輸出值可從+VS到-VS)。表21顯示了圖26所示電路的增益。并且，為幾個(gè)共同電路增益給出了1%的電阻值。表21 圖26所示電路圖的運(yùn)放A1和A2的可控性增益及部分電阻值表單向供電放大器的兩運(yùn)放共模增益的設(shè)計(jì)思路當(dāng)從圖27所示的兩運(yùn)放儀表放大器電路的參考輸入端觀察時(shí)，我們會(huì)發(fā)現(xiàn)，這一電路僅是兩個(gè)變換器的串聯(lián)。假定兩個(gè)信號輸入端的電壓都是0，那么，輸出電壓 Vo1=-V加于電壓V上的正極電壓可能會(huì)趨于控制放大器負(fù)極的輸出電壓。如果放大器由單向電源（0到4VS）控制，那么，這種情況就不大可能會(huì)出現(xiàn)。圖27 兩運(yùn)放儀表放大器

12、結(jié)構(gòu)圖 從運(yùn)放A1的輸出端到整個(gè)電路的輸出端，即A2的輸出端，電壓增益等于 V=-V從電壓V到V的增益是這兩個(gè)增益的共同作用結(jié)果，等于 V=-V（-）（因?yàn)镽=R、R=R）所以，正如所預(yù)料的，電阻增益為+1，值得注意的是，兩個(gè)變換器的存在導(dǎo)致了這樣的結(jié)果，而在三運(yùn)放儀表放大電路中，其參考輸入端的同相信道起著同樣的作用。和三運(yùn)放一樣，兩運(yùn)放放大電路也可通過單向供電和參考電壓的選擇來限制共模電壓的幅值。圖28運(yùn)用2.5V參考電壓的兩運(yùn)放儀表放大器輸出電壓的范圍限制電路圖圖28是由5V電源電壓控制的兩運(yùn)算器放大電路圖。在本例中參考輸入端輸入電壓為2.5V，對于0V的差模輸入電壓和0到5V的任何輸入共

13、模電壓，理想情況下，輸出電壓應(yīng)該是2.5V。當(dāng)共模電壓從2.5V向5V遞增時(shí)，運(yùn)放A1的輸出電壓為 Vo1=VCM+(VCM-VREF)（R2/R1）在本例中，V=2.5V，R2/R1=1/4，當(dāng)VcM=4.5V時(shí)，A1的輸出電壓將會(huì)達(dá)到5v，共模電壓會(huì)明顯增加。事實(shí)上，運(yùn)放A1和A2的輸入電壓幅值得局限性可能會(huì)將放大器共模電壓幅值限制在4.5V內(nèi)。同樣，當(dāng)共模電壓從2.5v降到0時(shí)，運(yùn)放A1的輸出電壓由0.5V的共模電壓降為0。很明顯，運(yùn)放A1的輸出電壓并不比反向輸入或放大器輸出電壓向負(fù)電壓方向拓展多多少。這種反向供給或運(yùn)放在單項(xiàng)供電時(shí)的輸出電壓為0。對于AD620內(nèi)的單片式兩運(yùn)放儀表放大器

14、，即使最為恰當(dāng)?shù)脑O(shè)計(jì)正共模電壓幅度仍會(huì)為利于控制而降為0。另外，可能更為糟糕的是，同三運(yùn)放儀表放大器設(shè)計(jì)相比，兩運(yùn)放儀表放大器設(shè)計(jì)標(biāo)準(zhǔn)的局限性，對其獲得高交流共模抑制是一個(gè)內(nèi)在的阻礙，這一局限性源于兩運(yùn)放共模信道中固有的不平衡狀態(tài)。假定一正弦電壓以FCM的頻率輸入V和V（圖28），理想情況下，若獨(dú)立頻率FCM至少在正常交流電壓頻率范圍之內(nèi)4050HZ，那么，最終交流輸出電壓的幅值應(yīng)該是0V（共模誤差），電壓傳輸將成為大量共模干擾的源泉。直接供給VIN2的共模電壓和被運(yùn)放A1及經(jīng)電阻R1、R2組成的伴隨運(yùn)放A1的增益電路放大后的共模電壓之間，在到0伏時(shí)有著瞬間的差別。如果交流共模誤差為0，運(yùn)放A

15、1和由其電阻R3、R4組成的增益電路一定會(huì)出現(xiàn)這種瞬間的差別。任何交流共模誤差（假定這種微不足道的誤差來自運(yùn)放本身的共模抑制比）都能通過調(diào)整R1、R2、R3、R4的比例來消除，進(jìn)而獲得如下平衡,R1=R4、R2=R3。但是，任何由放大器A1引入的相位移動(dòng)都會(huì)導(dǎo)致電壓VO1的相位略微滯后于VIN2的直接供給電壓的相位。這種相位上的不同步會(huì)導(dǎo)致VO1和VIN2之間瞬間的不同(傳輸媒介)，即使產(chǎn)生兩電壓的放大器正處于其最理想的水平，這就會(huì)使得電路的輸出電壓Vout的頻率依賴于共模誤差電壓。進(jìn)而，這種交流共模誤差將會(huì)隨共模頻率線性的增加，因?yàn)橥ㄟ^運(yùn)放A1的相位移動(dòng)共模誤差會(huì)隨頻率徑直增加，事實(shí)上，因?yàn)?/p>

16、頻率遠(yuǎn)少于運(yùn)放A1閉環(huán)頻帶的1/10，共模誤差（涉及到放大器的輸入）可以在輸出電壓Vout的共模誤差電壓那與A1閉環(huán)帶寬接近，由以下公式可看出 %CMError=(100%)=% G是差模增益本例中為5。例如，如果運(yùn)放A1有一個(gè)100KHZ的閉環(huán)增益（對微電放大器來說是相當(dāng)?shù)湫偷模?，?dāng)通過R1和R2來控制增益設(shè)置并且共模頻率為100HZ時(shí)，那么%CMError=100HZ/100KHZ =0.1%1%的共模誤差等效于60dB的共模抑制，所以，在本例中即使改變電路獲得100dB的交流CRM，這只能對不到1HZ的頻率起作用。AD627同相放大器是兩運(yùn)放儀表放大器中較為先進(jìn)的產(chǎn)品，它克服了交流共模抑

17、制的局限性，正如圖29所示，AD627可以在8KHZ時(shí)保持80dB的CRM（增益為1000），即使運(yùn)放A1和A2的頻帶只有150KHZ。圖29儀表放大器AD627的共模抑制和頻率比率圖用于減法器中的四個(gè)電阻通常處于集成電路的內(nèi)部并且有很高的阻值。 很典型的，高共模電壓的差分放大器用輸入電阻進(jìn)行電壓的調(diào)節(jié).所以，差模信號和共模信號電壓是可調(diào)的，共模電壓受到抑制，而差模電壓就得到放大。INSIDE AN INSTRUMENTATION AMPLIFIERA Simple Op Amp Subtractor Provides an In-Amp FunctionThe simplest (but s

18、till very useful) method of implementing a differential gain block is shown in Figure 2-1.Figure 2-1. A 1-Op Amp IN-Amp Difference Amplifier Circuit Functional Block DiagramAlthough this circuit provides an in-amp function, amplifying differential signals while rejecting those that are common mode,

19、it also has some limitations. First, the impedances of the inverting and noninverting inputs are relatively low and unequal. In this example, the input impedance to VIN1 equals 100 k, while the impedance of VIN2 is twice that, at 200 k. Therefore, when voltage is applied to one input while grounding

20、 the other, different currents will flow depending on which input receives the applied voltage. (This unbalance in the sources resistances will degrade the circuits CMRR.)Furthermore, this circuit requires a very close ratio match between resistor pairs R1/R2 and R3/R4; otherwise, the gain from each

21、 input would be differentdirectly affecting common-mode rejection. For example, at a gain of 1, with all resistors of equal value, a 0.1% mismatch in just one of the resistors will degrade the CMR to a level of 66 dB (1 part in 2,000). Similarly, a source resistance imbalance of 100歐 will degrade CM

22、R by 6 dB.In spite of these problems, this type of bare bones in-amp circuit, often called a difference amplifier or subtractor, is useful as a building block within higher performance in-amps. It is also very practical as a standalone functional circuit in video and other high speed uses, or in low

23、 frequency, high common-mode voltage (CMV) applications, where the input resistors divide down the input voltage as well as provide input protection for the amplifier. Some monolithic difference amplifiers such as Analog Devices AD629 employ a variation of the simple subtractor in their design. This

24、 allows the IC to handle common-mode input voltages higher than its own supply voltage. For example, when powered from a 正負(fù)15 V supply, the AD629 can amplify signals with common-mode voltages as high as正負(fù)270 V.Improving the Simple Subtractor with Input BufferingAn obvious way to significantly improv

25、e performance is to add high input impedance buffer amplifiers ahead of the simple subtractor circuit, as shown in the 3-op amp instrumentation amplifier circuit of Figure 2-2.Figure 2-2. A Subtractor Circuit with Input BufferingThis circuit provides matched, high impedance inputs so that the impeda

26、nces of the input sources will have a minimal effect on the circuits common-mode rejection. The use of a dual op amp for the 2-input buffer amplifiers is preferred because they will better track each other over temperature and save board space. Although the resistance values are different, this circ

27、uit has the same transfer function as the circuit of Figure 2-3.Figure 2-3. A Buffered Subtractor Circuit with Buffer Amplifiers Operating with GainFigure 2-3 shows further improvement: now the input buffers are operating with gain, which provides a circuit with more flexibility. If the value of R5

28、= R8 and R6 = R7 and, as before, R1 = R3 and R2 = R4, thenVOUT = (VIN2 VIN1) (1 + R5/R6) (R2/R1)While the circuit of Figure 2-3 does increase the gain (of A1 and A2) equally for differential signals, it also increases the gain for common-mode signals.The 3-Op Amp In-AmpThe circuit of Figure 2-4 prov

29、ides further refinement and has become the most popular configuration for instrumentation amplifier design. The classic 3-op amp in-amp circuit is a clever modification of the buffered subtractor circuit of Figure 2-3. As with the previous circuit, op amps A1 and A2 of Figure 2-4 buffer the input vo

30、ltage. However, in this configuration, a single gain resistor, RG, is connected between the summing junctions of the two input buffers, replacing R6 and R7. The full differential input voltage will now appear across RG (because the voltage at the summing junction of each amplifier is equal to the vo

31、ltage applied to its positive input). Since the amplified input voltage (at the outputs of A1 and A2) appears differentially across the three resistors R5, RG, and R6, the differential gain may be varied by just changing RG.Figure 2-4. The Classic 3-Op Amp In-Amp CircuitThere is another advantage of

32、 this connection: once the subtractor circuit has been set up with its ratio-matched resistors, no further resistor matching is required when changing gains. If the value of R5 = R6, R1 = R3, and R2 = R4, thenVout= (VIN2 VIN1) (1 + 2R5/RG)(R2/R1)Since the voltage across RG equals VIN, the current th

33、rough RG will equal (VIN/RG). Amplifiers A1 and A2, therefore, will operate with gain and amplify the input signal. Note, however, that if a common-mode voltage is applied to the amplifier inputs, the voltages on each side of RG will be equal and no current will flow through this resistor. Since no

34、current flows through RG (nor, therefore, through R5 and R6), amplifiers A1 and A2 will operate as unity gain followers. Therefore, common-mode signals will be passed through the input buffers at unity gain, but differential voltages will be amplified by the factor (1 + (2 RF/RG). In theory, this me

35、ans that the user may take as much gain in the front end as desired (as determined by RG) without increasing the common-mode gain and error. That is, the differential signal will be increased by gain, but the common-mode error will not, so the ratio (Gain (VDIFF)/(VERR OR CM) will increase. Thus, CM

36、RR will theoretically increase in direct proportion to gaina very useful property. Finally, because of the symmetry of this configuration, common-mode errors in the input amplifiers, if they track, tend to be canceled out by the output stage subtractor. This includes such errors as common-mode rejec

37、tion vs. frequency. These features explain the popularity of this configuration. 3-Op Amp In-Amp Design Considerations Two alternatives are available for constructing 3-op amp instrumentation amplifiers: using FET or bipolar input operational amplifiers. FET input op amps have very low bias currents

38、 and are generally well suited for use with very high (>10E6歐) source impedances. FET amplifiers usually have lower CMR, higher offset voltage, and higher offset drift than bipolar amplifiers. They also may provide a higher slew rate for a given amount of power.The sense and reference terminals (

39、Figure 2-4) permit the user to change A3s feedback and ground connections. The sense pin may be externally driven for servo applications and others for which the gain of A3 needs to be varied. Likewise, the reference terminal allows an external offset voltage to be applied to A3. For normal operatio

40、n, the sense and output terminals are tied together, as are reference and ground.Amplifiers with bipolar input stages tend to achieve both higher CMR and lower input offset voltage drift than FET input amplifiers. Super beta bipolar input stages combine many of the benefits of FET and bipolar proces

41、ses, with even lower IB drift than FET devices.A common (but frequently overlooked) pitfall for the unwary designer using a 3-op amp in-amp design is the reduction of common-mode voltage range that occurs when the in-amp is operating at high gain. Figure 2-5 is a schematic of a 3-op amp in-amp opera

42、ting at a gain of 1,000.Figure 2-5. A 3-Op Amp In-Amp Showing Reduced CMV RangeIn this example the input amplifiers, A1 and A2, are operating at a gain of 1,000, while the output amplifier is providing unity gain. This means that the voltage at the output of each input amplifier will equal one-half

43、the peak-to-peak input voltage X 1,000, plus any common-mode voltage that is present on the inputs (the common-mode voltage will pass through at unity gain regardless of the differential gain). Therefore, if a 10 mV differential signal is applied to the amplifier inputs, amplifier A1s output will eq

44、ual +5 V, plus the common-mode voltage, and A2s output will be 5 V, plus the common-mode voltage. If the amplifiers are operating from 15 V supplies, they will usually have 7 V or so of headroom left, thus permitting an 8 V common-mode voltagebut not the full 12 V of CMV which, typically, would be a

45、vailable at unity gain (for a 10 mV input). Higher gains or lower supply voltages will further reduce the common-mode voltage range.The Basic 2-Op Amp Instrumentation AmplifierFigure 2-6 is a schematic of a typical 2-op amp in-amp circuit. It has the obvious advantage of requiring only two, rather t

46、han three, operational amplifiers and providing savings in cost and power consumption. However, the nonsymmetrical topology of the 2-op amp in-amp circuit can lead to several disadvantages, most notably lower ac CMRR, compared to the 3-opamp design, limiting the circuits usefulness.The transfer func

47、tion of this circuit isVOUT = (VIN2 VIN1) (1 + R4/R3)for R1 = R4 and R2 = R3Figure 2-6. A 2-Op Amp In-Amp CircuitTable 2-1. Operating Gains of Amplifiers A1 and A2 and Practical 1% Resistor Values for the Circuit of Figure 2-6Input resistance is high and balanced, thus permitting the signal source t

48、o have an unbalanced output impedance. The circuits input bias currents are set by the input current requirements of the noninverting input of the two op amps, which typically are very low.Disadvantages of this circuit include the inability to operate at unity gain, a decreased common-mode voltage r

49、ange as circuit gain is lowered, and poor ac common-mode rejection. The poor CMR is due to the unequal phase shift occurring in the two inputs, VIN1 and VIN2. That is, the signal must travel through amplifier A1 before it is subtracted from VIN2 by amplifier A2. Thus, the voltage at the output of A1

50、 is slightly delayed or phase-shifted with respect to VIN1. Minimum circuit gains of 5 are commonly used with the 2-op amp in-amp circuit because this permits an adequate dc common-mode input range, as well as sufficient bandwidth for most applications. The use of rail-to-rail (single-supply) amplif

51、iers will provide a common-mode voltage range that extends down to VS (or ground in single-supply operation), plus true rail-to-rail output voltage range (i.e., an output swing from +VS to VS).Table 2-1 shows amplifier gain vs. circuit gain for the circuit of Figure 2-6 and gives practical 1% resist

52、or values for several common circuit gains.2-Op Amp In-AmpsCommon-Mode DesignConsiderations for Single-Supply OperationWhen the 2-op amp in-amp circuit of Figure 2-7 is examined from the reference input, it is apparent that it is simply a cascade of two inverters. Figure 2-7. The 2-Op Amp In-Amp Arc

53、hitectureAssuming that the voltage at both of the signal inputs, VIN1 and VIN2, is 0, the output of A1 will equalVO1 = VREF (R2/R1)A positive voltage applied to VREF will tend to drive the output voltage of A1 negative, which is clearly not possible if the amplifier is operating from a single power

54、supply voltage (+VS and 0 V). The gain from the output of amplifier A1 to the circuits output, VOUT, at A2, is equal toVOUT = VO1 (R4/R3)The gain from VREF to VOUT is the product of these two gains and equalsVOUT = (VREF (R2/R3)(R4/R3)In this case, R1 = R4 and R2 = R3. Therefore, the reference gain

55、is +1, as expected. Note that this is the result of two inversions, in contrast to the noninverting signal path of the reference input in a typical 3-op amp in-amp circuit. Just as with the 3-op amp in-amp, the common-mode voltage range of the 2-op amp in-amp can be limited by single-supply operatio

56、n and by the choice of reference voltage. Figure 2-8 is a schematic of a 2-op amp in-amp operating from a single 5 V power supply. The reference input is tied to VS/2 which, in this case, is 2.5 V. The output voltage should ideally be 2.5 V for a differential input voltage of 0 V and for any common-

57、mode voltage within the power supply voltage range (0 V to 5 V).Figure 2-8. Output Swing Limitations of 2-Op Amp In-Amp Using a 2.5 V ReferenceAs the common-mode voltage is increased from 2.5 V toward 5 V, the output voltage of A1 (VO1) will equalVO1 = VCM + (VCM VREF) (R2/R1)In this case, VREF = 2.

58、5 V and R2/R1 = 1/4. The output voltage of A1 will reach 5 V when VCM = 4.5 V. Further increases in common-mode voltage obviously cannot be rejected. In practice, the input voltage range limitations of amplifiers A1 and A2 may limit the in-amps common-mode voltage range to less than 4.5 V.Similarly, as the common-mode voltage is reduced from 2.5 V toward 0 V, the output voltage of A1 will hit zero for a VCM of 0.5 V. Clearly, the output