頻率補償研究心得

1、Research on Multistage Amplifier Frequency Compensation 概括放大器為模擬設(shè)計中的核心功能模塊。 CMOS 技術(shù)下低電壓使得多級成為必然, 頻率補 償用于保證良好的頻率特性。 目前所提出的幾乎所有的頻率補償技術(shù)都是基于 NMC 和 RNMC , 并且圍繞著這兩種補償方式在高穩(wěn)定性, 快速暫態(tài)響應, 低功耗, 芯片面積等方面進行優(yōu)化。 經(jīng)過對頻率補償?shù)难芯?建立了理論框架,熟悉了各種補償電路 , 完成了初期的理論積 累, 為后期進行深入研究奠定了良好基礎(chǔ)。 在這篇文章里, 我將著重談?wù)勎覍Ω鞣N補償電路 的研究體會和理解認識,簡要推導電路極零點

2、表達式并大概介紹一下其頻率特性。電路分析一、 (NMC Nest Miller Compensation Fig 1.Nest Miller CompensationIn the three stage NMC topology, there are two Miller capacitors Cm1and Cm2connected from the output to the output of each stage, respectively. There is a large capacitive load which makes the pole at the output very

3、close to the dominant pole at the output of the first stage. Both poles are located at low frequency, posing a great threat to the stability of the amplifier. Pole-splitting using compensation capacitors and pole-zero cancellation using feed-forward paths seem to be the obvious solutions to remove t

4、he effect of the pole. The use of a feed-forward path to cancel this pole is risky because an imperfect pole-zero cancellation at low frequencies creates a pole-zero doublets and deteriorates the settling time of the amplifier. This leaves us with the only choice of pole splitting using a Miller com

5、pensation capacitor. That is why almost all the frequency compensation scheme based on NMC add a capacitor between the output of the first and third stage。The Miller capacitors Cm1and Cm2form two negative feedback loops to stabilize the amplifier but seriously reduce the high frequency gain. As a re

6、sult, extra power is needed to compensate this gain reduction. Moreover, the Miller capacitor Cm2that shorts the last stage gives the additional disadvantages that the phase shift reaches 180°as frequency increases, leading to a positive feedback loop involving Cm1, gm2, and Cm2, which is a ser

7、ious source of instability. Therefore, the trans-conductance gm3must be large enough to counter this shorting effect, thus, it is not suited for low-power applications.To analyze the stability of the NMC amplifier, the small signal transfer function of the NMC amplifier shown in Fig.1 will be invest

8、igated.首先分析一下我對極點的直觀認識。 極點反映在波特圖上, 即為增益曲線的拐點。 從能量的角度看, 電容能量耗散隨著頻率升高而加劇。 從電壓角度看, 電容阻抗隨頻率升高而降 低導致每一級輸出阻抗降低。從電流角度看,頻率升高,使電容吸取信號流的能力增強,而 電阻呈現(xiàn)出相對高阻抗。 極點的物理意義可以理解為電阻電容分流的臨界點。 在低頻處, 高 頻極點電容分流低于電阻,故電容可看作開路,信號流近似全部流經(jīng)電阻,形成直流增益。 在高頻處,低頻極點電容分流高于電阻,故電容可看作短路,信號流近似全部流經(jīng)電容,進 行能量耗散。對圖 Fig.1所示 NMC 的極點進行直觀分析。 首先每一級的輸出寄

9、生電容遠小于所連接的 補償電容,故可看作開路。在主極點 P0附近,高頻點處的電容 Cm2, CL看作開路,信號流過對 地電阻形成高電壓增益, Vout =gm2R2gm3RLVA。 A 點相對 OUT 點可近似看作零電位, OUT 點通過 Cm1向 A 注入信號流 Vout sCm1,該值應等于 A 點通過到地電阻的分流。因此有 VAgm2R2gm3RLsCm1=VAR1 (1 即為 P0=1gm2R2gm3RLCm1R1 (2 在此基礎(chǔ)上,當頻率繼續(xù)升高, Cm1看作短路,兩端近似等電位。當頻率升高至第一次 極點 P1時, B 點達到電阻電容分流臨界點。 我們利用 gm2激發(fā)的信號流全部流經(jīng)

10、 Cm2的近似關(guān) 系得到次極點 gm2VA=sCm2VA(3 即為 P1=gm2Cm2 (4 再分析第二次極點 P2,電容 Cm2兩端電位近似相等。由 gm3激發(fā)的信號全部流經(jīng)負載電 容 CL。對點 OUT 點有 gm3VB=VBsCL(5 即為 P2=gm3CL (6 以上直觀的分析方法避免了繁瑣的計算, 可以很快地得到極點表達式, 不過有一定誤差。 接下來,我將提出更精確的分析方法。該方法可以便利地計算出次極點及零點表達式。 上面的論述中已經(jīng)分析過多級頻率補償普遍采用彌勒電容分離 P0和 P2。 因此幾乎在所有 的補償電路中主極點都具有相同的表達方式,如式 (2。因此我們需要分析的是三級放

11、大器 中兩個次極點。在次級點頻率范圍內(nèi), Cm1兩端近似等電位。電容分流占主導,電阻近似看 作開路。只剩下跨導和補償電容,利用 A 與 OUT 近似等電位的關(guān)系可以列出下式gm2VA+(gm2VAsCm2+VA (gm3 =VAsCL(7 With the assumption of gm3 gm2, equation (7 can be simplified as1+sCm2 gm2 +s2CLCm2gm2gm3=0(8接下來再分析電路的零點。 零點的頻率范圍遠高于主極點, 和上面原理相似。 我們將輸 出電位置零,則有g(shù)m1Vin*1+gm2 sCm1 (1+gm3sCm2+=0(9即為 s

12、2Cm1Cm2+sCm2gm2 gm2gm3=0(10 From equation (10, since there are one RHP zero and one LHP zero, and the RHP zero locates at a lower frequency. It is known that the RHP zero degrades the stability significantly, although it was not taken into account in the early literature, for low-voltage low-power C

13、MOS designs the removal of the right-half-plane (RHP zero is mandatory. There are many methods to eliminate the RHP zero and improve the bandwidth. The methods involve using voltage buffer and current buffer, a nulling resistor, and MZC technique.From another aspect, to ensure stability, the last st

14、age trans-conductance gm3required in a three stage NMC amplifier is given bygm3 4(2GBWCL(11Apparently, in a NMC amplifier, the required trans-conductance for the last stage alone is four times the trans-conductance for a single-stage amplifier. It is thus not suited for low-power applications. Obvio

15、usly, this power consuming effect is mainly caused by the inner Miller capacitor Cm2. The first Miller capacitor Cm1causes the slope to be -20dB per decade in frequency, as in any amplifier. Hence, it is the second Miller capacitor Cm2which causes an unnecessary reduction in high-frequency gain such

16、 that a large trans-conductance gm3is needed for the last stage.Based on these considerations, it becomes clear that taking away the inner Miller capacitor Cm2could be a possible way to achieving better performance. However in this case the first non-dominant pole would be determined by parasitic ca

17、pacitances, resulting in layout-sensitive circuits. Moreover, a safe gain margin would not be ensured due to the effects of the zeros caused by the parasitic capacitances. Besides, since the second stage dc gain AV2appears in the expression of the first non-dominant pole as a multiplier to other par

18、ameters, the sensitivity must be high.For sake of comparison, the case that the inner Miller capacitor is excluded from the three-stage NMC topology is discussed and presented in the next section.二、 UMC (Unique Miller Compensation Fig 2.Single Miller CompensationThe case that the inner Miller capaci

19、tor is excluded from the three-stage NMC topology is referred to as Unique Miller Compensation (UMC, which is shown in Fig.2. The function of the gmfis to implement a push-pull output stage to improve the slewing performance.First the pole will be analyzed, as there is no Miller capacitor at the out

20、put of the second stage, signal will flow directly to ground through output conductance. We can obtaingm2gm3sC2+go2 gmf=sCL(12 極點表達式為s2CLC2+s(CLgo2+gmfC2 +gmfgo2+gm2gm3=0(13 With the assumption of CLgo2 gmfC2, gm2gm3 gmfgo2, we haves2CLC2+sCLgo2+gm2gm3=0(14First non-dominant pole P1=gm3gm2 CLgo2 =AV

21、2gm3CL(15Second non-dominant pole P2=go2 C2 =1Ro2C2(16Although C2is a lumped parasitic capacitance, the second non-dominant pole P2cannotbe kept high since the second-stage output resistance Ro2 is large with regard to the other small equivalent resistance 1/gm. Consequently, this results in a compl

22、ex-pole arrangement for the non-dominant poles.Then analysis the zero point: 1+1sCm(gmf+gm2gm3sC2+go2=0 (17 Calculate ass2CmC2+s(Cmgo2 gmfC2 gmfgo2 gm2gm3=0(18In the unity-feedback configuration, to ensure a third-order Butterworth frequency response with the damping ratio =12Q=0.707, the stability

23、conditions are given byGBW =12P1=12AV2gm3CL=14P2=141Ro2C2(19Clearly, the stability conditions given by (19 are hard to maintain, since both AV2 and Ro2 cannot be accurately specified. They are greatly dependent on the operating points of the relevant transistors. Moreover, the lumped parasitic capac

24、itance C2, which is also imprecise, can inevitably lead to vulnerable layout-dependent circuits. In conclusion, with the three imprecise values: AV2, Ro2, and C2, the stability condition (19 cannot be reliably ensured in practical implementations. Even if the feed-forward stage gmf is taken into acc

25、ount, the effects of the imprecise parameters are still in existence. As such the problem remains unsolved. Therefore, other topologies have to be devised. 三、DFCFC1 (Damping Factor Control Frequency Compensation Fig 4.Damping Factor Control Frequency Compensation(gmVin+i RL=vin i1sCm(20With the assu

26、mption of gmRL 1, we can obtaini =1+gmRLRL+mVin gmRLRL+mVin(21若有 RL 1sCm , 則 i =gmRLsCmVin; 若有 RL 1sCm , 則 i =gmVin, 相當于大小為 1gm 的電阻。直觀上理解為當頻率低于極點時,信號流大部分由 RL到地,形成較大的電壓 增益,從而輸入點相對輸出點可看作零電位,從輸出通過 Cm向輸入注入信號流 sCmVout。當 頻率高于極點時, Cm阻抗變得足夠小,以至于 gm激發(fā)的信號流近似全部流過 Cm, RL相當于開路。有個疑問,在此 DFC 中需要屏蔽負載,使信號只流過 gm和 Cm。方

27、式有兩種,一種是提 升負載,形成低頻極點,如此在高頻下低頻極點電容分流占主導,電阻看作開路。但另一種 理解方法為降低負載,通過內(nèi)部負反饋環(huán)路穩(wěn)定 DFC 內(nèi)部直流點,使輸出直流恒定,可看 作交流地,從而負載被屏蔽,不再有信號通過?；蛘呃斫鉃槔媒档驮鲆婕夹g(shù)使 DFC block 輸出近似為交流地,但為保證 gm的控制作用,其增益不能低于 1,即內(nèi)部環(huán)路增益不能高 于 DFC 本身增益。這兩者間有何關(guān)聯(lián)之處? iDFCFC1基于 SMC 在第二級輸出增加了 DFC 模塊。有效地改善了 UMC 穩(wěn)定性控制不足 的問題。該模塊的頻率特性我們已經(jīng)在前面討論過,等效為跨導為 gm4的壓流源或阻值為 1g

28、m4 的特殊阻抗。 特殊性在于該阻抗不影響原電路低頻直流增益, 而是通過分流作用有效 控制電路穩(wěn)定性。故在分析次級點時可將 UMC 中 go2替換為 gm4,由于 gm4 go2,故有效 增強了對阻尼系數(shù)的控制。改寫極點表達式 (13式和零點表達式 (18式如下s2CLCp2+s(CLgm4+gmfCp2 +gmfgm4+gm2gmL=0 (22 s2Cm1Cp2+s(Cm1gm4 gmfCp2 gmfgm4 gm2gmL=0 (23With the assumption of CL Cp2,分別化簡得 極點表達式 1+s CLgm4gmfgm4+gm2gmL+s2CLCp2gmfgm4+gm

29、2gmL(24 零點表達式1+sgmfCp2Cm1gm4gmfgm4+gm2gmL s2Cm1Cp2gmfgm4+gm2gmL(25由假設(shè)條件 Cm1 Cp2,式 (25的 s1項為負,可能引入低頻正零點,于穩(wěn)定性不利。該低頻正零點為 Z = gmfgm4+gm2gmLgmfCp2Cm1gm4 gmLCm1(1+gm2gm4=gmLgm1gm1Cm1(1+gm2gm4(26 即為Z =gmLgm1(1+gm2gm4(27為保證不受 RHP ZERO影響,需要 Z 提升至 10GBW 處,由式 (27,將增大功耗。若忽略零點影響,由三級巴特沃斯頻率響應得gm4=(Cp2CLgm3(28nulln

30、ullnull路增益降低，導致等效電阻升高，性能惡化。另一方面即為反饋回路內(nèi)部穩(wěn)定性的問題，反 饋越深，補償難度越大。還有就是反饋回路可能引入低頻極零點，這將有可能影響外部系統(tǒng) 穩(wěn)定性。 基于 current buffer 的補償方式還有若干變形，如 DLPC 10，原理很簡單，為了提高帶 寬，去掉內(nèi)層彌勒電容并增加阻尼系數(shù)控制。 頻率補償用途很廣， 不僅用于放大器設(shè)計， 還用于反饋回路， LDO 的回路補償， 如 current buffer 中的反饋回路補償?shù)取?Conclusion 此次研究頻率補償，一方面是作為 Linear Voltage Regulator 的延伸，另一方面也是為今

31、 后研究更復雜的回路頻率補償?shù)於ɑA(chǔ)。 反饋回路一方面涉及反饋理論， 另一方面涉及頻率 特性，如穩(wěn)定性和暫態(tài)特性?；芈吩陔娐废到y(tǒng)中無處不在，小到放大器，大到鎖相環(huán)，從內(nèi) 部模塊的局部回路，到系統(tǒng)級的大回路，環(huán)環(huán)相扣，因此對于反饋回路頻率特性的分析極其 重要。從小信號和大信號，靜態(tài)和動態(tài)，穩(wěn)定和震蕩（VCO） ，不同的角度進行分析。另外 基于反饋回路的噪聲抑制問題也很重要。這些在今后的學習中都要仔細分析，加以深化。 Reference 1 Song Guo, Hui Lee, ”Single-Capacitor Active-Feedback Compensation for Small Cap

32、acitive Load Three-Stage Amplifiers,” IEEE Trans. Circuits and Systems, vol.56, pp758-762, 2009. 2 A. Pugliese, G. Cappuccino, G. Coorullo, “Nested Miller compensation capacitor sizing rules for fast-settling amplifier design,” IEEE Electronic Letters, vol.41, pp.573-575, 2005. 3 J. Ramos, P. Xiaohong, “Three Stage Amplifier Frequency Compensation,” IEEE J. Solid-State Circuits, pp.365-368, 2003. 4 Ka Nang Leung, Mok, P. K. T, “Three stage large capacitive load amplifier with damping factor control frequency compensation,” I