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1、 畢業(yè)設(shè)計(jì)(論文 外文資料翻譯系別：專(zhuān)業(yè)：班級(jí)：姓名：學(xué)號(hào)：外文出處：附件：2014年03月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of its major features for a developer new to the device. Future articles will examine other aspe

2、cts of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known a

3、s "THUMB". This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions,

4、 the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip "embedded ICE" th

5、at allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instr

6、uctions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data. In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages; FETCH,

7、 DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance. As we

8、shall see later the ARM 7 designers had some clever ideas to solve this problem. Instruction Fig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmer's model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (PC. Since the ARM 7 is

9、a load-and- store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.M1M2M34, R 1,R 2 (R4=R0+R2 3Fig 2 Load And Store ArchitectureAs stat

10、ed above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions

11、 that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the "link register". When a call is made to a procedure, the return add

12、ress is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 intoR15, the PC. For multiple calling trees, the contents of R14 (the link register must be placed onto the stack. 15 User registers +PCR13 is used as

13、 the stack pointerR14 is the link registerR14 is the Program CounterCurrent Program Status Register Fig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR. This contains a set of condition code flags in the upper four bits that record the

14、result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts. 31 30 29 28 27Negative Carry OverflowIRQ System User

15、Undefined instructionAbortThumb instruction setFig 4 Current Program Status Register and Flags Exception And Interrupt ModesThe ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interruptsources and the

16、ir own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated. FIQ: (Fast Interrupt reQuest This supports high speed interrupt handling. Generally it is used for a single critical

17、 interrupt source in a systemIRQ: (Interrupt ReQuest This supports all other interrupt sources in a system Supervisor: A "protected" mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after resetAbort: If an instruction or data is fetched from

18、 an invalid memory region, an abort exception will be generatedUndefined Instruction:If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the u

19、ser registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一the saved program stat

20、us register (SPSR，is added. When the processor changes the current value of the CPSR stored in the SPSR，this can be restored on exiting the exception mode. System&UserFIQ Supervisor Abort IRQ Undefined Fig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector

21、table. Exceptions in the ARM processor can be split into three distinct types.(i Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii Exceptions caused as a side effect of an instruction such as a abort caus

22、ed by trying to fetch data from an invalid memory region.(iii Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode,

23、the current value of the PC+4 is saved into the Link register (R14 of the privileged mode and the current value of CPSR is saved into the privileged mode's SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter

24、 is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to push Prefetch Abort(instruction fetch memory abortSoftware interrupt (SWIUndefined instructionResetData Abort (data access momory abortIRQ (interruptFIQ

25、(fast interruptSupervisor Undefined Supervisor Abort Abort IRQ FIQ0x000000000x0000001C0x000000040x0000000C 0x000000080x000000100x00000018Fig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM

26、 architecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possib

27、le.Once processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR must be restored from the SPSR and finally the Program Counter is restored

28、by moving the contents of the link register to R15, (i.e. the Program Counter. The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instr

29、uction set has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format. ARM instructions typically have a three-operand format, as shown belowADD Rl，R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors th

30、ere is a small group of instructions that are conditionally executed depending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.COND31 28Fig. 7 Instruction Condition Code BitsThe top f

31、our bits of each instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional b

32、ranches of three instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used. Fig. 8 Instruction Condition CodesThus our ADD instruction below could be prefixed with a condition code, as shown. This adds no overhead to in

33、struction executionEQADD R1，R2，R3 ;If(Zero flag = 1then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. This takes place in the same cycle as the instruction. The ADD instruction could be expanded a

34、s followsEQADD R1，R2 R3，LSL #2 ; If ( Zero flag = 1 then R1 = R2+ (R3 x 4 Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1，R2 R3，LSL #2; If (Zero flag = 1 then R1 = R2 + (R3 x4and set condition code flagsIn the ARM instruction set t

35、here are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions.The standard branch (B instruction allows a jump of around+-32Mb. A conditional branch can be formed by use of the condition codes. For example, a "branch notequ

36、al" would be the branching instruction B and the condition code "NE" for not equal giving "BNE". The next form of the branch instruction is the branch with link. This is the branch instruction but the current value of the PC +4 is saved into R14, the link register. This acts

37、 as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on the type of exception, it may be necessary to modify the c

38、ontents of the link register to get the correct return address. For example, in the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+

39、4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address. This can be done in a single instruction thus: SUBS pc, r14, #4/ PC=Link register-4 0x80000x400PC=0x80000x4000x8000Fig 9 Branch and Branch Link In

40、struction OperationBranching instructions are also used to enter the 16-bit Thumb instruction set. Both the branch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb ins

41、tructions. Branch link exchange will jump to a location, save PC+4 into the link register and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processin

42、g. 0x8000T=1Y=10x4000x4000x8000Fig. 10 Branch Exchange and Branch Link Exchange Instruction Operation Software InterruptsThe ARM instruction set has a software interrupt instruction. Execution of this instruction forces an exception as described above; the processor will enter supervisor mode and ju

43、mp to the SWI vector at 0x00000008.Fig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal. On execution of an SWI instruction, this ordinal can be examined to determine which SWI procedure to run and gives over 16 million possible

44、SWI functions.Swi_ #1 . call swi function oneTn the swi handlerregister unsigned*link ptr asm ("r14"；/ define a pointer to the hnk register Switch (*(link-ptr-1&Ox00FFFFFF /calculate the number of the swi functionCase 0x01 : SWI_unction (; /Call the functionThis can be used to provide

45、a hardware abstraction layer. In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are therunning in a supervisor mode, with a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM

46、7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless tosay, this is extremely useful when entering or exiting a procedure. M0 Fig. 12 Load and Store Multiple Instruction OperationThe

47、CPSR and SPSR are only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.MSR MRSR15 R15Fig. 13 Programming The SPSR And CPSR Registers THUMB SupportThe ARM processor is capable of executing both 32-bit (ARM instructi

48、ons and 16- Bit (Thumb instructions. The Thumb instruction set must always be entered byrunning a Branch exchange or branch link exchange instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they a

49、re unconditionally executed except though for branch instructions. Fig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一Rl5. A instructions can access the full register set. Fig.15 Thumb programmers modelThe Thumb instruction

50、set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except that the ordin

51、al field is only 8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSR is restored the, Thumb bit will be reset and the processor continues to run Thumb instructi

52、ons. BCX BXFig.16 Thumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you only have 16-bit wide memory then Thumb code will be

53、 faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7的體系結(jié)構(gòu)介紹 特里沃馬丁曾，鼠 技術(shù)總監(jiān)本文給出了ARM 7架構(gòu)的概述和開(kāi)發(fā)新的設(shè)備，以及主要功能的描述，未來(lái)將研究ARM 體系結(jié)構(gòu)的其他方面。 基本特點(diǎn)ARM7單片機(jī)原理的特點(diǎn)是，它是一個(gè)基于寄存器的加載和存儲(chǔ)與多個(gè)操作模式的體系結(jié)構(gòu)。ARM7是一個(gè)32位單片機(jī)，它也能夠運(yùn)行16位指令集，被稱(chēng)為“拇指”。 這有助于實(shí)現(xiàn)

54、一個(gè)更大的代碼密度和加強(qiáng)節(jié)能。而所有的寄存器到寄存器的數(shù)據(jù)處理的指令都是單周期指令，如數(shù)據(jù)傳送指令，多周期。增加這些指令的性能，ARM7具有三級(jí)管道。由于與低門(mén)數(shù)設(shè)計(jì)的固有的簡(jiǎn)單性，ARM7的低功耗處理在瓦/ MIP基礎(chǔ)行業(yè)是領(lǐng)導(dǎo)者。最后，以協(xié)助開(kāi)發(fā)，ARM 內(nèi)核有一個(gè)內(nèi)置的JTAG 調(diào)試端口和芯片上的“嵌入式冰”，允許程序被下載和全面調(diào)試系統(tǒng)。為了保持ARM 既簡(jiǎn)單又劃算，代碼和數(shù)據(jù)區(qū)域通過(guò)單數(shù)據(jù)總線訪問(wèn)。因此ARM7能夠單循環(huán)執(zhí)行所有的數(shù)據(jù)處理指令，數(shù)據(jù)傳送指令可能需要幾個(gè)周期，因?yàn)樗麄儗⑿枰辽賰蓚€(gè)訪問(wèn)總線（一個(gè)是指令一個(gè)是數(shù)據(jù)）。為了提高性能，三個(gè)管道被用于允許多個(gè)指令同時(shí)處理。這個(gè)管

55、道有三個(gè)階段：接收，編譯，執(zhí)行。每一個(gè)階段的硬件設(shè)計(jì)是獨(dú)立的，三個(gè)指令能夠同時(shí)地被執(zhí)行。在迅速上升的連續(xù)代碼中，此管道是最有效的。然而一個(gè)分支指令會(huì)導(dǎo)致管道的性能被破壞。我們必須看到后來(lái)的ARM7設(shè)計(jì)師提出一些聰明的辦法來(lái)解決這些事情。指令 圖1 ARM7的三個(gè)階段管道ARM 7程序設(shè)計(jì)模型程序設(shè)計(jì)員的ARM7模型由15個(gè)用戶(hù)寄存器組成，如圖3所示，R15被用做為程序設(shè)計(jì)器，自從ARM7作為下載和存儲(chǔ)建筑學(xué)以后，用戶(hù)程序必須從CPU 暫存器下載數(shù)據(jù)，執(zhí)行的數(shù)據(jù)和存儲(chǔ)的結(jié)果返回到寄存器，不像其他的處理器沒(méi)有記憶存儲(chǔ)器指令可用。 圖4 當(dāng)前程序狀態(tài)注冊(cè)和標(biāo)記異常和中斷模式ARM7體系結(jié)構(gòu)模式有總數(shù)

56、為6個(gè)不同的運(yùn)行模式，如下面所示。這些模式被保護(hù)或者異常模式有相關(guān)的中斷源和自己的寄存器組。用戶(hù)模式：這個(gè)模式是用于運(yùn)行代碼應(yīng)用。一旦在用戶(hù)模式下的操作不能被寫(xiě)入和模式只能改變時(shí)，生成一個(gè)異常?？焖僦袛嗄Ｊ剑褐С指咚偃僦袛嗵幚?，通常在系統(tǒng)中用作單信號(hào)臨界中斷源。 外部中斷模式：支持系統(tǒng)中的所有中斷源。管理模式：運(yùn)行系統(tǒng)級(jí)別的代碼訪問(wèn)硬件或者操作系統(tǒng)調(diào)用運(yùn)行“保護(hù)”模式。ARM7復(fù)位后進(jìn)入此模式。數(shù)據(jù)訪問(wèn)終止模式：如果一條命令或者數(shù)據(jù)從無(wú)效的記憶區(qū)域中取出，異常終止便產(chǎn)生。未定義指令：如果接收的操作碼不是ARM 指令，未定義的指令異常就會(huì)產(chǎn)生。 用戶(hù)寄存器R0-R7對(duì)所有的運(yùn)行模式都是相同的。

57、然而當(dāng)進(jìn)入快速中斷模式后，快速中斷模式有自己的R8-R14來(lái)代替用戶(hù)寄存器。同樣地，其他模式相互間有自己的R13和R14，以至于每一個(gè)運(yùn)行模式有自己的唯一的堆棧指針和環(huán)節(jié)注冊(cè)。CPSR 對(duì)所有的模式共用。然而在每一個(gè)異常模式，額外的注冊(cè)已保存的程序狀態(tài)寄存器，被添加了。當(dāng)處理器改變當(dāng)前的CPSR ，保存在SPSR ，可以從異常模式中修復(fù)。31 30 29 28 27復(fù)數(shù)攜帶溢出系統(tǒng)用戶(hù)未定義指令中止 ARM 指令系統(tǒng)支持6種數(shù)據(jù)類(lèi)型，也就是8位有符號(hào)和無(wú)符號(hào)，16位有符號(hào)和無(wú)符號(hào)，加上32位有符號(hào)和無(wú)符號(hào)。ARM 處理器指令系統(tǒng)設(shè)計(jì)的目的在于在小規(guī)模地或者大端法的格式支持這些數(shù)據(jù)類(lèi)型，然而大多

58、數(shù)的ARM 硅安裝啟用的是小端格式。ARM 指令典型地有三大操作格式，如下所示ADD R1,R2,R3;R1=R2+R3ARM7程序流控制在所有的處理器有一個(gè)小組，有條件的執(zhí)行取決于一組處理器標(biāo)志指示。這些分支指令，比如分支不相等。在ARM 指令系統(tǒng)中，所有的指令都是有條件的執(zhí)行。31 28 COND圖7 指令條件碼位每個(gè)指令的前四位包含條件代碼，如果要執(zhí)行，指令必須滿足。這有助于消除程序中的小樹(shù)枝和消除攤點(diǎn)管道，增加整體程序的性能。從而為三個(gè)或更少的小條件分支指令，有條件指令的執(zhí)行必須被用到。對(duì)于較大的跳躍，應(yīng)該用正常的分支指令。 圖8 指令條件代碼因此，我們添加下面的指令可能條件碼前綴，如下所示。這增加了沒(méi)有指令執(zhí)行的開(kāi)銷(xiāo)EQADD R1，R2，R3 ;If(Zero flag = 1then R1 = R2+R3ARM 處理器同樣有一個(gè)32位的柱式移位器，在數(shù)據(jù)處理指令中允許轉(zhuǎn)移或循環(huán)其中一個(gè)操作數(shù)。這發(fā)生在和指令相同的循環(huán)。加法指令可以如下擴(kuò)展EQADD R1，R2 R3，LSL #2 ; If ( Zero flag = 1 then R1 = R2+ (R3 x 4 最后的程序設(shè)計(jì)員可能決定在CPSR 中如果特定的指令可以設(shè)置狀態(tài)碼標(biāo)志。EQADDS R1，R2 R3，LSL #2; If (Zero flag = 1 then R1 = R2 + (R3 x4