數(shù)據(jù)采集系統(tǒng)的設(shè)計(jì)

1、概述在電子設(shè)計(jì)技術(shù)領(lǐng)域，可編程邏輯器件(如PLD, GAL)的應(yīng)用，已有了很好的普及。這些器件為數(shù)字系統(tǒng)的設(shè)計(jì)帶來極大的靈活性。由于這類器件可以通過軟件編程而對(duì)其硬件的結(jié)構(gòu)和工作方式進(jìn)行重構(gòu)，使得硬件的設(shè)計(jì)可以如同軟件設(shè)計(jì)那樣方便快捷。這一切極大地改變了傳統(tǒng)的數(shù)字系統(tǒng)設(shè)計(jì)方法、設(shè)計(jì)過程、乃至設(shè)計(jì)觀念。隨著大規(guī)模集成電路技術(shù)和計(jì)算機(jī)技術(shù)的不斷發(fā)展，在涉及通信、國防、航天、醫(yī)學(xué)、工業(yè)自動(dòng)化、計(jì)算機(jī)應(yīng)用、儀器儀表等領(lǐng)域的電子系統(tǒng)設(shè)計(jì)工作中，EDA技術(shù)的含量正以驚人的速度上升;電子類的高新技術(shù)項(xiàng)目的開發(fā)也依賴于EDA技術(shù)的應(yīng)用。即使是普通的電子產(chǎn)品的開發(fā)，EDA技術(shù)常常使一些原來的技術(shù)瓶頸得以輕松突破

2、，從而使產(chǎn)品的開發(fā)周期大為縮短、性能價(jià)格比大幅提高。不言而喻，EDA技術(shù)將迅速成為電子設(shè)計(jì)領(lǐng)域中的極其重要的組成部分。本次設(shè)計(jì)的目的是使用可編程邏輯器件設(shè)計(jì)一個(gè)專用的A/D轉(zhuǎn)換器的控制器，取代常用的微控制器，用于數(shù)據(jù)采集。本文講述對(duì)A/D進(jìn)行數(shù)據(jù)采樣控制。設(shè)計(jì)要求用一片CPLD/FPGA，模數(shù)轉(zhuǎn)換控制器ADC和LED顯示器構(gòu)成一個(gè)數(shù)據(jù)采集系統(tǒng)，用CPLD/FPGA實(shí)現(xiàn)數(shù)據(jù)采集中對(duì)A/D 轉(zhuǎn)換，數(shù)據(jù)運(yùn)算，及有關(guān)數(shù)據(jù)的顯示控制。課題除了學(xué)習(xí)相應(yīng)的硬件知識(shí)外，還要學(xué)習(xí)如何使用VHDL語言設(shè)計(jì)可編程邏輯器件。第一章 設(shè)計(jì)要求本設(shè)計(jì)要求用一片CPLD/FPGA、模數(shù)轉(zhuǎn)換器ADC和數(shù)模轉(zhuǎn)換器DAC構(gòu)成一個(gè)

3、數(shù)據(jù)采集系統(tǒng)，并用CPLD/FPGA實(shí)現(xiàn)數(shù)據(jù)采集中對(duì)A/D轉(zhuǎn)換、數(shù)據(jù)運(yùn)算、D/A轉(zhuǎn)換以及有關(guān)數(shù)據(jù)顯示的控制。 第二章 設(shè)計(jì)方案2.1數(shù)據(jù)采集和控制系統(tǒng)概述數(shù)據(jù)采集和控制系統(tǒng)是對(duì)生產(chǎn)過程或科學(xué)實(shí)驗(yàn)中各種物理量進(jìn)行實(shí)時(shí)采集、測(cè)試和反饋控制的閉環(huán)系統(tǒng)。它在工業(yè)控制、軍事電子設(shè)備、醫(yī)學(xué)監(jiān)護(hù)等許多領(lǐng)域發(fā)揮著重要作用。2.2數(shù)據(jù)采集和控制系統(tǒng)總框圖系統(tǒng)的組成框圖如圖1所示，其功能如下：(1) 系統(tǒng)按一定速率采集輸入電壓U1，經(jīng)ADC0809轉(zhuǎn)換為8位數(shù)字量DATA。(2) 輸入數(shù)據(jù)與通過預(yù)置按鍵輸入數(shù)據(jù)采集控制器內(nèi)的標(biāo)準(zhǔn)數(shù)據(jù)相減，求得帶極性位的差值±U(數(shù)字量)；差值之絕對(duì)值送至DAC0832轉(zhuǎn)

4、換為U，它和特定的極性判別電路共同輸出±U。(3) 數(shù)據(jù)采集和處理均在數(shù)據(jù)采集系統(tǒng)控制器的管理下有序進(jìn)行。工作速率由時(shí)鐘信號(hào)CLK的速率決定。圖1 數(shù)據(jù)采集系統(tǒng)組成框圖2.3數(shù)據(jù)采集和控制系統(tǒng)整體組裝原理圖根據(jù)系統(tǒng)設(shè)計(jì)要求，數(shù)據(jù)采集系統(tǒng)控制器SJCJKZQ可由四個(gè)模塊組成：A/D轉(zhuǎn)換控制模塊ADZHKZ、數(shù)據(jù)運(yùn)算與處理模塊SJYSCL、D/A轉(zhuǎn)換控制模塊DAZHKZ以及有關(guān)鍵盤輸入與數(shù)據(jù)顯示控制模塊JPXSKZ，其組成框圖及有關(guān)接口如圖2所示。 圖2 數(shù)據(jù)采集系統(tǒng)總體組成原理圖第三章 設(shè)計(jì)思路數(shù)據(jù)采集系統(tǒng)控制器SJCJKZQ可由四個(gè)模塊組成：A/D轉(zhuǎn)換控制模塊ADZHKZ、數(shù)據(jù)運(yùn)算與

5、處理模塊SJYSCL、D/A轉(zhuǎn)換控制模塊DAZHKZ以及有關(guān)鍵盤輸入與數(shù)據(jù)顯示控制模塊JPXSKZ。3.1 A/D轉(zhuǎn)換控制模塊ADZHKZ ADC0809是CMOS的8位A/D轉(zhuǎn)換器，片內(nèi)有8路模擬開關(guān)，可控制8個(gè)模擬量中的一個(gè)進(jìn)入轉(zhuǎn)換器中。ADC0809的分辨率為8位，轉(zhuǎn)換時(shí)間約100 s，含鎖存控制的8路多路開關(guān)，輸出由三態(tài)緩沖器控制，單5 V電源供電。圖3是ADC0809的管腳及主要控制信號(hào)時(shí)序圖。 圖4是ADZHKZ模塊生成的符號(hào)。圖3 ADC0809的管腳及主要控制信號(hào)時(shí)序圖圖4 ADZHKZ模塊符號(hào)對(duì)于ADC0809模數(shù)轉(zhuǎn)換的控制程序段的VHDL設(shè)計(jì)，根據(jù)ADC0809的A/D轉(zhuǎn)換

6、控制要求，我們可用一個(gè)狀態(tài)機(jī)來實(shí)現(xiàn)，其狀態(tài)轉(zhuǎn)換如圖5所示。 圖5 狀態(tài)轉(zhuǎn)換圖3.2數(shù)據(jù)運(yùn)算與處理模塊SJYSCL 表1是在ADC0809的基準(zhǔn)電壓(Vref)為5.12 V時(shí)，模擬輸入電壓與輸出電壓的對(duì)應(yīng)關(guān)系表，其中最小電壓準(zhǔn)位是5/28=5/256=0.2 V。 這樣，當(dāng)由ADC0809的D7.0收到的數(shù)據(jù)信號(hào)是10000110(即86H)時(shí)，則對(duì)照表8.1時(shí)，高4位1000是2.56 V，而低4位0110是0.12 V，所以最后的電壓輸出結(jié)果是2.56 V+0.12 V=2.68 V。表1 ADC0809模擬輸入電壓與輸出電壓的對(duì)應(yīng)關(guān)系 圖6 BCD加法示意圖 圖7 SJYSCL模塊符號(hào)為

7、了方便后續(xù)的電壓數(shù)據(jù)顯示，我們應(yīng)將輸出電壓表示成12位的BCD碼形式。如上述的2.56 V是0010 0101 0110，0.12 V是0000 0001 0010，所以相加的結(jié)果2.68 V是0010 0110 1000，因此必須設(shè)計(jì)一個(gè)12位的BCD碼加法程序。 上圖是2.56+0.18=2.74的二進(jìn)制的BCD加法示意圖。從圖6中可以看出，二進(jìn)制BCD碼相加時(shí)，由最低位4位加起，且每4位相加的結(jié)果超過10時(shí)需作進(jìn)位操作。圖7是SJYSCL生成的符號(hào)3.3 D/A轉(zhuǎn)換控制模塊DAZHKZDAC0832是采樣頻率為八位的D/A轉(zhuǎn)換芯片，集成電路內(nèi)有兩級(jí)輸入寄存器，使DAC0832芯片具備雙緩

8、沖、單緩沖和直通三種輸入方式，以便適于各種電路的需要。圖8 DAC0832內(nèi)部結(jié)構(gòu)圖DAC0832的內(nèi)部結(jié)構(gòu)如圖8所示。DAC0832中有兩級(jí)鎖存器，第一級(jí)鎖存器稱為輸入寄存器，它的鎖存信號(hào)為ILE；第二級(jí)鎖存器稱為DAC寄存器，它的鎖存信號(hào)為傳輸控制信號(hào) 。因?yàn)橛袃杉?jí)鎖存器，DAC0832可以工作在雙緩沖器方式，即在輸出模擬信號(hào)的同時(shí)采集下一個(gè)數(shù)字量，這樣能有效地提高轉(zhuǎn)換速度。此外，兩級(jí)鎖存器還可以在多個(gè)D/A轉(zhuǎn)換器同時(shí)工作時(shí)，利用第二級(jí)鎖存信號(hào)來實(shí)現(xiàn)多個(gè)轉(zhuǎn)換器同步輸出。圖9是DAZHKZ模塊生成的符號(hào)。3.4 鍵盤輸入與數(shù)據(jù)顯示控制模塊JPXSKZ鍵盤輸入與數(shù)據(jù)顯示控制模塊JPXSKZ各主

9、要功能模塊:時(shí)序產(chǎn)生電路，鍵盤掃描電路，抖動(dòng)消除電路，鍵盤譯碼電路，按鍵存儲(chǔ)電路。時(shí)序產(chǎn)生電路，由于設(shè)計(jì)需要不止一個(gè)時(shí)鐘，若輸入是ClK，N位計(jì)數(shù)器的輸出位QN-l坷，則Q(0)為CLK的2分頻脈沖，Q(3)為CLK電路16分頻脈沖，Q(N-1)為2頻。Q(5downto4)其脈沖序列是00-0110-11-00-01周期變化，其頻率為CLK的32分頗。由此可得到設(shè)計(jì)中所需要的頻率。鍵盤掃描電路用來產(chǎn)生掃描信號(hào)，掃描信KY32KYO按照1110-1101-1011-0111-1110的規(guī)律依次變化，通過輸出KX22KXO來檢測(cè)是否有鍵接下，如掃描信號(hào)示1101，表示正在掃描4，5，6這三個(gè)鍵，

10、如果這三個(gè)鍵多沒被按下，則KX2:0輸出為Ill，如果數(shù)字鍵4按下，口2:0將會(huì)輸出為011。按鍵位置與數(shù)碼關(guān)系如表2 所示，圖10是JPXSKZ模塊生成的符號(hào)。圖9 DAZHKZ模塊符號(hào) 圖10 JPXSKZ模塊符號(hào)表2按鍵位置與數(shù)碼關(guān)系 KY30 1110 1110 1110 1101 1101 1101 1111 1011 0111 0111 0111 0111KX20 011 101 110 011 101 110 101 101 110 011 101 110按鍵值 1 2 3 4 5 6 7 8 9 * 0 #第四章 VHDL源程序4.1 A/D轉(zhuǎn)換控制模塊ADZHKZ的VHDL源

11、程序 -ADZHKZ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADZHKZ IS PORT(D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); RST: IN STD_LOGIC; -復(fù)位信號(hào) CLK: IN STD_LOGIC; -轉(zhuǎn)換工作時(shí)鐘信號(hào) EOC: IN STD_LOGIC; -0809的轉(zhuǎn)換結(jié)束控制信號(hào) ALE: OUT STD_LOGIC; -0809的通道選擇地址鎖存信號(hào) START: OUT STD_LOGIC; -080

12、9的轉(zhuǎn)換啟動(dòng)控制信號(hào) OE: OUT STD_LOGIC; -0809的輸出使能控制信號(hào) ADDA: OUT STD_LOGIC; -0809的通道選擇控制信號(hào) BCDOUT: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END ENTITY ADZHKZ; ARCHITECTURE ART OF ADZHKZ IS TYPE STATES IS (ST0，ST1，ST2，ST3，ST4，ST5，ST6); SIGNAL CURRENT_STATE，NEXT_STATE: STATES; SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO

13、 0); SIGNAL LOCK0，LOCK1: STD_LOGIC; -轉(zhuǎn)換后數(shù)據(jù)輸出鎖存時(shí)鐘信號(hào) SIGNAL VALUE: STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL CEN: STD_LOGIC; SIGNAL ALE0: STD_LOGIC; SIGNAL START0: STD_LOGIC; SIGNAL OE0: STD_LOGIC; BEGIN -A/D轉(zhuǎn)換控制模塊 STATESYSTEM: BLOCK IS BEGIN ADDA<='1' -狀態(tài)轉(zhuǎn)換控制 PRO: PROCESS(CURRENT_STATE，EOC) IS

14、 BEGIN CASE CURRENT_STATE IS WHEN ST0=>ALE0<='0' START0<='0' OE0<='0' LOCK0<='0' NEXT_STATE<=ST1; CEN<='0' WHEN ST1=>ALE0<='1' START0<='0' OE0<='0' LOCK0<='0' NEXT_STATE<=ST2; CEN<='

15、0' WHEN ST2=>ALE0<='0' START0<='1' OE0<='0' LOCK0<='0' NEXT_STATE<=ST3; CEN<='0' WHEN ST3=>ALE0<='0' START0<='0' OE0<='0' LOCK0<='0' CEN<='0' IF EOC='1' THEN -測(cè)試EOC的下降沿

16、NEXT_STATE<=ST3; ELSE NEXT_STATE<=ST4; END IF; WHEN ST4=>ALE0<='0' START0<='0' OE0<='0' LOCK0<='0' CEN<='0' IF EOC='0' THEN NEXT_STATE<=ST4;-測(cè)試EOC的上升沿，=1表明轉(zhuǎn)換結(jié)束 ELSE NEXT_STATE<=ST5; END IF; WHEN ST5=>ALE0<='0'

17、; START0<='0' OE0<='1' LOCK0<='0' NEXT_STATE<=ST6; CEN<='1' WHEN ST6=>ALE0<='0' START0<='0' OE0<='1' LOCK0<='1' NEXT_STATE<=ST0; CEN<='0' WHEN OTHERS=>ALE0<='0' START0<='0

18、' OE0<='0' LOCK0<='0' NEXT_STATE<=ST0; CEN<='0' END CASE; END PROCESS; PROCESS(RST, CLK) BEGIN IF RST='1' THEN CURRENT_STATE<=ST0 ELSIF RISING_EDGE(CLK) THEN CURRENT_STATE<=NEXT_STATE; -在時(shí)鐘上升沿，轉(zhuǎn)換至下一狀態(tài) END IF; END PROCESS; -用于給輸出信號(hào)去毛刺 PROCESS(CLK)

19、 BEGIN IF RISING_EDGE(CLK) THEN ALE<=ALE0; START<=START0; OE<=OE0; LOCK1<=LOCK0; END IF; END PROCESS; -數(shù)據(jù)鎖存進(jìn)程 PROCESS(LOCK1) BEGIN IF RISING_EDGE(LOCK1) THEN REGL<=D; -在LOCK1的上升沿，將轉(zhuǎn)換好的數(shù)據(jù)鎖入END IF; END PROCESS; END BLOCK STATESYSTEM; -A/D轉(zhuǎn)換數(shù)據(jù)的BCD碼轉(zhuǎn)換模塊 CONVERSION: BLOCK IS SIGNAL V: STD_

20、LOGIC_VECTOR(7 DOWNTO 0); SIGNAL HB，LB: STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL C30，C74，C118: STD_LOGIC; SIGNAL TEMPA，TEMPB，TEMPC: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS(REGL) IS BEGIN V<=REGL; -將A/D轉(zhuǎn)換后的高4位通過查表的方式用12位BCD碼表示 CASE V(7 DOWNTO 4) IS -FOR A/D CONVERSION DATA HIGHT BYTEWHEN "11

21、11" =>HB<="010010000000" -4.80 WHEN "1110" =>HB<="010001001000" -4.48 WHEN "1101" =>HB<="010000010110" -4.16 WHEN "1100" =>HB<="001110000100" -3.84 WHEN "1011" =>HB<="001101010010&

22、quot; -3.52 WHEN "1010" =>HB<="001100100000" -3.20 WHEN "1001" =>HB<="001010001000" -2.88 WHEN "1000" =>HB<="001001010110" -2.56 WHEN "0111" =>HB<="001000100100" -2.24 WHEN "0110" =>H

23、B<="000110010010" -1.92 WHEN "0101" =>HB<="000101100000" -1.60 WHEN "0100" =>HB<="000100101000" -1.28 WHEN "0011" =>HB<="000010010110" -0.96WHEN "0010" =>HB<="000001100100" -0.64 WHEN

24、 "0001" =>HB<="000000110010" -0.32 WHEN OTHERS =>HB<="000000000000" -0.00 END CASE; -將A/D轉(zhuǎn)換后數(shù)據(jù)的低4位用12位BCD碼表示 CASE V(3 DOWNTO 0) IS -FOR A/D CONVERSION DATA LOW BYT WHEN "1111" =>LB<="000000110000" -0.30 WHEN "1110" =>LB

25、<="000000101000" -0.28 WHEN "1101" =>LB<="000000100110" -0.26 WHEN "1100" =>LB<="000000100100" -0.24 WHEN "1011" =>LB<="000000100010" -0.22WHEN "1010" =>LB<="000000100000" -0.20 WHEN

26、"1001" =>LB<="000000011000" -0.18 WHEN "1000" =>LB<="000000010110" -0.16 WHEN "0111" =>LB<="000000010100" -0.14 WHEN "0110" =>LB<="000000010010" -0.12 WHEN "0101" =>LB<="00000

27、0010000" -0.10 WHEN "0100" =>LB<="000000001000" -0.08 WHEN "0011" =>LB<="000000000110" -0.06 WHEN "0010" =>LB<="000000000100" -0.04 WHEN "0001" =>LB<="000000000010" -0.02 WHEN OTHERS =>LB&

28、lt;="000000000000" -0.00 END CASE; END PROCESS; -將A/D轉(zhuǎn)換后高低4位的12位BCD碼進(jìn)行加法操作處理 PROCESS(HB，LB，CEN) IS VARIABLE TEMP1，TEMP2，TEMP3: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RISING_EDGE(CEN) THEN TEMP1: =HB(3 DOWNTO 0)+LB(3 DOWNTO 0); IF TEMP1>"1001" THEN TEMP1: =TEMP1+"0110"

29、; TEMP2: =HB(7 DOWNTO 4)+LB(7 DOWNTO 4)+'1' IF TEMP2>"1001" THENTEMP2: =TEMP2+"0110" TEMP3: =HB(11 DOWNTO 8)+LB(11 DOWNTO 8)+'1' IF TEMP3>"1001" THEN TEMP3: =TEMP3+"0110" END IF; ELSE TEMP3: =HB(11 DOWNTO 8)+LB(11 DOWNTO 8); IF TEMP3>&

30、quot;1001" THEN TEMP3: =TEMP3+"0110" END IF; END IF; ELSETEMP2: =HB(7 DOWNTO 4)+LB(7 DOWNTO 4); IF TEMP2>"1001" THEN TEMP2: =TEMP2+"0110" TEMP3: =HB(11 DOWNTO 8)+LB(11 DOWNTO 8)+'1' IF TEMP3>"1001" THEN TEMP3: =TEMP3+"0110" END IF;

31、 ELSE TEMP3: =HB(11 DOWNTO 8)+LB(11 DOWNTO 8); IF TEMP3>"1001" THEN TEMP3: =TEMP3+"0110" END IF; END IF; END IF; END IF; VALUE<=TEMP3&TEMP2&TEMP1; END PROCESS; -將經(jīng)過BCD碼轉(zhuǎn)換處理后的數(shù)據(jù)輸出 BCDOUT<=VALUE; END BLOCK CONVERSION; END ARCHITECTURE ART; 4.2 數(shù)據(jù)運(yùn)算與處理模塊SJYSCL的VHDL源

32、程序 -SJYSCL.VHDLIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SJYSCL IS PORT(CLK: IN STD_LOGIC; DABC: IN STD_LOGIC_VECTOR(11 DOWNTO 0); DTA: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DTB: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DTC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); QABC: OUT STD_L

33、OGIC_VECTOR(11 DOWNTO 0); END ENTITY SJYSCL; ARCHITECTURE ART OF SJYSCL IS SIGNAL DA，DB，DC: STD_LOGIC_VECTOR(3 DOWNTO 0); -DA IS THE HIGHEST BIT，DC THE LAST ONE SIGNAL DDA，DDB，DDC: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN DA<=DABC(11 DOWNTO 8); DB<=DABC(7 DOWNTO 4); DC<=DABC(3 DOWNTO 0); DDA<

34、=DTA(3 DOWNTO 0); DDB<=DTB(3 DOWNTO 0); DDC<=DTC(3 DOWNTO 0); PROCESS IS VARIABLETEMPA，TEMPB，TEMPC: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN WAIT UNTIL CLK='1' ; IF DA>DDA THEN IF DB>DDB THEN IF DC>=DDC THENTEMPC: =DC-DDC; TEMPB: =DB-DDB; TEMPA: =DA-DDA; ELSE TEMPC: ="1010&quo

35、t;-DDC+DC; IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: =DB-'1'-DDB; TEMPA: =DA-DDA; END IF; ELSIF DB=DDB THEN IF DC>=DDC THEN TEMPC: =DC-DDC; TEMPB: =DB-DDB; TEMPA: =DA-DDA; ELSE TEMPC: ="1010"-DDC+DC; IF TEMPC>"1001" THEN TEMPC:

36、=TEMPC+"0110" ; END IF; TEMPB: ="1010"-DDB-'1'+DB; IF TEMPB>"1001" THENTEMPB: =TEMPB+"0110" END IF; TEMPA: =DA-'1'-DDA; END IF; ELSE IF DC>=DDC THEN TEMPC: =DC-DDC; TEMPB: ="1010"-DDB+DB; IF TEMPB>"1001" THEN TEMPB:

37、 =TEMPB+"0110" END IF; TEMPA: =DA-'1'-DDA; ELSETEMPC: ="1010"-DDC+DC; IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: ="1010"-'1'-DDB+DB; IF TEMPB>"1001" THEN TEMPB: =TEMPB+"0110" END IF; TEMPA: =DA-

38、'1'-DDA; END IF; END IF; ELSIF DA=DDA THENIF DB>DDB THEN IF DC>=DDC THEN TEMPC: =DC-DDC; TEMPB: =DB-DDB; TEMPA: =DA-DDA; ELSE TEMPC: ="1010"-DDC+DC; IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: =DB-'1'-DDB; TEMPA: =DA-DDA; END IF; EL

39、SIF DB=DDB THEN IF DC>=DDC THEN TEMPC: =DC-DDC; TEMPB: =DB-DDB; TEMPA: =DA-DDA; ELSE TEMPC: =DDC-DC; TEMPB: =DDB-DB; TEMPA: =DDA-DA; END IF; ELSEIF DDC>=DC THEN TEMPC: =DDC-DC; TEMPB: =DDB-DB; TEMPA: =DDA-DA; ELSE TEMPC: ="1010"-DC+DDC; IF TEMPC>"1001" THEN TEMPC: =TEMPC

40、+"0110" END IF; TEMPB: =DDB-'1'-DB; TEMPA: =DDA-DA; END IF; END IF; ELSE IF DDB>DB THEN IF DDC>=DC THEN TEMPC: =DDC-DC; TEMPB: =DDB-DB; TEMPA: =DDA-DA; ELSE TEMPC: ="1010"-DC+DDC; IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: =DDB-&

41、#39;1'-DB; TEMPA: =DDA-DA; END IF; ELSIF DDB=DB THEN IF DDC>=DC THEN TEMPC: =DDC-DC; TEMPB: =DDB-DB; TEMPA: =DDA-DA; ELSE TEMPC: ="1010"-DC+DDC; IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: ="1010"-'1'-DB+DDB; IF TEMPB>"10

42、01" THEN TEMPB: =TEMPB+"0110" END IF; TEMPA: =DDA-'1'-DA; END IF; ELSE IF DDC>=DC THEN TEMPC: =DDC-DC; TEMPB: ="1010"-DC+DDC; IF TEMPB>"1001" THEN TEMPB: =TEMPB+"0110" END IF; TEMPA: =DDA-'1'-DA; ELSE TEMPC: ="1010"-DC+DDC;

43、 IF TEMPC>"1001" THEN TEMPC: =TEMPC+"0110" END IF; TEMPB: ="1010"-'1'-DB+DDB; IF TEMPB>"1001" THEN TEMPB: =TEMPB+"0110" END IF; TEMPA: =DDA-'1'-DA; END IF; END IF; END IF; QABC(11 DOWNTO 8)<=TEMPA; QABC(7 DOWNTO 4)<=TEMPB;

44、 QABC(3 DOWNTO 0)<=TEMPC; END PROCESS; END ARCHITECTURE ART; 4.3 D/A轉(zhuǎn)換控制模塊DAZHKZ的VHDL源程序-DAZHKZ.VHDLIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DAZHKZ IS PORT(DATA_IN: IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK: IN STD_LOGIC; KK: IN S

45、TD_LOGIC; RST: IN STD_LOGIC; DATA_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END ENTITY DAZHKZ; ARCHITECTURE ART OF DAZHKZ IS SIGNAL TEMPG: INTEGER RANGE 0 TO 9; -BCDG SIGNAL TEMPS: INTEGER RANGE 0 TO 9; -BCDS SIGNAL TEMPB: INTEGER RANGE 0 TO 9; -BCDB SIGNAL TEMP: INTEGER RANGE 0 TO 255; SIGNAL DATA: ST

46、D_LOGIC_VECTOR(7 DOWNTO 0); BEGINTEMPG<=CONV_INTEGER(DATA_IN(3 DOWNTO 0); TEMPS<=CONV_INTEGER(DATA_IN(7 DOWNTO 4); TEMPB<=CONV_INTEGER(DATA_IN(11 DOWNTO 8); TEMP<=TEMPB*100+TEMPS*10+TEMPG; PROCESS(KK，TEMP，CLK) BEGIN IF RST='1' THEN DATA<=(OTHERS=>'0'); ELSIF RISING_

47、EDGE(CLK) THENDATA<=CONV_STD_LOGIC_VECTOR(TEMP，8); IF KK='1' THEN DATA_OUT<=DATA; ELSE NULL; END IF; END IF; END PROCESS; END ARCHITECTURE ART; 4.4 鍵盤輸入與數(shù)據(jù)顯示控制模塊JPXSKZ的VHDL源程序-JPXSKZ.VHDLIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JPXSKZ IS PORT(BC

48、DOUT: IN STD_LOGIC_VECTOR(11 DOWNTO 0); KEYC: IN STD_LOGIC; KEY: IN STD_LOGIC; QA: IN STD_LOGIC_VECTOR(11 DOWNTO 0); DATAOUT: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); END ENTITY JPXSKZ; ARCHITECTURE ART OF JPXSKZ IS SIGNAL STATE: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL QQA: STD_LOGIC_VECTOR(11 DOWNTO 0); BEG

49、IN CHOSEKEY: PROCESS(KEYC) IS VARIABLE TEMP: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINIF RISING_EDGE(KEYC) THEN IF TEMP="10" THEN TEMP: ="00" ELSE TEMP: =TEMP+'1' END IF; END IF; STATE<=TEMP; END PROCESS CHOSEKEY ; CHOSEDISPLAY: PROCESS(STATE) IS BEGIN CASE STATE ISWHEN &quo

50、t;00"=>DATAOUT<=QQA; WHEN "01"=>DATAOUT<=BCDOUT; WHEN "10"=>DATAOUT<=QA; WHEN OTHERS=>NULL; END CASE; END PROCESS CHOSEDISPLAY; KEYBOARD: PROCESS(KEY，STATE) IS VARIABLE TEMPA，TEMPB，TEMPC: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN WAIT UNTIL KEY='1' IF

51、STATE="00" THENIF TEMPA="1001" THEN TEMPA: ="0000" TEMPB: =TEMPB+'1' IF TEMPB="1001" THEN TEMPB: ="0000" TEMPC: =TEMPC+'1' IF TEMPC="1001" THEN TEMPC: ="0000" END IF; END IF; ELSE TEMPA: =TEMPA+'1' END IF; ELSE NULL; END IF; QQA(11 DOWNTO 8)<=TEMPC; QQA(7 DOWNTO 4)<=TEMPB; QQA(3 DOWNTO 0)<=TE