程序?qū)嵗?：MFSK調(diào)制VHDL程序及仿真

1、MFSK調(diào)制VHDL程序及仿真-文件名:PL_MFSK-功能:基于VHDL硬件描述語(yǔ)言,完成對(duì)基帶信號(hào)的MFSK調(diào)制-說(shuō)明:這里MFSK的M為4-最后修改日期:2004.2.13library ieee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PL_MFSK isport(clk :in std_logic; -系統(tǒng)時(shí)鐘start :in std_logic; -開始調(diào)制信號(hào)x :in std_logic; -基帶信號(hào)y :out std_lo

2、gic; -調(diào)制信號(hào)end PL_MFSK;architecture behav of PL_MFSK issignal q :integer r a nge 0 t o 15; -計(jì)數(shù)器signal f :std_logic_vector(3 downto 0; -分頻器signal xx:std_logic_vector(1 downto 0; -寄存輸入信號(hào)x的2位寄存器signal yy:std_logic_vector(1 downto 0; -寄存xx信號(hào)的寄存器beginprocess(clk -此進(jìn)程過(guò)對(duì)clk進(jìn)行分頻,得到4種載波信號(hào)f3、f2、f1、f0。beginif c

3、lk'event and clk='1' thenif start='0' then f<="0000"elsif f="1111" then f<="0000"else f<=f+1;end if;end if;end process;process(clk -對(duì)輸入的基帶信號(hào)x進(jìn)行串/并轉(zhuǎn)換,得到2位并行信號(hào)的yy beginif clk'event and clk='1' thenif start='0' then q<=0;

4、elsif q=0 then q<=1;xx(1<=x;yy<=xx;elsif q=8 then q<=9;xx(0<=x;else q<=q+1;end if;end if;end process;process(clk,yy -此進(jìn)程完成對(duì)輸入基帶信號(hào)x的MFSK調(diào)制beginif clk'event and clk='1' thenif start='0' then y<='0' - if語(yǔ)句完成2位碼并行碼到4種載波的選通elsif yy="00" then y<=not f(3;elsif yy="01" then y<=not f(2;elsif yy="10" then y<=not f(1;else y<=not f(0;end if;end if;end process;end behav;3. MFSK調(diào)制VHDL程序仿真圖及注釋MFSK調(diào)制VHDL程序仿真圖及注釋如圖8.13.4所示。 (aMFSK調(diào)制VHDL程序仿真全圖 注:中間信號(hào)yy與輸出調(diào)制信號(hào)y的對(duì)應(yīng)關(guān)系:“00”=f3;“01”=f2;“10”=f1;“11