基于VHDL的FIR數(shù)字濾波器

1、本報(bào)告分兩局部：1 由matlab計(jì)算FIR數(shù)字濾波器的濾波系數(shù)；2 用VHDL語(yǔ)言設(shè)計(jì)邏輯電路，再通過(guò)QUARTUS II 軟件，將各個(gè)模塊的電路封裝成期間，在頂層設(shè)計(jì)中通過(guò)連線，完成整個(gè)系統(tǒng)。所有源程序在本文檔同一文件夾下的fir文件中。FIR數(shù)字濾波器的系數(shù)計(jì)算。這里通過(guò)MATLAB的Fdatool軟件實(shí)現(xiàn)。輸入數(shù)據(jù)S(n)為9位，輸出y(n)為10位的低通濾波器數(shù)據(jù)：各個(gè)參數(shù)如下：Lilter Typer lowpass FIR Window kaiser階數(shù)：15，濾波類型為：直接型FIRFIR濾波器的幅頻響應(yīng)相頻響應(yīng)FIR濾波器的沖擊響應(yīng)濾波器系數(shù)對(duì)系數(shù)進(jìn)行調(diào)整，整數(shù)化：Num =

2、0.3594 0.8281 0.8281 0.3594 0.0977 -0.1758 Num*(28)ans = Columns 1 through 10 Columns 11 through 16FIR數(shù)字濾波器的VHDL實(shí)現(xiàn)根據(jù)作業(yè)要求，S(n)為9位，y(n)為10位的低通濾波器。數(shù)據(jù)：-19,6,29,3,-45,-25,92,212,212,92,-25,-45,3,29,6,-19階數(shù)：15， 濾波類型為：直接型FIR FIR濾波器的原理圖設(shè)計(jì)如下： 設(shè)計(jì)原理：一 概要我的原理說(shuō)明是根據(jù)上面原理圖的設(shè)計(jì)順序逐步進(jìn)行的。1 存放器延時(shí)器。 原理圖上標(biāo)有dff9的器件。輸入9位數(shù)據(jù)，通

3、過(guò)dff9的D觸發(fā)存放器，到達(dá)延時(shí)的作用。2 第一級(jí)加法器 數(shù)據(jù)通過(guò)add9910,就是9位數(shù)字輸入，10位數(shù)字輸出加法器，完成第一級(jí)相加運(yùn)算，因?yàn)榇祟}是16階FIR數(shù)字濾波器，它的濾波系數(shù)有對(duì)稱的關(guān)系，所以采用上面的第一級(jí)加法器，到達(dá)簡(jiǎn)化運(yùn)算的效果。3 乘法器乘法器用來(lái)將數(shù)據(jù)乘以由matlab計(jì)算得到的濾波系數(shù)，此題的系數(shù)分別為：-19,6,29,3,-45,-25,92,212。在乘法器設(shè)計(jì)時(shí)暫時(shí)沒(méi)有考慮符號(hào)，符號(hào)問(wèn)題由下面的減法器實(shí)現(xiàn)。即：假設(shè)系數(shù)符號(hào)為負(fù)，那么在下一級(jí)用減法器減去乘法器所得的數(shù)據(jù)。所有的乘法器為：mult19, mult mult 6, mult 29, mult 3,

4、 mult 45, mult 25, mult 92, mult 212。4 第二級(jí)加，減法器第二級(jí)加法器主要有add111414,add151415,add161717。add111414就是說(shuō)11位數(shù)據(jù)加14位數(shù)據(jù)輸出14位數(shù)據(jù)，說(shuō)有的都是相同的命名規(guī)那么。減法器的作用是反映乘法器的負(fù)號(hào)的，對(duì)于負(fù)的濾波系數(shù)，在此相當(dāng)于經(jīng)過(guò)減法器相減。5 第三級(jí)加，減法器與上一級(jí)大體相同的原理。6 輸出輸出通過(guò)add141710，將上一級(jí)得到的14位和17位數(shù)據(jù)相加，再拿出相加結(jié)果的高十位作為輸出。到此，整個(gè)FIR數(shù)字濾波器設(shè)計(jì)完畢，下面詳細(xì)說(shuō)明各個(gè)局部的具體實(shí)現(xiàn)。二 詳細(xì)說(shuō)明 我的說(shuō)明是根據(jù)上面的概要逐一

5、展開(kāi)的。我的設(shè)計(jì)是先編寫(xiě)各個(gè)功能的vhdl源文件，再生成功能模塊，最后在頂層用原理圖的設(shè)計(jì)方法連線，組成整個(gè)系統(tǒng)。1 存放器延時(shí)器 設(shè)計(jì)中用D觸發(fā)器組成存放器，實(shí)現(xiàn)存放功能。這里用來(lái)存放一組9位的二進(jìn)制數(shù)據(jù)。實(shí)現(xiàn)功能：在CP正跳沿前接受輸入信號(hào)，正跳沿時(shí)觸發(fā)翻轉(zhuǎn)，正跳沿后輸入即被封鎖。源文件：ENTITY dff9 IS PORT( clk : IN STD_LOGIC; clear : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(8 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) ); END dff9

6、; ARCHITECTURE a OF dff9 IS BEGIN PROCESS(clk,clear) BEGIN IF clear='1' THEN Dout<="000000000" ELSIF clear='0' THEN IF(clk'EVENT AND clk='1') THEN Dout <= Din; END IF; END IF; END PROCESS; END a;2 第一級(jí)加法器 實(shí)現(xiàn)兩個(gè)二進(jìn)制數(shù)字的相加運(yùn)算。當(dāng)?shù)竭_(dá)時(shí)鐘上升沿時(shí)，將兩數(shù)輸入，運(yùn)算，輸出結(jié)果。源文件：LIBRARY I

7、EEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;ENTITY add9910 isPORT(clk : in STD_LOGIC; Din1,Din2 :in signed (8 downto 0); Dout:out signed(9 downto 0);END add9910;ARCHITECTURE a of add9910 isSIGNAL s1: signed(9 downto 0);SIGNAL s2: signed(9 downto 0);BEGIN s1<=(Din1(8)&Din1); s

8、2<=(Din2(8)&Din2);PROCESS(Din1,Din2,clk)BEGINif clk'event and clk='1' thenDout<=s1+s2;end if;end process;end a;3 乘法器功能：將數(shù)據(jù)乘以由matlab計(jì)算得到的濾波系數(shù)?？偣灿?個(gè)乘法器。源文件以mult19為例：LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ENTITY mult19 isPORT( clk : IN STD_LOGIC; Din

9、 : IN SIGNED (9 DOWNTO 0); Dout : OUT SIGNED (13 DOWNTO 0);END mult19;ARCHITECTURE a OF mult19 ISSIGNAL s1 : SIGNED (13 DOWNTO 0);SIGNAL s2 : SIGNED (10 DOWNTO 0);SIGNAL s3 : SIGNED (13 DOWNTO 0);BEGINP1:process(Din)BEGINs1(13 DOWNTO 4)<=Din;s1( 3 DOWNTO 0)<="0000"s2(10 DOWNTO 1)<

10、=Din;s2(0)<='0'if Din(9)='0' then s3<=('0'&s1(13 downto 1)+("0000"&s2(10 DOWNTO 1)+("00000"&Din(9 DOWNTO 1);else s3<=('1'&s1(13 downto 1)+("1111"&s2(10 DOWNTO 1)+("11111"&Din(9 DOWNTO 1);end if;e

11、nd process;P2: PROCESS(clk)BEGINif clk'event and clk='1' thenDout<=s3;end if;END PROCESS;END a;4 第二級(jí)加，減法器 對(duì)于乘了濾波系數(shù)的數(shù)據(jù)，進(jìn)行第二次的加和，由于上面有的濾波系數(shù)是負(fù)的，所以這里用減法器對(duì)上一面的負(fù)系數(shù)做減法運(yùn)算。源程序：減法器-sub121414LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;ENTITY sub121414 isPORT(clk : in ST

12、D_LOGIC; Din1 :in signed (13 downto 0); Din2 :in signed (11 downto 0); Dout:out signed(13 downto 0);END sub121414;ARCHITECTURE a of sub121414 isSIGNAL s1: signed(13 downto 0);BEGIN s1<=(Din2(11)&Din2(11)&Din2);PROCESS(Din1,Din2,clk)BEGINif clk'event and clk='1' thenDout<=s1

13、-Din1;end if;end process;end a;加法器- add111414LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;ENTITY add111414 isPORT(clk : in STD_LOGIC; Din1 :in signed (10 downto 0); Din2 :in signed (13 downto 0); Dout:out signed(13 downto 0);END add111414;ARCHITECTURE a of add111414 isSIGNAL

14、 s1: signed(13 downto 0);BEGIN s1<=(Din1(11)&Din1(11)&Din1(11)&Din1);PROCESS(Din1,Din2,clk)BEGINif clk'event and clk='1' thenDout<=s1+Din2;end if;end process;end a;還有add151415,add161717略5 第三級(jí)加，減法器功能同上： 加法器-add141415源代碼：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.S

15、TD_LOGIC_arith.ALL;ENTITY add141415 isPORT(clk : in STD_LOGIC; Din1 :in signed (13 downto 0); Din2 :in signed (13 downto 0); Dout:out signed(14 downto 0);END add141415;ARCHITECTURE a of add141415 isSIGNAL s1: signed(14 downto 0);SIGNAL s2: signed(14 downto 0);BEGIN s1<=(Din1(13)&Din1); s2<

16、=(Din1(13)&Din1);PROCESS(Din1,Din2,clk)BEGINif clk'event and clk='1' thenDout<=s1+s2;end if;end process;end a;減法器sub171517源代碼：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;ENTITY sub171517 isPORT(clk : in STD_LOGIC; Din1 :in signed (14 downto 0); Din2 :in s

17、igned (16 downto 0); Dout:out signed(16 downto 0);END sub171517;ARCHITECTURE a of sub171517 isSIGNAL s1: signed(16 downto 0);BEGIN s1<=(Din1(14)&Din1(14)&Din1);PROCESS(Din1,Din2,clk)BEGINif clk'event and clk='1' thenDout<=Din2-s1;end if;end process;end a;6 輸出級(jí)輸出通過(guò)一個(gè)加法器add15

18、1710完成10位數(shù)據(jù)的輸出，通過(guò)一個(gè)15位與一個(gè)17位數(shù)據(jù)相加得到的數(shù)據(jù)取高10為作為最終結(jié)果。源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_arith.ALL;ENTITY add151710 isPORT(clk : in STD_LOGIC; Din1:in signed (14 downto 0); Din2:in signed (16 downto 0); Dout:out signed(9 downto 0);END add151710;ARCHITECTURE a of add151710 isSIGNAL s1: signed(9 downto 0);SIGNAL s2: signed(9 downto 0);BEGIN s1<=(Din1(13)&Di