Actel的SmartFusion混合信號FPGA開發(fā)評估方

1、    Actel的SmartFusion混合信號FPGA開發(fā)評估方Actel的SmartFusion混合信號FPGA開發(fā)評估方案Actel公司的SmartFusion是集成了FPGA,ARMCortex-M3和可編程模擬的智能混合信號FPGA,非常適合硬件和嵌入系統(tǒng)設(shè)計.本文介紹了SmartFusion混合信號FPGA主要特性,方框圖,以及SmartFusion評估板主要特性,部分電路圖和馬達(dá)控制與工業(yè)自動化的開發(fā)方框圖.ActelsSmartFusionIntelligentMixed-SignalFPGAsaretheonlydevicesthat

2、integrateanFPGA,ARM®Cortex-M3,andprogrammableanaloActel的SmartFusion混合信號FPGA開發(fā)評估方案Actel公司的SmartFusion是集成了FPGA, ARM Cortex-M3和可編程模擬的智能混合信號FPGA,非常適合硬件和嵌入系統(tǒng)設(shè)計.本文介紹了SmartFusion混合信號FPGA主要特性,方框圖, 以及SmartFusion評估板主要特性,部分電路圖和馬達(dá)控制與工業(yè)自動化的開發(fā)方框圖.Actels SmartFusion Intelligent Mixed-Signal FPGAsare the only

3、devices that integrate an FPGA, ARM® Cortex-M3, and programmable analog, offering full customization,IPprotection, and ease-of-use. Based on Actels proprietaryflashprocess, SmartFusion FPGAs areideal for hardware and embedded designers who need a true system-on-chip (SoC) solution that gives

4、 more flexibility than traditional fixed-function microcontrollerswithout the excessive cost of soft processor cores on traditional FPGAs.SmartFusion主要特性:Microcontroller Subsystem (MSS) Hard100 MHz 32-Bit ARM® Cortex-M3 1.25 DMIPS/MHz Throughput from Zero Wait State MemoryMemory Protection Unit

5、 (MPU) Single Cycle Multiplication, Hardware Divide JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces Internal Memory Embedded Nonvolatile Flash Memory (eNVM), 64 Kbytes to 512Kbytes Embedded High-Speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, Implemented i

6、n 2 Physical Blocks to Enable Simultaneous Access from 2 Different Masters Multi-Layer AHB Communications MatrixProvides up to 16 Gbps of On-Chip Memory Bandwidth,1 Allowing Multi-Master Schemes 10/100Ethernet MAC with RMII Interface2 Programmable External Memory Controller,2 Which Supports: Asynchr

7、onous Memories NOR Flash, SRAM, PSRAM Synchronous SRAMs Two I2CPeripherals Two 16550Compatible UARTs Two SPI Peripherals Two 32-Bit Timers 32-Bit Watchdog Timer 8-Channel DMA Controller to Offload the Cortex-M3 from Data Transactions Clock Sources 1.5 MHz to 20 MHz Main Oscillator Battery-Backed 32

8、KHz Low-PowerOscillator with Real-Time Counter (RTC) 100 MHz Embedded RC Oscillator; 1% Accurate Embedded Analog PLL with 4 Output Phases (0, 90, 180, 270)High-Performance FPGA Based on Actels proven ProASIC®3 FPGA Fabric Low-Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based CMOS Proc

9、ess Nonvolatile, Live at Power-Up, Retains Program When Powered Off 350 MHz System Performance Embedded SRAMs and FIFOsVariable Aspect Ratio 4,608-Bit SRAM Blocks x1, x2, x4, x9, and x18 Organizations True Dual-Port SRAM (excluding x18) Programmable Embedded FIFO Control Logic SecureISPwith 128-Bit

10、AES via JTAG FlashLock® to Secure FPGA Contents Five Clock Conditioning Circuits (CCCs) with up to 2 Integrated Analog PLLs Phase Shift, Multiply/Divide, and Delay Capabilities Frequency: Input 1.5350 MHz, Output 0.75 to 350 MHzProgrammable AnalogAnalog Front-End (AFE) Up to Three 12-Bit SAR AD

11、Cs 500 Ksps in 12-Bit Mode 550 Ksps in 10-Bit Mode 600 Ksps in 8-Bit Mode Internal 2.56 V Reference or Optional External Reference One First-Order DAC (sigma-delta) per ADC 12-Bit 500 Ksps Update Rate Up to 5 High-Performance Analog Signal Conditioning Blocks (SCB) per Device, Each Including: Two Hi

12、gh-Voltage Bipolar Voltage Monitors (with 4 input ranges from ±2.5 V to11.5/+14 V) with 1% Accuracy High Gain Current Monitor, Differential Gain = 50, up to 14 V Common Mode Temperature Monitor (Resolution = ¼°C in 12-Bit Mode; Accurate from 55 to 150) Up to Ten High-Speed Voltage Com

13、parators (tpd= 50 ns)Analog Compute Engine (ACE) Offloads Cortex-M3Based MSS from Analog Initialization and Processing of ADC, DAC, and SCBs Sample Sequence Engine for ADC and DAC ParameterSet-Up Post-Processing Engine for Functions such as Low-Pass Filtering and Linear Transformation Easily Configu

14、red via GUI in Libero® Integrated Design (IDE) SoftwareI/Os and Operating Voltage FPGA I/OsLVDS, PCI, PCI-X, up to 24 mA IOH/IOLUp to 350 MHz MSS I/Os Schmitt Trigger, up to 6 mA IOH, 8 mA IOL Up to 180 MHz Digital VCC = 1.5 V (FPGA and MSS), Analog VCC = 3.3 V and 1.5 VSmartFusion intelligent

15、mixed signal FPGAs are uniquely suited for active motor control for permanent magnet motors, servo motors, series motors, separately excited motors, and alternating current (AC) induction motors.圖1.SmartFusion方框圖SmartFusion評估板The SmartFusion Evaluation Kit offers a simple, low-cost way to try the wo

16、rlds only FPGA with hard ARM Cortex-M3 and programmable analog. The SmartFusion device contains on-chip flash and on-chip SRAM memory, and the kit adds additional SPI flash memory, an OLED display, and built in Ethernet connectivity. The evaluation kit board also includes LEDs, switches, and various

17、 voltage, current and temperature monitoring functions for analog experimentation on the board.圖2.SmartFusion評估板外形圖The SmartFusion Evaluation Kit board includes:A2F200M3F-FGG484ES200,000System FPGA gates, 256 KB flash memory, 64 KB SRAM, and additional distributed SRAM in the FPGA fabric and externa

18、l memory controllerPeripherals include Ethernet, DMAs, I2Cs, UARTs, timers, ADCs, DACs and additional analog resourcesRefer to the SmartFusion product page for full device informationSPI-flash memory connected to SPI_0 on the deviceUSBconnection for programming and debug from Actels design toolsUSB

19、to UART connection to UART_0 for HyperTerminal examples10/100 Ethernet interface with on-chip MAC and external PHYRVI header for application programming and debug from either Keil or IAR SystemsMixed-signal header for daughter card supportUser Inputs and OutputsOLED display with I2C interface connec

20、ted to I2C_0 on the deviceFirst-order DAC (sigma delta) output with 12-bit 500 Ksps update ratePotentiometer used to vary voltage input for voltage and current monitoring8 LEDs connected to the FPGA fabric for FPGA demonstration2 user input switches connected through FPGA fabricBoth LEDs and switche

21、s can be used with GPIO by connecting through the fabricSelector to choose between GNU SoftConsole or RVI-Header for debugSelector to switch between programming the device (fabric) and debug modeOn-board 20 MHz crystal for system clockOn-board 32.768 KHz for RTC5 user I/Os for debugOption to use int

22、ernal 1.5 V regulator圖3.SmartFusion評估板的OLED連接圖圖4.SmartFusion評估板的20MHz和32.768kHz振蕩器連接圖圖5.SmartFusion評估板的USB到UART連接圖圖6.SmartFusion評估板的以太網(wǎng)接口連接圖圖7.SmartFusion評估板的低成本編程器連接圖圖8.SmartFusion評估板的A2F200 JTAG連接圖Designing with SmartFusion involves three different types of design: FPGA design, embedded design and

23、 analog design. These roles can be filled by three different designers, two designers, or even a single designer, depending on company structure and project complexity. Actel has developed design tools and flows to meet the needs of these three types of designers so they can work together smoothly o

24、n a single project. FPGA DesignLibero® Integrated Design Environment (IDE) is Actels comprehensive software toolset for designing with all Actel FPGAs. Libero IDE includes industry-leading synthesis, simulation and debug tools from Synopsys® and Mentor Graphics®, as well as innovative

25、 timing and power optimization and analysis. Embedded DesignActel offers FREE SoftConsole Eclipse-based IDE, which includes the GNU C/C+ compiler and GDB debugger. Actel also offers evaluation versions ofsoftware from Keil and IAR, with full versions available from respective suppliers. Analog Desig

26、nThe MSS configurator provides graphical configuration for current, voltage and temperature monitors, sample sequencing setup, and post-processing configuration, as well as DAC output.The MSS configurator creates a bridge between the FPGA and embedded designers so device configuration can be easily

27、shared between multiple developers.圖9.采用SmartFusion的設(shè)計流程連接圖SmartFusion intelligent mixed-signal FPGAs are uniquely suited to active motor control for permanent magnet motors, servo motors, series motors, separately excited motors and alternating current induction motors. A SmartFusion FPGA can activ

28、ely manage multiple electric motors, including start and stop, control of rotational direction, speed and torque, protection against motor overloads or faults and active control using closed loop performance algorithms. SmartFusion on-chip resources allow you to monitor motor performance in real tim

29、e with or without dedicated encoders, applying corrective control signals to maintain commanded direction, speed and torque and deliver precise motor position control.Actels motor control partner, Power and Control Design, Inc., has produced a SmartFusion Motor Control Development Kit that enables d

30、emonstration and benchtop development of your world-class permanent magnet motor control products.The kit includes five reference designs with source files: Trapezoidal using Hall effect sensor feedback Sinusoidal using Hall effect sensor feedback Sinusoidal with encoder feedback Sensorless trapezoidal with back-EMF feedback E