畢業(yè)論文-基于VHDL的頻率計(jì)設(shè)計(jì)

1、基于聲紋的說話人特征識(shí)別JIU JIANG UNIVERSITY 畢 業(yè) 論 文（設(shè) 計(jì)） 題 目 基于VHDL的頻率計(jì)設(shè)計(jì) 英文題目 The frequency meter based on VHDL design 院 系 電子工程學(xué)院 專 業(yè) 電子信息工程 姓 名 年 級(jí) 指導(dǎo)教師 2015年6月 19九江學(xué)院學(xué)士學(xué)位論文摘 要 數(shù)字頻率計(jì)是直接用十進(jìn)制數(shù)字來顯示被測信號(hào)頻率的一種測量裝置。它不僅可以測量正弦波、方波、三角波、尖脈沖信號(hào)，而且還可以測量它們的周期。經(jīng)過改裝，可以測量脈沖寬度，做成數(shù)字式脈寬測量儀；在電路中增加傳感器，還可以做成數(shù)字脈搏儀、計(jì)價(jià)器等。因此數(shù)字頻率計(jì)在測量物理量

2、方面應(yīng)用廣泛。本設(shè)計(jì)用VHDL在CPLD器件上實(shí)現(xiàn)數(shù)字頻率計(jì)測頻系統(tǒng)，能夠用十進(jìn)制數(shù)碼顯示被測信號(hào)的頻率，而且還能對(duì)其他多種物理量進(jìn)行測量。具有體積小、可靠性高、功耗低的特點(diǎn)。采用VDHL編程設(shè)計(jì)實(shí)現(xiàn)的數(shù)字頻率計(jì)，除被測信號(hào)的整形部分、鍵輸入部分和數(shù)碼顯示部分以外，其余全部在一片F(xiàn)PGA芯片上實(shí)現(xiàn)，整個(gè)系統(tǒng)非常精簡，而且具有靈活的現(xiàn)場可更改性。關(guān)鍵字：VHDL語言；頻率計(jì)；FPGA The frequency meter based on VHDL designAbstractDigital frequency meter is directly with a decimal number t

3、o display the measured signal frequency of a measuring device. It not only can measure the sine wave, square wave, triangle wave, pulse signal, but also can measure their cycle. Modified, and can measure pulse width, into a digital pulse width measuring instrument; Add the sensors in the circuit, bu

4、t also can be made into digital pulse apparatus, meter, etc. So the digital frequency meter has been widely applied in measuring physical quantities. This design with VHDL on the CPLD device to realize digital frequency meter frequency measurement and control system, can use decimal digital display

5、measured signal frequency, but also to measure a variety of other physical quantities. With the characteristics of small volume, high reliability, low power consumption. VDHL programming design was adopted to realize digital frequency meter, in addition to the measured signal of the plastic part and

6、 digital display, key input parts, all on a FPGA chip, the whole system is very compact, and with flexible field is modified.Key Words：VHDL language; Frequency meter; FPGA目 錄摘 要IThe frequency meter based on VHDL designIIAbstractII第一章 緒論111課題的研究背景112頻率計(jì)發(fā)展現(xiàn)狀1第2章 數(shù)字頻率計(jì)的要求32.1 主要技術(shù)指標(biāo)32.2 課題的研究內(nèi)容3第3章 數(shù)字頻

7、率計(jì)的方案設(shè)計(jì)43.1 基本原理43.11 頻率計(jì)測量頻率的設(shè)計(jì)原理43.1.2頻率計(jì)測量頻率的原理圖43.2 設(shè)計(jì)流程圖5第4章 數(shù)字頻率計(jì)各模塊功能介紹64.1頻率控制模塊的VHDL語言源程序64.1.1 頻率控制模塊的程序如下：64.1.2 頻率控制模塊CNT1274.2十進(jìn)制加法計(jì)數(shù)器CNT10的VHDL語言源程序74.2.1 十進(jìn)制計(jì)數(shù)器的程序74.2.2 十進(jìn)制計(jì)數(shù)器的頂層設(shè)計(jì)94.3系統(tǒng)模塊的VHDL語言源程序94.3.1系統(tǒng)模塊的設(shè)計(jì)94.3.2 系統(tǒng)模塊的程序94.4 鎖存器LOCK的VHDL語言源程序134.4.1 鎖存器LOCK的程序134.4.2 鎖存器LOCK頂層設(shè)計(jì)

8、圖144.5 譯碼模塊DECODER的VHDL語言源程序154.5.1 譯碼模塊DECODER的程序154.6四選一選擇器MUX41的VHDL語言源程序164.6.1 MUX41程序164.7 四進(jìn)制計(jì)數(shù)器CNT4的VHDL語言源程序174.7.1 四進(jìn)制計(jì)數(shù)器CNT4的程序174.7.2 四進(jìn)制計(jì)數(shù)器CNT4174.8 250分頻器的VHDL語言源程序184.8.1 250分頻器的程序184.8.2 250分頻器18 九江學(xué)院學(xué)士學(xué)位論文第一章 緒論在科技高度發(fā)展的今天，集成電路和計(jì)算機(jī)應(yīng)用得到了高速發(fā)展。尤其是計(jì)算機(jī)應(yīng)用的發(fā)展。它在人們?nèi)粘Ｉ钜阎饾u嶄露頭角。大多數(shù)電子產(chǎn)品多是由計(jì)算機(jī)電路

9、組成。而且將來的不久他們的身影將會(huì)更頻繁的出現(xiàn)在我們身邊。各種家用電器多會(huì)實(shí)現(xiàn)微電腦技術(shù)。頻率信號(hào)易于傳輸，抗干擾性強(qiáng)，可以獲得較好的測量精度。因此，頻率檢測是電子測量領(lǐng)域最基本的測量之一。本數(shù)字頻率計(jì)的設(shè)計(jì)是根據(jù)頻率計(jì)的測頻原理，可以選擇合適的時(shí)基信號(hào)對(duì)輸入被測信號(hào)脈沖進(jìn)行計(jì)數(shù)，實(shí)現(xiàn)測頻的目的。11課題的研究背景 隨著電子電路技術(shù)的發(fā)展，頻率計(jì)從早期的采用分立元件設(shè)計(jì)發(fā)展到后來的采用單元電路和單片機(jī)進(jìn)行設(shè)計(jì)。早期采用分立元件設(shè)計(jì)的頻率計(jì)成品體積大、穩(wěn)定性差、功耗高而且設(shè)計(jì)費(fèi)時(shí)、設(shè)計(jì)周期長，不能很快的將最初的概念設(shè)想轉(zhuǎn)為系統(tǒng)實(shí)現(xiàn)。在數(shù)字電子技術(shù)和集成電路迅速發(fā)展的影響下，數(shù)字頻率計(jì)不但穩(wěn)定性得

10、到了提高而且體積也減小了，得到了廣泛的應(yīng)用。但數(shù)字頻率計(jì)仍然存在很多缺點(diǎn)如電路復(fù)雜、設(shè)計(jì)周期較長、測量范圍有限、靈活性差等等。此外，現(xiàn)代電子產(chǎn)品更新?lián)Q代非常的快，在很短的時(shí)間內(nèi)可能就需對(duì)電路做出相應(yīng)的改進(jìn)以滿足新的功能要求。這對(duì)傳統(tǒng)的通用集成電路來說則需要重新設(shè)計(jì)、重新布線，而可編程邏輯器件的出現(xiàn)克服了這個(gè)缺點(diǎn)?？删幊踢壿嬈骷ㄟ^編程把通用集成電路集成在一塊尺寸很小的硅片上，電路的體積成倍縮小，走線短，減少了干擾，系統(tǒng)的可靠性也得到了提高，而且該類器件重構(gòu)硬件的結(jié)構(gòu)和工作方式可以通過軟件編程的方式實(shí)現(xiàn)，使電子設(shè)計(jì)通過開發(fā)語言和開發(fā)工具就可實(shí)現(xiàn)，體現(xiàn)了硬件電路軟設(shè)計(jì)的思想，硬件設(shè)計(jì)像軟件設(shè)計(jì)一樣

11、靈活、方便快捷，產(chǎn)品的開發(fā)周期也得到了極大的縮短，改變了傳統(tǒng)的數(shù)字系統(tǒng)設(shè)計(jì)方法、設(shè)計(jì)過程和設(shè)計(jì)觀念，也改變了頻率計(jì)的傳統(tǒng)設(shè)計(jì)方法和設(shè)計(jì)觀念。 大規(guī)?？删幊踢壿嬈骷目焖侔l(fā)展，使得SOPC(system Oil programmable chip，片上可編程系統(tǒng))成為可能。界面友好、易學(xué)易用的SOPC集成開發(fā)工具和高效、靈活的片上系統(tǒng)構(gòu)建方案，既獲得了強(qiáng)大的邏輯控制能力又具備了優(yōu)良的數(shù)據(jù)處理能力，實(shí)現(xiàn)了真正意義上的片上可編程系統(tǒng)。SOPC具有信號(hào)處理快、設(shè)計(jì)周期短、成本低、易集成等特點(diǎn)，被稱為“半導(dǎo)體產(chǎn)業(yè)的未來"，這也將成為未來儀器儀表測量系統(tǒng)設(shè)計(jì)的發(fā)展方向。12頻率計(jì)發(fā)展現(xiàn)狀早在19

12、52年美國就生產(chǎn)出了第一臺(tái)數(shù)碼管顯示的10MHz計(jì)數(shù)器。目前國內(nèi)外在頻率測量方面的理論和系統(tǒng)方法都比較成熟，而且電子計(jì)數(shù)器可以實(shí)現(xiàn)頻率、頻率比、周期、時(shí)間間隔、脈寬等多種參數(shù)的測量，早就突破了早期的只能用來測量頻率或進(jìn)行計(jì)數(shù)的概念。目前，頻率計(jì)正向著多功能化、程控化、智能化和模塊化的方向發(fā)展，測量技術(shù)和工具越來越先進(jìn)，測頻儀器的精度也越來越高，而且微波技術(shù)的發(fā)展需要測量越來越高的頻率。例如，泰克推出的最新頻率計(jì)分析儀不僅能夠精確測量出頻率、周期、時(shí)間、脈沖或相位、占空比、Vmax、Vmin、Vp-p等13種以上不同的參數(shù)，還提供數(shù)據(jù)統(tǒng)計(jì)、柱狀圖以及趨勢圖等被測信號(hào)進(jìn)行全面分析的分析模式，而且還

13、能進(jìn)行時(shí)域的Allan方差測試；泰克的FCA3000和FCA3100系列提供了最高達(dá)20GHz的寬頻率范圍，而且實(shí)現(xiàn)了每秒12位數(shù)字頻率分辨率和單次50 ps(FCA3100)或100 ps(FCA3000)的時(shí)間分辨率。程控計(jì)數(shù)器是電信號(hào)的臺(tái)式測量儀表和系統(tǒng)“器件"，而智能計(jì)數(shù)器不僅是以上二者，配備不同的傳感器后可以成為其他的非電量測量儀表。如配備激光測距傳感器可以得到被測距離，配備轉(zhuǎn)速傳感器又可以得到平均轉(zhuǎn)速或瞬時(shí)轉(zhuǎn)速等。在這些情況下，它就變成了測距儀和轉(zhuǎn)速分析儀，一機(jī)多用增加了儀器的靈活度，提高了儀器的利用率、降低了成本、可以減少實(shí)驗(yàn)室儀器的品種數(shù)型。目前，頻率測量的方法有比較

14、測頻法、響應(yīng)測頻法、直接測頻法、內(nèi)插法、游標(biāo)法、多周期同步法、全同步數(shù)字測頻法等等。比較測頻法和響應(yīng)測頻法測量范圍有限而且精度低。直接測頻法方法簡單，但精度不高；內(nèi)插法和游標(biāo)法精度有所提高，但由于采用的是模擬方法，電路設(shè)計(jì)復(fù)雜；精度較高的多周期同步測量法還可以和其他方法如內(nèi)插法、游標(biāo)法等結(jié)合使用，這樣可以在一定的程度上提高測量精度，但沒能消除基準(zhǔn)頻率信號(hào)的±1個(gè)字的計(jì)數(shù)誤差，而且仍然存在著時(shí)標(biāo)不穩(wěn)引入的誤差和一定的觸發(fā)誤差。全同步數(shù)字測頻法徹底消除了被測信號(hào)和基準(zhǔn)頻率信號(hào)的±1個(gè)字的計(jì)數(shù)誤差，精度較高，而且電路實(shí)現(xiàn)也不復(fù)雜。通過對(duì)上述幾種主要測頻方法的簡單介紹可以了解到，每

15、一種測頻方法各有自己的優(yōu)缺點(diǎn)和使用的場合，在不同的應(yīng)用條件下具有一定的優(yōu)勢。本設(shè)計(jì)的頻率計(jì)決定采用在多周期同步測量法的基礎(chǔ)上發(fā)展起來的全同步數(shù)字測頻法進(jìn)行設(shè)計(jì)。第2章 數(shù)字頻率計(jì)的要求在電子技術(shù)中，頻率是最基本的參數(shù)之一，并且與許多電參量的測量方案、測量結(jié)果都有十分密切的關(guān)系，因此頻率的測量就顯得更加重要。2.1 主要技術(shù)指標(biāo)1.頻率范圍為：1Hz50MHz。 2.結(jié)果用數(shù)碼管十進(jìn)制顯示。 3.輸入信號(hào)電壓幅度為50mV5V。2.2 課題的研究內(nèi)容（1）比較分析常用頻率計(jì)的原理和差別，選擇適合本設(shè)計(jì)的設(shè)計(jì)方法。（2）根據(jù)選定的設(shè)計(jì)方法，依自頂而下的設(shè)計(jì)方法對(duì)頻率計(jì)進(jìn)行總體方案的設(shè)計(jì)和模塊的劃分

16、。（3）用VHDL語言對(duì)各個(gè)模塊和頂層電路進(jìn)行設(shè)計(jì)。（4）在QuartusII環(huán)境下對(duì)設(shè)計(jì)進(jìn)行測試和仿真。（5）對(duì)頻率計(jì)的附件電路進(jìn)行設(shè)計(jì)，完成總體的頻率計(jì)設(shè)計(jì)，使其成為一個(gè)完整系統(tǒng)。（6）基于VHDL的頻率計(jì)的方案研究。第3章 數(shù)字頻率計(jì)的方案設(shè)計(jì)6位數(shù)字頻率計(jì)電路的設(shè)計(jì), 應(yīng)用MAX+PLUS軟件平臺(tái), 來說明VHDL語言在EDA仿真中的應(yīng)用。該設(shè)計(jì)實(shí)例的基本功能描述為:3.1 基本原理3.11 頻率計(jì)測量頻率的設(shè)計(jì)原理頻率計(jì)的基本原理是用一個(gè)頻率穩(wěn)定度高的頻率源作為基準(zhǔn)時(shí)鐘，對(duì)比測量其他信號(hào)的頻率。測頻法就是在確定的閘門時(shí)間Tw內(nèi)，記錄被測信號(hào)的變化周期數(shù)（或脈沖個(gè)數(shù)）Nx，則被是信號(hào)的

17、頻率為fx=Nx/Tw 。通常情況下計(jì)算每秒內(nèi)待測信號(hào)的脈沖個(gè)數(shù)，即閘門時(shí)間為1 s。閘門時(shí)間越長，得到的頻率值就越準(zhǔn)確，但閘門時(shí)間越長，則每測一次頻率的間隔就越長。閘門時(shí)間越短，測得的頻率值刷新就越快，但測得的頻率精度就受影響。一般取1 s作為閘門時(shí)間。原理圖： 原理圖3.1.2頻率計(jì)測量頻率的原理圖本設(shè)計(jì)采用FPGA來實(shí)現(xiàn)全同步數(shù)字頻率計(jì)。其系統(tǒng)原理框圖如圖3.1所示。由圖知，設(shè)計(jì)的絕大部分由FPGA完成。 3.2 設(shè)計(jì)流程圖使用MAX+PLUS進(jìn)行可編程邏輯器件開發(fā)主要包括4個(gè)階段：設(shè)計(jì)輸入、編譯處理、驗(yàn)證（包括功能仿真、時(shí)序仿真、和定時(shí)分析）和器件編程，流程如圖2. 1所示：設(shè)計(jì)要求設(shè)

18、計(jì)輸入編譯處理驗(yàn)證器件編程器件測試系統(tǒng)產(chǎn)品設(shè)計(jì)修改圖2.1 設(shè)計(jì)流程圖第4章 數(shù)字頻率計(jì)各模塊功能介紹在原理圖中共有5個(gè)模塊: 頻率控制模塊、十進(jìn)制計(jì)數(shù)器模塊、鎖存模塊、譯碼模塊、系統(tǒng)模塊,我們將利用VHDL語言分別對(duì)這5個(gè)模塊進(jìn)行源程序設(shè)計(jì)。4.1頻率控制模塊的VHDL語言源程序 頻率控制信號(hào)的輸入信號(hào)是1HZ，將時(shí)鐘信號(hào)clk 兩分頻后分別取反賦給鎖存使能lock和計(jì)數(shù)使能端ena，這樣計(jì)數(shù)完成后就能實(shí)現(xiàn)數(shù)據(jù)的鎖存。當(dāng)計(jì)數(shù)使能和時(shí)鐘信號(hào)同時(shí)出現(xiàn)低電平的時(shí)候，計(jì)數(shù)復(fù)位信號(hào)clr有效，將計(jì)數(shù)器清零，從新開始計(jì)數(shù)。4.1.1 頻率控制模塊的程序如下：library ieee;use ieee.s

19、td_logic_1164.all;use ieee.std_logic_unsigned.all;entity ctl is-計(jì)數(shù)允許、鎖存數(shù)據(jù)和清零三個(gè)控制信號(hào) port( clk : in std_logic; ena : out std_logic; clr : out std_logic; lock : out std_logic );end ctl;architecture behav of ctl is signal div2clk : std_logic; begin process(clk) begin if clk'event and clk='1'

20、 then div2clk<=not div2clk; end if; end process; process(clk,div2clk) begin if clk='0' and div2clk='0' then clr<='1' else clr<='0' end if; end process; lock<=not div2clk; ena<=div2clk;end; 4.1.2 頻率控制模塊CNT12 頻率控制模塊如圖4.1圖4.1 十二進(jìn)制CNT124.2十進(jìn)制加法計(jì)數(shù)器CNT10的VHDL

21、語言源程序六位十進(jìn)制計(jì)數(shù)器模塊包含六個(gè)級(jí)聯(lián)十進(jìn)制計(jì)數(shù)器，用來對(duì)施加到時(shí)鐘脈沖輸入端的待測信號(hào)產(chǎn)生的脈沖進(jìn)行計(jì)數(shù)，十進(jìn)制計(jì)數(shù)器具有集束使能、清零控制和進(jìn)位擴(kuò)展輸出的功能。使能信號(hào)和清零信號(hào)由閘門控制模塊的控制信號(hào)發(fā)生器所產(chǎn)生來對(duì)六個(gè)級(jí)聯(lián)十進(jìn)制計(jì)數(shù)器周期性的計(jì)數(shù)進(jìn)行控制。4.2.1 十進(jìn)制計(jì)數(shù)器的程序如下：Library ieee;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_1164.all;Entity cnt10 isPort (clk,clr,CS: in std_logic; QQ: out std_logic_vector(3 d

22、ownto 0); cout: out std_logic);end cnt10;architecture behav of cnt10 isbegin process(clk,clr,CS) variable cqi: std_logic_vector(3 downto 0); begin if clr='1' then cqi:=(others=>'0'); elsif clk'event and clk='1' then if CS='1' then if cqi<9 then cqi:=cqi+1; e

23、lse cqi:=(others=>'0'); end if; end if;end if;if cqi=9 then cout<='1'else cout<='0'end if;QQ<=cqi;end process;end behav;在源程序中COUT是計(jì)數(shù)器進(jìn)位輸出；QQ3.0是計(jì)數(shù)器的狀態(tài)輸出；CLK是始終輸入端；CLR是復(fù)位控制輸入端，當(dāng)CLR=1時(shí)，QQ3.0=0；CS是使能控制輸入端，當(dāng)CS=1時(shí)，計(jì)數(shù)器計(jì)數(shù)，當(dāng)CS=0時(shí)，計(jì)數(shù)器保持狀態(tài)不變。十進(jìn)制模塊如圖4.2 圖4.2 十進(jìn)制模塊 4.2.2 十進(jìn)制計(jì)

24、數(shù)器的頂層設(shè)計(jì)新建一個(gè)原理圖編輯窗，從當(dāng)前的工程目錄中凋出4個(gè)十進(jìn)制計(jì)數(shù)器元件shi.sym，并按圖4.3所示的4位十進(jìn)制計(jì)數(shù)器的頂層原理圖完成電路連接。圖4.3 CNT10頂層設(shè)計(jì)圖 完成4位十進(jìn)制計(jì)數(shù)器的原理圖編輯以后，即可進(jìn)行仿真測試和波形分析，當(dāng)CLR=0、CS=1是其計(jì)數(shù)值在0到9999之間循環(huán)變化，COUT為計(jì)數(shù)進(jìn)位輸出信號(hào)，作為后面的量程自動(dòng)切換模塊的輸入脈沖。 4.3系統(tǒng)模塊的VHDL語言源程序 4.3.1系統(tǒng)模塊的設(shè)計(jì)系統(tǒng)模塊實(shí)現(xiàn)對(duì)各模塊功能的整合，實(shí)現(xiàn)整個(gè)系統(tǒng)的功能。f_in為測試信號(hào)，mclk為輸入時(shí)鐘，carry_out為溢出信號(hào)，test_clk_out為內(nèi)部分頻輸出

25、的10000HZ信號(hào)，方便自測該程序，wei為六個(gè)數(shù)碼管的位選，dula為數(shù)碼管的段選。在這個(gè)模塊的設(shè)計(jì)中，用到了以上介紹的各個(gè)模塊，它實(shí)現(xiàn)的對(duì)是整個(gè)系統(tǒng)的控制。 4.3.2 系統(tǒng)模塊的程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity plj is port( f_in,mclk : in std_logic; carry_out,test_clk_out : out std_logic; wei: out std_logic_vector(5 downto 0); dula

26、 : out std_logic_vector(7 downto 0) ); end plj;architecture behav of plj is signal dula_temp1,dula_temp2,dula_temp3,dula_temp4,dula_temp5,dula_temp6 : std_logic_vector(7 downto 0); signal led1,led2,led3,led4,led5,led6 : std_logic_vector(3 downto 0); signal clk,clk_div1 : std_logic; signal wei_temp :

27、 std_logic_vector(5 downto 0); component cnt10-例化語句 port(clk,clr,ena : in std_logic; cq : out std_logic_vector(3 downto 0); cout : out std_logic);end component;component ctl port( clk : in std_logic; ena : out std_logic; clr : out std_logic; lock : out std_logic );end component;component reg4 port(

28、clk : in std_logic; cq : in std_logic_vector(3 downto 0); led : out std_logic_vector(3 downto 0) );end component;component decodeport(qin : in std_logic_vector(3 downto 0); qout : out std_logic_vector(7 downto 0);end component; signal cout1,cout2,cout3,cout4,cout5 : std_logic; signal clr1,ena1,lock1

29、 : std_logic; signal cq1,cq2,cq3,cq4,cq5,cq6 : std_logic_vector(3 downto 0);begin u1 : cnt10 port map(clk=>f_in, clr=>clr1,ena=>ena1, cq=>cq1,cout=>cout1); u2 : cnt10 port map(clk=>cout1,clr=>clr1,ena=>ena1, cq=>cq2,cout=>cout2); u3 : cnt10 port map(clk=>cout2,clr=&g

30、t;clr1,ena=>ena1, cq=>cq3,cout=>cout3); u4 : cnt10 port map(clk=>cout3,clr=>clr1,ena=>ena1, cq=>cq4,cout=>cout4); u5 : cnt10 port map(clk=>cout4,clr=>clr1,ena=>ena1, cq=>cq5,cout=>cout5); u6 : cnt10 port map(clk=>cout5,clr=>clr1,ena=>ena1, cq=>cq6,c

31、out=>carry_out); u7 : ctl port map(clk=>clk, clr=>clr1,ena=>ena1,lock=>lock1); u8 : reg4 port map(clk=>lock1,cq=>cq1, led=>led1); u9 : reg4 port map(clk=>lock1,cq=>cq2, led=>led2); u10 : reg4 port map(clk=>lock1,cq=>cq3, led=>led3); u11 : reg4 port map(clk=&

32、gt;lock1,cq=>cq4, led=>led4); u12 : reg4 port map(clk=>lock1,cq=>cq5, led=>led5); u13 : reg4 port map(clk=>lock1,cq=>cq6, led=>led6); u19:decode port map(qin => led1,qout=>dula_temp1); u14:decode port map(qin => led2,qout=>dula_temp2); u15:decode port map(qin =>

33、; led3,qout=>dula_temp3); u16:decode port map(qin => led4,qout=>dula_temp4); u17:decode port map(qin => led5,qout=>dula_temp5); u18:decode port map(qin => led6,qout=>dula_temp6); test_clk_out<=clk_div1; wei<=wei_temp; process(mclk)-分頻：從50MHZ分出1HZ基準(zhǔn)信號(hào) 處理后可以產(chǎn)生用于測頻所需的計(jì)數(shù)允許、鎖存數(shù)

34、據(jù)和清零三個(gè)控制信號(hào)。variable cnt1 : integer range 0 to 2500;variable cnt2 : integer range 0 to 10000;beginif mclk'event and mclk='1' thenif cnt1=2500 thencnt1:=0;clk_div1 <= not clk_div1;-掃描信號(hào)if cnt2=10000 thencnt2:=0;clk <=not clk;elsecnt2:=cnt2+1;end if;elsecnt1:=cnt1+1;end if;end if;end

35、process;process(clk_div1)variable count : integer range 0 to 6;beginif clk_div1'event and clk_div1='1' then count := count + 1; if count=6 then count := 0; end if;end if;case count is when 0 => wei_temp <= "111110"dula<=dula_temp1; when 1 => wei_temp <= "111

36、101"dula<=dula_temp2; when 2 => wei_temp <= "111011"dula<=dula_temp3; when 3 => wei_temp <= "110111"dula<=dula_temp4; when 4 => wei_temp <= "101111"dula<=dula_temp5; when 5 => wei_temp <= "011111"dula<=dula_temp6; wh

37、en others =>NULL;end case;end process;end;-f_in 為測試信號(hào)，mclk為輸入時(shí)鐘，carry_out為溢出信號(hào)，test_clk_out為內(nèi)部分頻輸出的10000HZ信號(hào)，為方便自測該程序，wei為六個(gè)數(shù)碼管的位選，dula為數(shù)碼管的段選，如圖4.4圖4.4 系統(tǒng)模塊CODE4.4 鎖存器LOCK的VHDL語言源程序鎖存模塊實(shí)現(xiàn)對(duì)計(jì)數(shù)器結(jié)果的鎖存，并將其送入譯碼模塊。clk是鎖存允許信號(hào)，當(dāng)clk有效時(shí)，鎖存模塊便將輸入信號(hào)cq的值送給輸出信號(hào)led。見圖4.54.4.1 鎖存器LOCK的程序如下：library ieee;use ieee.

38、std_logic_1164.all;use ieee.std_logic_unsigned.all;entity reg4 is-鎖存器port( clk : in std_logic; cq : in std_logic_vector(3 downto 0); led : out std_logic_vector(3 downto 0) );end reg4;architecture one of reg4 isbegin process(clk,cq) begin if clk'event and clk='1' then led<=cq; end if;

39、end process;end;圖4.5 鎖存器LOCK4.4.2 鎖存器LOCK頂層設(shè)計(jì)圖圖4.6 鎖存器LOCK頂層設(shè)計(jì)圖4.5 譯碼模塊DECODER的VHDL語言源程序譯碼模塊實(shí)現(xiàn)對(duì)計(jì)數(shù)結(jié)果的譯碼，讓其直觀地顯示于數(shù)碼管上。這便是典型的8段譯碼器。qin是輸入信號(hào)，qout是輸出信號(hào)，連接于數(shù)碼管。見圖4.74.5.1 譯碼模塊DECODER的程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all; entity decode i

40、s-BCD譯碼port(qin : in std_logic_vector(3 downto 0); qout : out std_logic_vector(7 downto 0);end decode; architecture behave of decode isbegin with qin selectqout<="11000000"when "0000","11111001"when "0001","10100100"when "0010","101

41、10000"when "0011","10011001"when "0100","10010010"when "0101","10000010"when "0110","11111000"when "0111","10000000"when "1000","10010000"when "1001",NULLwhen others

42、;圖4.7 譯碼模塊DECODERend behave;4.6四選一選擇器MUX41的VHDL語言源程序當(dāng)被測頻率超出量程時(shí)，設(shè)計(jì)分頻模塊對(duì)被測頻率進(jìn)行分頻衰減，單位上升，從而擴(kuò)大測量頻率的范圍。見圖4.8 4.6.1 MUX41程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MUX41 IS PORT(A,B,C,D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); SEL:IN STD_LOGIC_VECTOR(1 DOWNTO 0); DATA:OUT

43、 STD_LOGIC_VECTOR(3 DOWNTO 0);END MUX41;ARCHITECTURE ONE OF MUX41 ISBEGINPROCESS(SEL)BEGINIF(SEL="00")THEN DATA<=A;ELSIF(SEL="01")THEN DATA<=B;ELSIF(SEL="10")THEN圖4.8 四選一選擇器MUX41 DATA<=C;ELSE DATA<=D;END IF;END PROCESS;END ONE; 4.7 四進(jìn)制計(jì)數(shù)器CNT4的VHDL語言源程序 4.7.1

44、 四進(jìn)制計(jì)數(shù)器CNT4的程序如下：Library ieee;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_1164.all;Entity cnt4 isPort (clk: in std_logic; Q: out std_logic_vector(1 downto 0);END CNT4;architecture BHV of cnt4 isSIGNAL A:std_logic_vector(1 downto 0);BEGINPROCESS(CLK)BEGINIF CLK'EVENT AND CLK='1' TH

45、ENIF A="11" THENA<="00"ELSE A<=A+1;END IF;END IF;Q<=A;END PROCESS;END BHV;4.7.2 四進(jìn)制計(jì)數(shù)器CNT4圖4.9 四進(jìn)制計(jì)數(shù)器CNT4 四進(jìn)制模塊如圖4.94.8 250分頻器的VHDL語言源程序 4.8.1 250分頻器的程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FENG250 IS PORT(CLK:IN STD_LOGIC; CL

46、K8HZ:OUT STD_LOGIC);END FENG250;ARCHITECTURE ONE OF FENG250 ISSIGNAL COUNT:INTEGER RANGE 0 TO 250;SIGNAL CLK_TEMP :STD_LOGIC;BEGINPROCESS(CLK)BEGINIF(CLK'EVENT AND CLK='1')THENIF(COUNT=124)THENCOUNT<=0;CLK_TEMP<= NOT CLK_TEMP;ELSECOUNT<=COUNT+1;END IF;END IF;END PROCESS;CLK8HZ&l

47、t;=CLK_TEMP;END ONE;4.8.2 250分頻器見圖4.10圖4.10 250分頻器您好，為你提供優(yōu)秀的畢業(yè)論文參考資料，請(qǐng)您刪除以下內(nèi)容，O(_)O謝謝！A large group of tea merchants on camels and horses from Northwest China's Shaanxi province pass through a stop on the ancient Silk Road, Gansu's Zhangye city during their journey to Kazakhstan, May 5, 2015

48、. The caravan, consisting of more than 100 camels, three horse-drawn carriages and four support vehicles, started the trip from Jingyang county in Shaanxi on Sept 19, 2014. It will pass through Gansu province and Xinjiang Uygur autonomous region, and finally arrive in Almaty, formerly known as Alma-

49、Ata, the largest city in Kazakhstan, and Dungan in Zhambyl province. The trip will cover about 15,000 kilometers and take the caravan more than one year to complete. The caravan is expected to return to Jingyang in March 2016. Then they will come back, carrying specialty products from Kazakhstan A s

50、mall art troupe founded six decades ago has grown into a household name in the Inner Mongolia autonomous region. In the 1950s, Ulan Muqir Art Troupe was created by nine young musicians, who toured remote villages on horses and performed traditional Mongolian music and dances for nomadic families. Th

51、e 54-year-old was born in Tongliao, in eastern Inner Mongolia and joined the troupe in 1975.He says there are 74 branch troupes across Inner Mongolia and actors give around 100 shows every year to local nomadic people. "I can still recall the days when I toured with the troupe in the early '

52、;80s. We sat on the back of pickup trucks for hours. The sky was blue, and we couldn't help but sing the folk songs," Nasun says. The vastness of Inner Mongolia and the lack of entertainment options for people living there, made their lives lonely. "The nomadic people were very excited

53、 about our visits," Nasun recalls. "We didn't have a formal stage. The audience just sat on the grass. Usually, the performances became a big party with local people joining in." For him, the rewarding part about touring isn't just about sharing art with nomadic families but a

54、lso about gaining inspiration for the music and dance. Ulan Muqir literally translates as "red burgeon", and today's performers of the troupe still tour the region's villages and entertain nomadic families, but their fame has spread around the world. On May 16 and 17, nearly 100 si

55、ngers and dancers from the troupe performed at Beijing's Poly Theater. Their show, titled Ulan Muqir on the Grassland, depicted the history and development of the art troupe. "Being from the region allowed me to embrace the culture of Inner Mongolia and being a member of the troupe showed me where I belonged," Nasun, the ar