tp4056最大1al鋰電池充電模塊ucc

1、UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013120V 升壓，4A 峰值電流，高頻高側(cè)和低側(cè)驅(qū)動(dòng)器樣片: UCC27210, UCC27211特性應(yīng)用范圍用輸入驅(qū)動(dòng)高側(cè)和低側(cè)配置中的兩個(gè) N 通道金電信，數(shù)據(jù)通信和的電源屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管 (MOSFET)最大引導(dǎo)電壓 120V 直流4A 吸收，4A 源輸出電流0.9 上拉和下拉電阻半橋和轉(zhuǎn)換器推挽轉(zhuǎn)換器高電壓同步降壓型轉(zhuǎn)換器兩開關(guān)正激式轉(zhuǎn)換器有源箝位正激式轉(zhuǎn)換器D 類音頻放大器輸入引腳能夠耐受 -10V 至 20V 的電壓，并且與電源電壓范圍無關(guān)晶體管-晶體管邏輯

2、電路 (TTL) 或偽 CMOS 兼容輸入版本8V 至 17V VDD 運(yùn)行范圍，（絕對(duì)最大值 20V）7.2ns 上升和 5.5ns 下降時(shí)間（采用 1000pF 負(fù)載時(shí)）說明UCC27210 和 UCC27211 驅(qū)動(dòng)器基于常見的UCC27200 和 UCC27201 MOSFET 驅(qū)動(dòng)器，但是對(duì)性能進(jìn)行了幾項(xiàng)改進(jìn)。 峰值輸出上拉和下拉電流快速延遲時(shí)間（典型值 18ns)已經(jīng)被增加至 4A 拉電流和 4A 灌電流，并且上拉和下拉電阻已經(jīng)被減少至 0.9，因此可以在 MOSFET 的效應(yīng)平臺(tái)轉(zhuǎn)換期間用盡可能小的開關(guān)損耗來驅(qū)動(dòng)大功率 MOSFET。 現(xiàn)在，輸入結(jié)構(gòu)能夠直接處理 -10 VDC，

3、這增加了穩(wěn)健耐用性，并且可實(shí)現(xiàn)與柵極驅(qū)動(dòng)變壓器的直接對(duì)接，而無需使用整流二極管。 此輸入與電源電壓無關(guān)，并且具有一個(gè) 20V 的最大額定值。2ns 延遲匹配用于高側(cè)和低側(cè)驅(qū)動(dòng)器的對(duì)稱欠壓閉鎖功能可提供全部行業(yè)標(biāo)準(zhǔn)封裝（小外形集成電路(SOIC)-8 封裝， PowerPAD SOIC-8，4mm x4mm 小外形4mm SON-10）無引線 (SON)-8 封裝和 4mm x-40 至 140 的額定溫度范圍典型應(yīng)用圖+12V+12V+100VSECONDARY SIDE CIRCUITSECONDARY SIDE CIRCUIT+100VVVDDDDHBHBDRIVE HIDRIVE HIH

4、IHIHOHOPWM CONTROLLERPWMHSCONTROLLERLILIDRIVE LOLODRIVE LOLOUCC27211UCC27210VSSVSSISOLATION AND FEEDBACK+12VVDD+100VHBDRIVE HIHIHOHSLILODRIVELOUCC27211Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconduc

5、tor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing do

6、es not necessarily include testing of all parameters.© 20112013, Texas Instruments IncorporatedEnglish Data Sheet: SLUSAT7CONTROLCONTROLCONTROLHSUCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013說明 （續(xù)）UCC27210/1 的開關(guān)節(jié)點(diǎn)（HS 引腳）能夠處理 -18V 最大電壓，這可保護(hù)高側(cè)通道不受固有負(fù)電壓所導(dǎo)致的寄生電感和離散電容的損壞。 UCC27210（偽 CMO

7、S 輸入）和 UCC27211（TTL 輸入）已經(jīng)增加了滯后，從而使得到模擬或數(shù)字脈寬調(diào)制 (PWM)低端和高端柵極驅(qū)動(dòng)器是器的接口具有增強(qiáng)的抗擾度。的，并在彼此的接通和關(guān)斷之間實(shí)現(xiàn)了至 2ns 的匹配。由于在上集成了一個(gè)額定電壓為 120V 的自舉二極管，因此無需采用外部分立式二極管。 為高端和低端驅(qū)動(dòng)器提供了欠壓閉鎖功能，如果驅(qū)動(dòng)電壓低于額定的閥值電壓，則提供對(duì)稱接通/關(guān)閉運(yùn)行方式，并且強(qiáng)制輸出為低電平。這兩款器件均采用 8 引腳 SOIC (D)，PowerPad SOIC-8 (DDA)，4mm x 4mm SON-8 (DRM) 和 SON-10 (DPR)封裝。These devi

8、ces have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATION (1)(1)These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu

9、which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.D (SOIC-8) and DDA (Power Pad SOIC-8) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27210ADR/UCC27211ADR) to o

10、rder quantities of 2,500 devices per reel.DRM (SON-8) package comes either in a small reel of 250 pieces as part number UCC27210ADRMT/UCC27211ADRMT, or larger reels of 3000 pieces as part number UCC27210ADRMR/UCC27211ADRMR.DPR (SON-10) package comes either in a small reel of 250 pieces as part numbe

11、r UCC27210ADPRT/UCC27211ADPRT, or large reels of 3000 pieces as part number UCC27210ADPRR/UCC27211ADPRR.(2)(3)(4)2Copyright © 20112013, Texas Instruments IncorporatedTEMPERATURE RANGE TA = TJINPUT COMPATIBILITYPACKAGED DEVICES(1)SOIC-8 (D) (2)PowerPAD SOIC-8 (DDA) (2)SON-8 (DRM) (3)SON-10 (DPR)

12、 (4)-40°C to 140°CPseudo CMOSUCC27210DUCC27210DDAUCC27210DRMUCC27210DPRTTLUCC27211DUCC27211DDAUCC27211DRMUCC27211DPRUCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013ABSOLUTEUM RATINGSover operating free-air temperature range (unless otherwise noted)(1) All voltages are with respe

13、ct to VSS unless otherwise noted. Currents are positive into, negative out of the specified terminal.(2) Verified at bench characterization. VDD is the value used in an application design.RECOMMENDED OPERATING CONDITIONSall voltages are with respect to VSS; currents are positive into and negative ou

14、t of the specified terminal. 40°C < TJ = TA < 140°C (unless otherwise noted)3Copyright © 20112013, Texas Instruments IncorporatedPARAMETERMINTYPMAXUNITSupply voltage range, VDD, VHB-VHS81217VVoltage on HS, VHS-1105Voltage on HS, VHS (repetitive pulse <100 ns)-(24V-VDD)110Volt

15、age on HB, VHBVHS +8,VHS +17,VDD 1115Voltage slew rate on HS50V/nsOperating junction temperature range-40140°CMINMAXUNITSupply voltage range, VDD(1), VHB - VHS-0.320VInput voltages on LI and HI, VLI, VHI-1020Output voltage on LO, VLODC-0.3VDD + 0.3Repetitive pulse <100 ns(2)-2VDD + 0.3Output

16、 voltage on HO, VHODCVHS 0.3VHB + 0.3Repetitive pulse <100 ns(2)VHS - 2VHB + 0.3Voltage on HS, VHSDC-1115Repetitive pulse <100 ns(2)-(24V-VDD)115Voltage on HB, VHB-0.3120ESDHuman Body M(HBM)2kVField Induced Charged Device M (FICDM)1Operating virtual junction temperature range, TJ-40150°CS

17、torage temperature, TSTG-65150Lead temperature (soldering, 10 sec.)300UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013THERMAL INFORMATION(1)(2)For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.The junction-to-amb

18、ient thermalunder natural convection is obtained in a simulation on a JEDEC-standard, high-K board, asspecified in JESD51-7, in an environment descr bed in JESD51-2a.(3)The junction-to-case (top) thermalis obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test e

19、xists, but a close description can be found in the ANSI SEMI standard G30-88.(4)The junction-to-board thermal temperature, as described in JESD51-8.is obtained by simulating in an environment with a ring cold plate fixture to control the PCB(5)The junction-to-top characterization parameter, JT, esti

20、mates the junction temperature of a device in a real system and is extractedfrom the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7).The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and

21、 is extracted from the simulation data for obtaining JA , using a procedure descr bed in JESD51-2a (sections 6 and 7).(6)(7)The junction-to-case (bottom) thermalis obtained by simulating a cold plate test on the exposed (power) pad. No specificJEDEC standard test exists, but a close description can

22、be found in the ANSI SEMI standard G30-88.THERMAL INFORMATION(1)(2)For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.The junction-to-ambient thermalunder natural convection is obtained in a simulation on a JEDEC-standard, h

23、igh-K board, asspecified in JESD51-7, in an environment descr bed in JESD51-2a.(3)The junction-to-case (top) thermalis obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.(4)The jun

24、ction-to-board thermal temperature, as described in JESD51-8.is obtained by simulating in an environment with a ring cold plate fixture to control the PCB(5)The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extractedfrom the si

25、mulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7).The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure descr bed i

26、n JESD51-2a (sections 6 and 7).(6)(7)The junction-to-case (bottom) thermalis obtained by simulating a cold plate test on the exposed (power) pad. No specificJEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.4Copyright © 20112013, Texas Instruments

27、 IncorporatedTHERMAL METRICUCC27210/11(1)UNITSDRMDPR8 PINS10 PINSJAJunction-to-ambient thermal(2)33.936.8°C/WJCtopJunction-to-case (top) thermal(3)33.236.0JBJunction-to-board thermal(4)11.414.0JTJunction-to-top characterization parameter(5)0.40.3JBJunction-to-board characterization parameter(6)

28、11.714.2JCbotJunction-to-case (bottom) thermal(7)2.33.4THERMAL METRICUCC27210/11(1)UNITSDDDA8 PINS8 PINSJAJunction-to-ambient thermal(2)111.837.7°C/WJCtopJunction-to-case (top) thermal(3)56.947.2JBJunction-to-board thermal(4)53.09.6JTJunction-to-top characterization parameter(5)7.82.8JBJunction

29、-to-board characterization parameter(6)52.39.4JCbotJunction-to-case (bottom) thermal(7)n/a3.6UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013ELECTRICAL CHARACTERISTICSVDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted)(1) En

30、sured by design.5Copyright © 20112013, Texas Instruments IncorporatedPARAMETERTEST CONDITIONMINTYPMAXUNITSSupply CurrentsIDDVDD quiescent currentV(LI) = V(HI) = 0 V0.050.0850.17mAIDDOVDD operating currentUCC27210f = 500 kHz, CLOAD = 02.65.2UCC272112.55.2IHBBoot voltage quiescent currentV(LI) =

31、V(HI) = 0 V0.0150.0650.1IHBOBoot voltage operating currentf = 500 kHz, CLOAD = 02.55.0IHBSHB to VSS quiescent currentV(HS) = V(HB) = 115 V0.00051.0µAIHBSOHB to VSS operating currentf = 500 kHz, CLOAD = 00.071.2mAInputVHITInput voltage thresholdUCC272104.25.05.8VUCC27210 (DDA only)4.25.05.9VLITI

32、nput voltage thresholdUCC272UCC27210 (DDA only)VIHYSInput voltage hysteresisUCC272101.8R NInput pulldown102kVHITInput voltage thresholdUCC272VUCC27211 (DDA only)VLITInput voltage thresholdUCC272UCC27211 (DDA only)VIHYSInput voltage hysteres

33、isUCC27211700mVR NInput pulldown68kUnder-Voltage Lockout (UVLO)VDDRVDD turn-on threshold6.27.07.8VDDA only5.87.08.1VDDHYSHysteresis0.5VHBRVHB turn-on thresholdDDA onlyVHBHYSHysteresis1.1Bootstrap DiodeVFLow-current forward voltageIVDD-HB = 100 µA0.650.8VVFIHigh-current forward

34、 voltageIVDD-HB = 100 mA0.850.95RDDynamic, VF/IIVDD-HB = 100 mA and 80 mA5LO Gate DriverVLOLLow-level output voltageILO = 100 mA0.050.090.19VVLOHHigh level output voltageILO = -100 mA, VLOH = VDD - VLO9Peak pull-up current (1)VLO = 0 V3.7APeak pull-down current(1)VLO = 12 V4.5HO G

35、ATE DriverVHOLLow-level output voltageIHO = 100 mA0.050.090.19VVHOHHigh-level output voltageIHO = -100 mA, VHOH = VHB - VHO9Peak pull-up current(1)VHO = 0 V3.7APeak pull-down current(1)VHO = 12 V4.5UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013ELECTRICAL CHARACTERISTICS (conti

36、nued)VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted)(2) Ensured by design.(3) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.(4) Typical values for TA = 25°C.6Copyright ©

37、20112013, Texas Instruments IncorporatedPARAMETERTEST CONDITIONMINTYPMAXUNITSSwitching Parameters: Propagation DelaysTDLFFVLI falling to VLO fallingUCC27210, CLOAD = 0152137nsTDHFFVHI falling to VHO falling152137TDLRRVLI rising to VLO rising152446TDHRRVHI rising to VHO rising152446TDLFFVLI falling t

38、o VLO fallingUCC27211, CLOAD = 0101730TDHFFVHI falling to VHO falling101730TDLRRVLI rising to VLO rising101840TDHRRVHI rising to VHO rising101840Switching Parameters: Delay MatchingTMONFrom HO OFF to LO ONUCC27210TJ = 25°C311nsTJ = 40°C to 140°C314TMOFFFrom LO OFF to HO ONTJ = 25°

39、;C311nsTJ = 40°C to 140°C314TMONFrom HO OFF to LO ONUCC27211TJ = 25°C29.5nsTJ = 40°C to 140°C214TMOFFFrom LO OFF to HO ONTJ = 25°C29.5nsTJ = 40°C to 140°C214Switching Parameters: Output Rise and Fall TimetRLO rise timeCLOAD = 1000 pF, from 10% to 90%7.2nstRHO

40、rise time7.2tFLO fall timeCLOAD = 1000 pF, from 90% to 10%5.5tFHO fall time5.5tRLO, HOCLOAD = 0.1 µF, (3 V to 9 V)0.360.6µstFLO, HOCLOAD = 0.1 µF, (9 V to 3 V)0.150.4Switching Parameters: MiscellaneousMinimum input pulse width that changes the output50nsBootstrap diode turn-off time (

41、2)(3)IF = 20 mA, IREV = 0.5 A(4)20UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013Timing DiagramsLIInput (HI, LI)HITDLRR, TDHRRLOOutput (HO, LO)TDLFF, TDHFFHOTMONTMOFF7Copyright © 20112013, Texas Instruments IncorporatedUCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013DEVIC

42、E INFORMATIONFunctional Block DiagramHB2UVLOHO3LEVEL SHIFTHS45HIVDD1UVLOLO8VSSLI67SOIC-8 (D)TOP VIEWPower PadTM SOIC-8 (DDA)TOP VIEW11LOVDDLOVDD22HBVSSHBVSS33LIHOLIHO44HIHSHIHSSON-10 (DPR) TOP VIEWSON-8 (DRM)TOP VIEW18LOVDDLOVDDExposedThermal Die Pad*HBVSS2HB7VSSHOLI36LIHOHSHI45HIHSNCNC8Copyright &#

43、169; 20112013, Texas Instruments Incorporated110234987568ExposedThermal7Die Pad658765UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013TERMINAL FUNCTIONS(1)For cold temperature applications we recommend the upper capacitance range. Attention should also be made to PCB layout - see Layout Re

44、commendations.HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 . If the source impedance is greater than 100 , add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added capacitor value depends on t

45、he noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs.The PowerPAD is not directly connected to any leads o

46、f the package. However it is electrically and thermally connected to the substrate which is the ground of the device.(2)(3)9Copyright © 20112013, Texas Instruments IncorporatedPIN NAMEPINDESCRIPTIOND/DDA/DRMDPRVDD11Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typic

47、al decoupling capacitor range is 0.22 µF to 4.7 µF (See (1).HB22High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin.Typical range of HB bypass capacitor is 0.022 µF to

48、 0.1 µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and should also be selected based on speed and ripple criteriaHO33High-side output. Connect to the gate of the high-side power MOSFET.HS44High-side source connection. Connect to source of high-side power MOSFET

49、. Connect the negative side of bootstrap capacitor to this pin.HI57High-side input.(2)LI68Low-side input.(2)VSS79Negative supply terminal for the device which is generally grounded.LO810Low-side output. Connect to the gate of the low-side power MOSFET.N/C-5/6Not Connected.PowerPAD (3)PadPadUtilized

50、on the DDA, DRM and DPR packages only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.UCC27210 UCC27211ZHCS501E NOVEMBER 2011 REVISED AUGUST 2013TYPICAL CHARACTERISTICSQUIESCENT CURRENTvs SUPPLY VOLTAGEUCC27210 IDD OPERATING CURRENTvs FREQUENCY100100UCC27210, VDD = 12V8010601CL=0pF, T=40°C CL=0pF, T=25°C CL=0pF, T=140°C CL=1000pF, T=25°C CL=1000pF, T=140°C CL=4700pF, T=140°C400.12000.0102468101