PWM模塊和時(shí)鐘系統(tǒng)模塊學(xué)習(xí)筆記

1、PWM模塊1. PWM 通道占空比寄存器 PWM Channel Duty Register PWMDTY)Mcdule 3著& + 0x001 C 二 PIDTYO. 0x001 D s WA1DTY1. 0x001E 二 PWMDTY2, OxODI - = IRWMDrfSModuie Baw + 0x0020 - PWMDTY4. 0x0021 二 PWMDTY5 0x0022 三 PWMDTY6, QMQO23 - PWMDTV7rss32iBit?65斗32”BitOReset 1111|1111Figure PWM Channel OutyiPWMDTYx)Read: A

2、nytime每個(gè)通道都有一個(gè)專用的用來(lái)設(shè)置占空比的寄存器PWMDTYx PWMDTYx和PWMPERx的值共同決定了占空比的值，就是說(shuō)當(dāng)每個(gè)通道的count的值計(jì)數(shù)到和PWMDTYx的值相等時(shí)，相應(yīng)的輸出信號(hào)就發(fā)生一次翻轉(zhuǎn)。如果你設(shè)置PWMPOL寄存器的某位 PPOLx的值為1,也就是開(kāi)始的時(shí)候輸出為高電平，然后當(dāng)計(jì)數(shù)器數(shù)到和PWMDTYx的值后就翻轉(zhuǎn)為低電平，那么 PWMDTY寄存器的值就包含了高電平的時(shí)間，再結(jié)合占空比說(shuō)明 一下吧PPOLx=1:占空比=(PWMDTYx/PWMPERX) *100%PPOLx=0:占空比=(PWMPERx-PWMDTYx /PWMPERx*100%2. P

3、WM 通道周期寄存器 PWM Channel Period Registers(PWMPERx)Module Ba% * 0x0014 - PVVMPEF?0.CxQD*5 - FVMPERI, QxS)Q1& - PWWPER2. 0x0017 - FWYPER3 kd_.le Ea» + ax00ia= PWMPER4,Oxflfl-9= PWMPER5;PWF/PER6 0«OG1 B = PAMPER?ra54121 0!Bit 7B54321ano11111111Figure 13-1S PWM Channel Period(PWMPERm)RcMl An

4、vtimer乂 nLe: AnyLnic每個(gè)通道都有一個(gè)專用的用來(lái)設(shè)置周期情況的寄存器(PWMPERx)，這個(gè)寄存器的值就決定了 PWM通道輸出信號(hào)周期的長(zhǎng)短，如果我們已經(jīng)知道的參考時(shí)鐘源的值，那么就可以計(jì)算 出PWM輸出信號(hào)的周期了，計(jì)算方法如下：PWMxPeriod=ChannelClockPeriod*PWMPEI左對(duì)齊情況下即 CAEx=0) PWMxPeriod=ChannelClockPeriod*PWMPERx居中對(duì)齊情況下即 CAEx=1)3. PWM 使能寄存器 PWM Enable Register(PWME)LIdiJuIe Gase + C)xOO DO#ES*J2QP

5、WEfF£4 PAfJE3 PVME2 PWM ElPWME7:0分別控制著對(duì)應(yīng)的8個(gè)通道的使能，例如：PWME_PWMEO=0禁止通道0的PWM輸出PWME_PWME7=1:使能通道7的PWM輸出3.PWM極性寄存器 PWM Polarity Register(PWMPOL)13.3.2 2 PWM Polarity Register (PWMPOL)1 lie stdi i:n clarity ul eacJi PWM uhdnnrt avrloim ih dtltr: iiniicd by dusuciiiLiL PPULx b:l in the PWMPOL register

6、. If the polarity hit is one, the 卩 W 陽(yáng) channel outpur is high fit the beginning of the cycle and ihen gue when lhe duly count is reached. Conversely. iTthe polarii bil ：k zero, iht uuipui low nrul ihen jroes high when ihc duty counr is reached.'屁Ul* 弓 JEG » ：XXI01T3543210RA1PPOL7PP0L6PPOL5

7、PPOLJPPOL3PPOL2PPOL1&PDLDRflseS0 0 0 0D00Figure 13-4, PWM Polarity Register (PWMPOL)Read: AtiyiimeWrite- Anylimr-PWMPOL寄存器是用來(lái)控制 PWM 一開(kāi)始輸出時(shí)的信號(hào)高低情況，假如 PPOLX設(shè)為1,則和 之相應(yīng)的PWM通道在開(kāi)始的時(shí)候輸出為高電平， 然后等到計(jì)數(shù)器的值和你設(shè)置的那個(gè) PWM 信號(hào)的值（PWMDTYX）相等的時(shí)候就輸出低電平。 PPOL的值為0的時(shí)候正好和這相反。4. PWM Clock Select Register（PW附鐘選擇寄存器）Modu

8、1; BdM + 0x00027g543210RWPCLK7PCLKL6PCLK5PCLK4PCLK3PCLK2PCLK1PCLKD30000000FigurePWM Clock Select Regisler (PWMCLK)Rtfd; .'knytimeWrite； AnytimeNOTERegister bits PCLK0 td PCLK7 can hr written anytime- If & clock select is changed uhiJle a PWM signal is being generated, a truncaicd Oi iUriclie

9、d puls亡 can occur during ihe trarsitiun.PWMCLK寄存器是用來(lái)設(shè)置每個(gè)通道的參考時(shí)鐘源的，每個(gè)通道都有2個(gè)時(shí)鐘源，具體的為CLOCK A,CLOCK SA（0,1,4,5）;CLOCK B,CLOC（S閉,6,7）,例如：PWMCLK_PCLKO=0則通道0選擇CLOCK A乍為時(shí)鐘源PWMCLK_PCLK6=側(cè)通道6選擇CLOCK SB乍為參考時(shí)鐘源5. PWM PrescaleClock Select Register（PWMPRCLK）PW預(yù)分頻時(shí)鐘選擇寄存器PCK0?PCKSiPCKBO0PCKA2PCKA1PC KAO4jReet 00Q00

10、000I = UnimpleTTienieri or Resep_(ecFbgur# 13>6一 PWM Prenl# Clock Select Register (PWMPRCLK)Read: AnytimeWriie: An> limePWMPRCLK的第3位和第7位沒(méi)有定義，低三位用來(lái)設(shè)置CLOCKA的分頻，4-6位則設(shè)置CLOCK B的分頻，以 CLOCK A 為例，具體值的計(jì)算如下表：Table 13-6. Clock A Prescaler Sel匚t官PCKA2PCKA1PC KAOValue of Clock A000Bus clock001Bus cloGk I

11、2D10Bus clock 14011Bus cloak / 8100Bus dock / 16101Bus dock J 32110Rus clock 1 64111Bus clack 11286、PWM Center Align Enable Register(PWMCAE)The PWMCAE rey:sLer .oniiiii-eighL centre bits for th? electicn ofcenier njgned uLLtputs or lei1： iligiieJ outputs for each PWM channel- If ilr < ALx bit 皿対

12、ta a nne tht cflCTtspondiug PWM output will h< center aligned. Jfthe CAEx bit is cleared* the corresponding PWM output will be Jcft aligned. See Sectirm 114.2'*1 eft .Migned Outputi11 and C'crinn 1 ?.4.2.6, "Venter AlignedOiilput<T Ff>ri mpredeihilcd description of the PWM nuip

13、ui modes.Meet.jIf* Raw + OxODIMRW7«543210CAF7CAF!JCAESCAFiCAF3CAF?CAF1CAFO-F=-000000Q0Fiura 13*7. PWM Cant«r Align Erabh Ragtitw (PWMCAE)Keud; AnytimeWrite; AnytimePWMCAE寄存器用來(lái)設(shè)置每個(gè)通道的對(duì)齊方式，CAEx為0時(shí)，設(shè)置相應(yīng)的通道為左對(duì)齊,CAEx為1時(shí)，設(shè)置相應(yīng)的通道為中心對(duì)齊7、PWM Control Register (PWMCTL)1 he PWMCTL register providesfor

14、 various control nf the PWM mod tile.M&du 0 Baes * DmOC 057643210二:CON67CON45COK23COHO'PS WAIPFRZ00w00000000=Unirnpleniisnted or lReservadFiigure 136. PWM Control Reglttsr (PWMCTL)PWMCTL寄存器可以控制相應(yīng)通道之間的兩兩級(jí)聯(lián)情況，以便將PWM 口設(shè)置成16位的輸出，這樣有利于提高精度，比如你設(shè)置PWMCTL_CON01=1那么通道0和通道1就級(jí)聯(lián)成一個(gè)16位的PWM輸出通道，這個(gè)16位的PWM通道

15、的輸出端為通道 1的輸出端口，其配置 情況也由通道1的相應(yīng)寄存器去設(shè)置。8 PWM Scale A Rerister(PWMSCLA)PWMSCLA寄存器是用來(lái)將 CLOCK A寄存器繼續(xù)壓縮分頻，以產(chǎn)生CLOCK SA具體的計(jì)算 公式如下：CLOCK SA=CLOCK/2*PWMSCLA注意：當(dāng)PWMSCLA為0的時(shí)候?qū)嶋H上是滿標(biāo)度值，也就是將COLCK A 512分頻寄存器各位如下所示Module Bam + CnOOOa7654321DRWB.I765A321BHO00000000Figure B-1L PWM Scale A Hagitter (PWMKLA)9、PWM Scale B

16、 Register(PWMSCLB)LB ix th;scale in scaling cloc 13 tci irenerifli cluck SB. Clotk SB ispcncraied by taking cldtk B. di' idnig n by ilw value m thr PWMSCLB rcpisier and dividing tlui by iwu.Clock SB-Clock B (2 * PWMSCLB)NOTEWhen PWMSCLB S00| PWMSCLB value is c<Bisiderda full scale vaJut；of 25

17、 6. Clock B is thus divided by 51XAny value xntten In ibis rsiiisttr -.villthe sca'e cojnler t(i kuid th亡 nL”imIli亡 | MSC1.BJ.tr'od已 Ba 北-.xcui-u5iJ21Brt 765431BrtOOQOOOOOCFigure 13-12. PWIV Scale B Register (PWMSCLB)該寄存器的使用情況和PWMSCLA 一樣，這里不累述，具體可參考上面一段時(shí)鐘系統(tǒng)模塊1.CLKSEL 時(shí)鐘選擇寄存器(Clock Select Reg

18、ister )Figure 8-B. S12XECRG Clock Select Register (CLKSEL)CLKSEL=0;鎖存器時(shí)鐘關(guān)PLLSEL位，選定鎖相環(huán)(PLL Select)位，置為1選定鎖相環(huán)時(shí)鐘。0:系統(tǒng)時(shí)鐘來(lái)自晶振1:系統(tǒng)時(shí)鐘來(lái)自鎖相環(huán)2.PLLCTL:鎖相環(huán)控制寄存器(CRG IPLL Control Register )7B5432 1DCMEPLLONFM1FM0FSTWKPPREPCESCME11000001Figure 8-9. S12XECRG IPLL Control Register (PLLCTL)CME位，時(shí)鐘監(jiān)控允許位(Clock Monito

19、rEnable) , CME=1時(shí)，時(shí)鐘監(jiān)控允許；CME=時(shí)禁止;PLLON位，鎖相環(huán)電路允許位，PLLON= 1時(shí)，鎖相環(huán)電路允許；=0時(shí)禁止。FM1, FM0: IPLL頻率調(diào)制使能位Table 8-7. FM Amplitude selectionFM1FMOFM Amplitude / fvco Variation00FM off01=1%10-2%t134%這兩位是用來(lái)減少噪聲用的，任何時(shí)候都可以寫(xiě)，除了PLLSEL=時(shí)SCME自時(shí)鐘模式使能位。正常模式可以寫(xiě)一次，特殊模式anytime。當(dāng)工作在自 時(shí)鐘模式(SCME=)1時(shí)，不能被清除。SCMEl時(shí)，探測(cè)到外部晶振失效時(shí)產(chǎn)生復(fù)位信號(hào)；SCME= 0時(shí)，探測(cè)到外部晶振失效時(shí)進(jìn)入自給時(shí)鐘方式。通常，單片機(jī)的片內(nèi)寄存器在 CPI復(fù)位時(shí)都是清0的。在此，注意到，這個(gè)鎖相環(huán) 控制寄存器見(jiàn)PLLCTL在復(fù)位后有2位為1，在沒(méi)有全面掌握某個(gè) CPU勺特性之前，盡可 能使用復(fù)位后的默認(rèn)參數(shù)是一條原則，這可以使系統(tǒng)初始化的處理盡量簡(jiǎn)單。使用默認(rèn)參