基于單片機(jī)的溫濕度檢測報警系統(tǒng)外文翻譯

1、-譯文：單片機(jī)溫度控制系統(tǒng)中英文翻譯資料at89s52是美國ATMEL公司生產(chǎn)的低電壓，高性能CMOS8位單片機(jī)，片含4Kbytes的快速可擦寫的只讀程序存儲器PEROM和128 bytes的隨機(jī)存取數(shù)據(jù)存儲器RAM，器件采用ATMEL公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS-51產(chǎn)品指令系統(tǒng)，片置通用8位中央處理器CPU和flish存儲單元，功能強(qiáng)大at89s52單片機(jī)可為您提供許多高性價比的應(yīng)用場合，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)：與MCS-51產(chǎn)品指令系統(tǒng)完全兼容4K字節(jié)可重復(fù)寫flash閃速存儲器1000次擦寫周期全靜態(tài)操作：0HZ24MHZ三級加密程序存儲器128*

2、8字節(jié)部RAM32個可編程I/O口2個16位定時計數(shù)器6個中斷源可編程串行UART通道低功耗空閑和掉電模式功能特性概述AT89S52提供以下標(biāo)準(zhǔn)功能：4K 字節(jié)flish閃速存儲器，128字節(jié)部RAM，32個I/O口線，兩個16位定時計數(shù)器，一個5向量兩級中斷構(gòu)造，一個全雙工串行通信口，片振蕩器及時鐘電路。同時，at89s52可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停頓CPU的工作，但允許RAM，定時計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的容，但振蕩器停頓工作并制止其它所有部件工作直到下一個硬件復(fù)位。方框圖引腳功能說明Vcc：電源電壓GND：地

3、P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)位口。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個邏輯門電路，對端口寫“1”可 作為高阻抗輸入端用。 在外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址低8位和數(shù)據(jù)總線復(fù)用，在期間激活部上拉電阻。P1口：P1是一個帶部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅(qū)動吸收或輸出電流4個TTL邏輯門電路。對端口寫“1”，通過部的上拉電阻把端口拉到高電平，此時可做熟出口。做輸出口使用時，因為部存在上拉電阻，*個引腳被外部信號拉低時會輸出一個電流Iil.Flash編程和程序校驗期間，P1承受低8位地址。P2口：P2是一個帶有部上拉

4、電阻的8位雙向I/O口，P2的輸出緩沖級可驅(qū)動吸收或輸出電流4個TTL邏輯門電路。對端口寫“1”，通過部地山拉電阻把端口拉到高電平，此時可作為輸出口，作輸出口使用時，因為部存在上拉電阻，*個引腳被外部信號拉低時會輸出一個電流Iil。在外部程序存儲器獲16位地址的外部數(shù)據(jù)存儲器例如執(zhí)行 MOV* DPTR指令時，P2口送出高8位地址數(shù)據(jù)。在8位地址的外部數(shù)據(jù)存儲器如執(zhí)行 MOV* RI指令時，P2口線上的容也即特殊功能存放器SFR區(qū)中R2存放器的容，在整個期間不改變。Flash編程或校驗時，P2亦承受高地址和其它控制信號。P3口：P3口是一組帶有部上拉電阻的8位雙向I/O口。P3口輸出緩沖級可驅(qū)

5、動吸收或輸出電流4個TTL邏輯門電路。對P3口寫入“1”時，他們被部上拉電阻拉高并可作為輸出口。做輸出端時，被外部拉低的P3口將用上拉電阻輸出電流Iil。P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能，如下表所示：端口引腳第二功能P3.0r*d (串行輸入口)P3.1t*d (串行輸出口)P3.2int0 (外中斷0)P3.3int1 (外中斷1)P3.4t0 (定時/計數(shù)器0)P3.5t1 (定時/計數(shù)器1)P3.6 WR (外部數(shù)據(jù)存儲器寫選通)P3.7RD (外部數(shù)據(jù)存儲器讀選通)P3口還接收一些用于flash閃速存儲器編程和程序校驗的控制信號。RST：復(fù)位輸入。當(dāng)振蕩器工

6、作時，RST引腳出現(xiàn)兩個機(jī)器周期以上高電平將使單片機(jī)復(fù)位。ALE/PROG：當(dāng)外部程序存儲器或數(shù)據(jù)存儲器時，ALE地址所存允許輸出脈沖用于所存地址的低8位字節(jié)。即使不外部存儲器，ALE仍以時鐘振蕩頻率的1/6輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是：每當(dāng)外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。對flash存儲器編程期間，該引腳還用于輸入編程脈沖PROG。如有不要，可通過對特殊功能存放器SFR區(qū)中的8EH單元的D0位置位，可制止ALE操作。該外置位后，只要一條MOV*和MOVC指令A(yù)LE才會被激活。此外，該引腳會被微弱拉高，單片機(jī)執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效。PSE

7、N：程序存儲允許PSEN輸出是外部程序存儲器的讀選通信號，當(dāng)at89s52由外部程序存儲器取指令或數(shù)據(jù)時，每個機(jī)器周期兩個PSEN有效，即輸出兩個脈沖。在此期間，當(dāng)外部數(shù)據(jù)存儲器，這兩次有效的PSEN信號不出現(xiàn)。EA/VPP:外部允許。欲使CPU僅外部程序存儲器地址為0000H-FFFFH，EA端必須保持低電平接地。需注意的是; 如果加密位LB1被編程，復(fù)位時部會鎖存EA端狀態(tài)。如 EA端為高電平接VCC端，CPU則執(zhí)行部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP.*TAL1: 振蕩器反相放大器的及部時鐘發(fā)生

8、器的輸出端。*TAL2: 振蕩器反相放大器的輸出端。時鐘振蕩器：at89s52中有一個用于構(gòu)成部振蕩器的高增益反相放大器，引腳*TAL1和*TAL2分別是該放大器的輸入端和輸出端。這個放大器與作為反響的片外石英晶體或瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體或瓷諧振器及電容C1、C2接在放大器的反響回路中構(gòu)成并聯(lián)振蕩電路。對外接電容C1、C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會輕微影響振蕩頻率的上下、振蕩器的穩(wěn)定性、起振的難易程度及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30PF+10PF，而如使用瓷諧振器建議選擇40PF+10PF。用戶也可以采用外部時鐘。采用外部

9、時鐘的電路如圖5右所示。這種情況下，外部時鐘脈沖接到*TAL1端，即部時鐘發(fā)生器的輸入端，*TAL2則懸空由于外部時鐘信號是通過一個2分頻觸發(fā)器后作為部時鐘信號的，所以對外部時鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時間和最大的低電平持續(xù)時間應(yīng)符合產(chǎn)品技術(shù)要求。空閑模式:在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時，片RAM和所有特殊功能存放器的容保持不變。空閑模式可由任何允許的中斷請求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，即可終止空閑工作模式。程序會首先響應(yīng)中斷，進(jìn)入中斷效勞程序，執(zhí)行完中斷效勞

10、程序并僅隨終端返回指令，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條指令。其二是通過硬件復(fù)位也可將空閑工作模式終止，需要注意的是，當(dāng)由硬件復(fù)位來終止空閑模式時，CPU通常是從激活空閑模式那條指令的下一條指令開場繼續(xù)執(zhí)行程序的，要完成部復(fù)位操作，硬件復(fù)位脈沖要保持兩個機(jī)器周期24個時鐘周期有效，在這種情況下，部制止CPU片RAM，而允許其它端口。為了防止可能對端口產(chǎn)生以外寫入，激活空閑模式的那條指令后一條指令不應(yīng)該是一條對端口或外部存儲器的寫入指令?？臻e和掉電模式外部引腳狀態(tài)模式程序存儲器ALEPSENPORT0 PORT1PORT2PORT3空閑模式部11數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)空閑模

11、式外部11浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式部00數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式外部00浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式:在掉電模式下，震蕩器停頓工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片RAM和特殊功能存放器的容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能存放器但不改變RAM中的容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。程序存儲器的加密 ：AT89S52可使用對芯片上的3個加密位進(jìn)展編程P或不編程U來得到如下表所示的功能：加密位保護(hù)功能表程序加密位保護(hù)類型LB1 LB2LB31UUU沒有程序保護(hù)功能2PUU制止從外部

12、程序存儲器中執(zhí)行MOVC指令讀取部程序存儲器的容3PPU除上表功能外，還制止程序校驗4PPP除以上功能外，同時制止外部執(zhí)行當(dāng)加密位LB1被編程時，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存起的初始值是一個隨機(jī)數(shù)，且這個隨機(jī)數(shù)會一直保持到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法去除。FLASH閃速存儲器的編程：at89s52單片機(jī)部有4K字節(jié)的FLASH PEROM,這個FLASH存儲陣列出廠時已處于擦除狀態(tài)即所有存儲單元的容均為FFH，用戶隨時可對其進(jìn)展編程。編程接口可接收高電平

13、+12V或低電平VCC的允許編程信號，低電平編程模式適合于用戶再線編程系統(tǒng)，而高電平編程模式可與通用EPROM編程器兼容。AT89S52單片機(jī)中，有些屬于低電壓編程方式，而有些則是高電平編程方式，用戶可從芯片上的型號和讀取芯片的簽名字節(jié)獲得該信息，見下表。Vpp=12vVpp=5v芯片頂面標(biāo)識at89s52*yywwat89s52*-5yyww簽名字節(jié)(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HAT89S52的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字節(jié)，要對整個芯片的PEROM程序存儲器寫入一個非空字節(jié)，

14、必須使用片擦除的方式將整個存儲器的容去除。編程方法：編程前，需按表1、圖3和圖4所示設(shè)置好地址，數(shù)據(jù)及控制信號， at89s52編程方法如下：1.在地址線上加上要編程單元的地址信號。2.在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。3.激活相應(yīng)的控制信號。4.在高電壓編程方式時，將EA/VPP端加上+12V編程電壓。5.每對FLASH存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE/PROG編程脈沖，改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)15步驟，直到全部文件編程完畢。每個字節(jié)寫入周期是自身定時地，通常約為1.5ms。數(shù)據(jù)查詢：at89s52單片機(jī)用數(shù)據(jù)查詢方式來檢測一個寫周期是否完畢，在一個寫周期

15、中，如需要讀取最后寫入的那個字節(jié)，則讀出的數(shù)據(jù)的最高位P0.7是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會出現(xiàn)在所有輸出端上，此時，可進(jìn)入下一個字節(jié)的寫周期，寫周期開場后，可在任意時刻進(jìn)展數(shù)據(jù)查詢。READY/BUSY：字節(jié)編程的進(jìn)度可通過“RDY/BSY輸出信號監(jiān)測，編程期間，ALE變?yōu)楦唠娖健癏后P3.4(RDY/BSY)端電平被拉低，表示正在編程狀態(tài)忙狀態(tài)。編程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。程序校驗：如果加密位LB1、LB2沒有進(jìn)展編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)。加密位不可能直接變化。證實加密位的完成通過觀察它們的特點和能力。芯片擦除：利用控

16、制信號的正確組合表1并保持ALE/PROG引腳10ms的低電平脈沖寬度即可將PEROM陣列4k字節(jié)整片擦除，代碼陣列在擦除操作中將任何非空單元寫入“1，這步驟需要再編程之前進(jìn)展。讀片簽名字節(jié)：at89s52單片機(jī)有3個簽名字節(jié)，地址為030H、031H和032H。用于聲明該器件的廠商、型號和編程電壓。讀簽名字節(jié)的過程和單元030H、031H和032H的正常校驗相仿，只需將P3.6和P3.7保持低電平，返回值意義如下：030H=1EH聲明產(chǎn)品由ATMEL公司制造。031H=51H聲明為at89s52單片機(jī)。032H=FFH聲明為12V編程電壓。032H=05H聲明為5V編程電壓。編程接口：采用控

17、制信號的正確組合可對FLASH閃速存儲陣列中的每一代碼字節(jié)進(jìn)展寫入和存儲器的整片擦除，寫操作周期是自身定時的，初始化后它將自動定時到操作完成。. z-AT89S52 single chip microputerThe at89s52 is a low-power, high-performance CMOS 8-bit microputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using At

18、mels high density nonvolatile memory technology and is patible with the industry standard MCS-51 instruction set and pinout. The chip bines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel at89s52 is a powerful microputer which provides a highly fle*ible and cost effective solution t

19、o many embedded control applications.Features: patible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 * 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer

20、/Counters Si* Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down ModesThe at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duple* serial port

21、, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logicfor operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to contin

22、ue functioning. The Power Down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the ne*t hardware reset.Pin Description:VCC Supply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL

23、 inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiple*ed loworder address/data bus during accesses to e*ternal program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes dur

24、ing Flash programming, and outputs the code bytes during program verification.E*ternal pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins

25、 they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are e*ternally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is a

26、n 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are e*ternally being pulled low will source current

27、(IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from e*ternal program memory and during accesses to e*ternal data memory that use 16-bit addresses (MOV* DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to e*t

28、ernal data memory that use 8-bit addresses (MOV* RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullu

29、ps. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are e*ternally being pulled low will source current (IIL) because of the pullups. Port 3 also serves t

30、he functions of various special features of the at89s52 as listed below:Port pinalternate functionsP3.0r*d (serial input port)P3.1t*d (serial output port)P3.2int0 (e*ternal interrupt0)P3.3int1 (e*ternal interrupt1)P3.4t0 (timer0 e*ternal input)P3.5t1 (timer1 e*ternal input)P3.6 WR (e*ternal data mem

31、ory write strobe)P3.7rd (e*ternal data memory read strobe)Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latchin

32、g the low byte of the address during accesses to e*ternal memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for e*ternal timing or clocking purposes. Note, however, t

33、hat one ALE pulse is skipped during each access to e*ternal Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOV* or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has n

34、o effect if the microcontroller is in e*ternal e*ecution mode.PSENProgram Store Enable is the read strobe to e*ternal program memory. When the at89s52 is e*ecuting code from e*ternal program memory, PSEN is activated twice each machinecycle, e*cept that two PSEN activations are skipped during each a

35、ccess to e*ternal data memory.EA/VPPE*ternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from e*ternal program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should

36、be strapped to VCC for internal program e*ecutions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.*TAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.*TAL2Output from the

37、inverting oscillator amplifier.Oscillator Characteristics*TAL1 and *TAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device fro

38、m an e*ternal clock source, *TAL2 should be leftunconnected while *TAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the e*ternal clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and ma*imum voltage h

39、igh and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mod

40、e can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program e*ecution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardwar

41、e inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an une*pected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to e*t

42、ernal memory.Status of E*ternal Pins During Idle and Power Down ModesmodeProgram memoryALEpsenPort0 Port1Port2Port3idleinternal11datadatadataDataIdleE*ternal11floatDatadataDataPowerdownInternal00DataDataDataDataPower downE*ternal 00floatdataDatadataPower Down ModeIn the power down mode the oscillato

43、r is stopped, and the instruction that invokes power down is the last instruction e*ecuted. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only e*it from power down is a hardware reset.Reset redefines the SFRs but does not change the o

44、n-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P)

45、to obtain the additional features listed in the table below: Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until res

46、et is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The at89s52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)

47、and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the at89s52 inside the users system, while the high-voltage programming mode is patible with

48、 conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.Vpp=12vVpp=5vTop-side markat89s52*yywwat89s52*-5yywwsignatur

49、e(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HThe at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Pr

50、ogramming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appro

51、priate data byte on the data lines.3. Activate the correct bination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last by