VHDL語(yǔ)言實(shí)例

1、.VHDL語(yǔ)言實(shí)例例1：設(shè)計(jì)一七段顯示譯碼器，用它來(lái)驅(qū)動(dòng)七段發(fā)光管LED顯示十六進(jìn)制數(shù)字0到9和字母A到F。LED顯示數(shù)碼管為共陽(yáng)極。LIBRARY ieee;                                 USE ieee.std_logic_1164.all;

2、60;   ENTITY HEX2LED IS                               PORT(              &#

3、160;                              HEX :IN std_logic_vector(3 DOWNTO 0);        LED : OUT std_logic_vector(6 TO 0)  

4、          );                                  END HEX2LED;       

5、                         圖例1 七段顯示譯碼器實(shí)體 ARCHITECTURE HEX2LED_arc OF HEX2LED IS      BEGIN           &

6、#160;                           - HEX-TO-SEVEN-SEGMENT DECODER              - SEGMENT ENCODING  

7、;                       - 0                           &

8、#160;            - -                                     

9、60; - 5 | |1                                   - - <-6             

10、              - 4 | |2                                   

11、60;- -                                  - 3                &

12、#160;                      WITH HEX SELECT   LED<= "1111001" when "0001",               

13、0;      "0100100" when "0010",                     "0110000" when "0011",          &#

14、160;           "0011001" when "0100",                     "0010010" when "0101",      

15、;               "0000010" when "0110",                     "1111000" when "0111",    

16、                 "0000000" when "1000",                      "0010000" when "100

17、1",                    "0001000" when "1010",                     "0000011&

18、quot; when "1011",                      "1000110" when "1100",                 &

19、#160; "0100001" when "1101",                     "0000110" when "1110",               

20、;     "0001110" when "1111",                     "1000000" when others;    END HEX2LED_arc;例2：設(shè)計(jì)一個(gè)八選一數(shù)據(jù)選擇器1）s是通道選擇信號(hào),   d0,d1

21、,d2,d3,d4,d5,d6,d7數(shù)據(jù)輸入    out1是數(shù)據(jù)輸出ENTITY sels IS PORT(d0,d1,d2,d3,d4,d5,d6,d7:IN BIT;          s :INTEGER RANGE 0 TO 7;          out1 :OUT BIT);END sels;圖例2（a)    八選一數(shù)據(jù)選擇器實(shí)體ARCHITECTURE sel

22、s_arc OF sels ISBEGIN       WITH s SELECT              out1 <= d0 WHEN 0,              d1 WHEN 1,      

23、0;       d2 WHEN 2,              d3 WHEN 3,        d4 WHEN 4,               d5 WHEN 5,   &

24、#160;          d6 WHEN 6,              d7 WHEN 7;END sels_arc;2)A,B,C是通道選擇信號(hào),    I0,I1,I2,I3,I4,I5,I6,I7數(shù)據(jù)輸入  Q是數(shù)據(jù)輸出LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY mux8 ISPOR

25、T(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:IN std_logic;          Q :OUT std_logic);END mux8; 圖例2（b)    八選一數(shù)據(jù)選擇器實(shí)體ARCHITECTURE mux8_arc OF mux8 IS    SIGNAL sel :INTEGER ；BEGIN    Q <= I0 AFTER 10 ns WHEN sel= 0 ELSE &

26、#160;            I1 AFTER 10 ns WHEN sel= 1 ELSE              I2 AFTER 10 ns WHEN sel= 2 ELSE              I3 AFTER

27、 10 ns WHEN sel= 3 ELSE              I4 AFTER 10 ns WHEN sel= 4 ELSE              I5 AFTER 10 ns WHEN sel= 5 ELSE         

28、60;    I6 AFTER 10 ns WHEN sel= 6 ELSE              I7 AFTER 10 ns ;   sel <= 0 WHEN A= 0 AND B= 0 AND C= 0 ELSE                

29、; 1 WHEN A= 1 AND B= 0 AND C= 0 ELSE                 2 WHEN A= 0 AND B= 1 AND C= 0 ELSE                 3 WHEN A= 1 AND B= 1 AND C= 0 ELSE&#

30、160;                4 WHEN A= 0 AND B= 0 AND C= 1 ELSE                 5 WHEN A= 1 AND B= 0 AND C= 1 ELSE      

31、0;          6 WHEN A= 0 AND B= 0 AND C= 1 ELSE                 7;END mux8_arc;例3：設(shè)計(jì)一D觸發(fā)器d是輸入端，clk是時(shí)鐘信號(hào)控制端，q是觸發(fā)器的輸出端。其程序如下：LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY reg

32、IS   PORT(d,clk:IN BIT;        q:OUT BIT);END reg;圖例3 D觸發(fā)器實(shí)體ARCHITECTURE reg_arc OF reg IS  BEGIN    PROCESS      BEGIN        WAIT UNTIL clk= 1;     

33、   q <= d;    END PROCESS;  PROCESSEND reg_arc;例4：設(shè)計(jì)一基本RS觸發(fā)器r、s為觸發(fā)器的輸入信號(hào)，q、not_q為觸發(fā)器的輸出信號(hào)。LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY RSFF IS   PORT(r,s:IN BIT;        q,not_q:OUT BIT);END RSFF;圖例4 基本RS觸發(fā)器實(shí)體ARCHITECTU

34、RE RSFF_arc OF RSFF IS  BEGIN    PROCESS(r,s)      VARIABLE last_state:BIT:= 0;      BEGIN        ASSERT NOT(r= 1 AND s= 1)        REPORT “Both r AND s equal to

35、 1”        SEVERITY error;        IF r= 0 AND s= 0 THEN           last_state:= last_state ;        ELSIF r= 1 AND s= 0 THEN   

36、0;       last_state:= 0;        ELSE - r= 0 AND s= 1           last_state:= 1;        END IF;    q <= last_state AFTER 10 ns; &

37、#160;  not_q <= NOT(last_state) AFTER 20 ns;  END PROCESS;END RSFF_arc;當(dāng)r和s同時(shí)等于1時(shí)，觸發(fā)器處于不定狀態(tài)。程序設(shè)計(jì)中設(shè)置了斷言語(yǔ)句是為了判斷r和s都等于1時(shí)，輸出終端將顯示報(bào)告“Both r AND s equal to 1”，同時(shí)終止模擬過程，并顯示錯(cuò)誤的嚴(yán)重error，以便設(shè)計(jì)者調(diào)試和修正模塊程序。從IF到END IF是條件語(yǔ)句，用到了可選項(xiàng)ELSIF和ELSE來(lái)判別RS觸發(fā)器的其它三種情況。IF語(yǔ)句后面是一賦值語(yǔ)句，將IF語(yǔ)句中賦值的中間變量lsat_state經(jīng)10 ns后送到q端。

38、圖8-12是RS觸發(fā)器的邏輯電路圖。例5：設(shè)計(jì)一個(gè)帶有異步清零、同步置數(shù)、使能控制的四位二進(jìn)制計(jì)數(shù)器LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY COUNT2 IS   PORT(A: IN INTEGER RANGE 0 TO 3;        CLK: IN STD_LOGIC;        CLR: IN STD_LOGIC;    &#

39、160;   EN: IN STD_LOGIC;        LD: IN STD_LOGIC;        Cout: OUT INTEGER RANGE 0 TO 3        );END COUNT2;圖例5   四位二進(jìn)制計(jì)數(shù)器實(shí)體ARCHITECTURE COUNT2_arc OF COUNT2 IS  SIGNAL 

40、SIG: INTEGER RANGE 0 TO 3;BEGIN  PROCESS (CLK, CLR)  BEGIN    IF CLR = '0' THEN       SIG <= 0;    ELSIF (CLK'EVENT AND CLK = '1') THEN      IF LD = '1' THEN   

41、;      SIG <= A;      ELSE        IF EN = '1' THEN           SIG <= SIG + 1;        ELSE    

42、0;      SIG <= SIG;        END IF;     END IF;   END IF;  END PROCESS;   Cout <= SIG;END COUNT2_arc例6：設(shè)計(jì)一個(gè)存儲(chǔ)容量為28×8的RAM。CS為RAM的片選信號(hào)，WR為RAM的寫信號(hào)，RD為RAM讀信號(hào)，ADR：八位地址信號(hào)，Din：八位數(shù)據(jù)輸入線，Dout為八位數(shù)

43、據(jù)輸出線。library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RAM is    port (WR: in STD_LOGIC;                 RD: in STD_LOGIC;         

44、60;      ADR: in STD_LOGIC_VECTOR (7 downto 0);                 CS: in STD_LOGIC;                 Din: in STD_LOGIC_VECTOR (7

45、 downto 0);                 Dout: out STD_LOGIC_VECTOR (7 downto 0)               );end RAM;圖例6   RAM實(shí)體architecture RAM_arch of RAM is   sub

46、type word is std_logic_vector(7 downto 0);   type memory is array (0 to 15)of word;   signal adr_in:integer range 0 to 15;   signal sram:memory;  begin       adr_in<=conv_integer(ADR);      process(wr)begin&

47、#160;        if(wr'event and wr='1')then           if(cs='1'and wr='1')then              sram(adr_in)<=din after 2 ns;&

48、#160;          end if;         end if;      end process;      process(rd,cs)begin         if(rd='0'and cs='1'

49、)then           dout<=sram(adr_in)after 3 ns;         else           dout<="ZZZZZZZZ"after 4 ns;        

50、 end if;      end process;end RAM_arch;例7：利用枚舉類型設(shè)計(jì)一個(gè)狀態(tài)機(jī)，用燈的顏色代表相應(yīng)的狀態(tài)名。library IEEE;use IEEE.std_logic_1164.all;ENTITY traffic_light IS    PORT ( sensor,clock :in std_logic;          red_light,green_light,yellow_ligh

51、t:out std_logic          );end traffic_light;architecture abc of traffic_light is     type t_state is (red,green,yellow);     signal present_state,next_state:t_state;begin  process(present_state,sensor)  b

52、egin    case present_state is    when green=>        next_state<=yellow;        red_light<='0'        green_light<='1'   &

53、#160;    yellow_light<='0'    when red=>        red_light<='1'        green_light<='0'        yellow_light<='0' &

54、#160;      if(sensor='1')then          next_state<=green;        else          next_state<=red;       

55、; end if;    when yellow=>          red_light<='0'          green_light<='0'          yellow_light<='1'