淺談多核處理器和系統(tǒng)軟件研發(fā)ppt課件

1、 淺談多核處置器與系統(tǒng)軟件研發(fā)-實例研討: 思科QuantumFlow處置器與系統(tǒng)軟件構造 陳懷臨陳懷臨tektalk系統(tǒng)軟件 工業(yè)動態(tài) 系統(tǒng)了解實例研討：思科QuantumFlow終了語提綱提綱目的：非盈利性智庫機構領域：科技跟蹤專題分析人物報道學術打假 tektalk 最近任務總結： 專題分析 tektalk 最近任務總結： 科技書籍： The Linux Kernel)下 The Linux Kernel)中The Linux Kernel)上下上 tektalk 最近任務總結： 人物評述： 上下 tektalk 操作系統(tǒng)桌面操作系統(tǒng)效力器操作系統(tǒng)嵌入式操作系統(tǒng) 編譯器與工具鏈gcc,

2、binutil, gdb)編程環(huán)境，中間件PVM，MPI，OpenMPMapreduce，HadoopCORBA，DCOM系統(tǒng)軟件系統(tǒng)軟件 嵌入式操作系統(tǒng)-傳統(tǒng)分時系統(tǒng)：Linux，F(xiàn)reeBSD-微內核： QNX/Neutrino， L4，Mach-大型通訊操作系統(tǒng)：華為/VRP思科/IOS，IOS-XR，IOS-XE系統(tǒng)軟件系統(tǒng)軟件通訊業(yè)工業(yè)研發(fā)動態(tài)通訊業(yè)工業(yè)研發(fā)動態(tài) 多核系統(tǒng)的繼續(xù)運用 多核系統(tǒng)的多樣化微觀分布式并行計算系統(tǒng)工業(yè)動態(tài)工業(yè)動態(tài) 系統(tǒng)System與操作系統(tǒng)Operating System，中心Kernel)的關系計算單元的多樣化ASIC，F(xiàn)PGA，CPU，NP互連網(wǎng)絡的多樣化

3、Bus，Switch Fabric，Interconnect數(shù)據(jù)報文Packet驅動，調度。中斷，異常處置的簡化性能的考量，犧牲層次性和透明性系統(tǒng)了解系統(tǒng)了解實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 工程啟動時間：2019年Q3或Q4【筆者注：SPP是2019年流片的。CRS-1是2019年推出的。】研發(fā)耗資：1億美金芯片主要定位：邊緣Edge路由器，企業(yè)路由器。芯片處理問題：Stateful Service與轉發(fā)Forwarding)合一。 首發(fā)系統(tǒng)：ASR1000主頻：1.2GHZ【筆者注：ESP-5G:900MHz. ESP-

4、10G:900MHz.ESP-20G:1.2GHz】晶體管數(shù)目：8億PFE內存：DDR2。 數(shù)據(jù)報文內存Packet Buffer：ESP-5G:64M.ESP-10G:128M.ESP-20G:256m*CAM:外掛TCAM 【筆者注：ESP-5G:10M. ESP-10G:10M.ESP-20G:40M】功耗：80瓦多核：40，4 Way-Thread。來自Tensica的Xtensa。片內互聯(lián)Interconnect：Crossbar Switch片外互聯(lián)：ESI 【筆者注：在未來的新QFPzhong，將是Interlaken】數(shù)據(jù)報文接口：4個10GBPS SPI4.2 。工藝：90n

5、m流片：德州儀器實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow 實例研討：思科實例研討：思科QuantumFlow SPA Slots# of ESP Slots# of RP Slots# of SIP SlotsIOS RedundancyBuilt in GigEHeightB

6、andwidthPerformanceAir FlowPower Supply (Watts) 3-slot1Integrated (RP1)Integrated (SIP10)S/W43.5 (2RU)5-10 Gbps4-8 MppsFront to Back4708-slot112S/Wn/a7 (4RU)10-40+ Gbps8-16+ MppsFront to Back76512-slot223H/Wn/a10.5 (6RU)10-40+ Gbps8-16+ MppsFront to Back1275Aggregated Services & ScaleCisco ASR 1

7、000 SeriesASR1000 ILT NamingCPP = Cisco Packet Processor now known as the QuantumFlow Processor (QFP)CC = CarrierCard now known as the SPA Interface Processor (SIP)FP = Forwarding Processor now known as the Embedded Services Processor (ESP)FRU = Field Replaceable UnitRP = Route Processor IOSd = IOS

8、daemon, IOS process running on RPChassis Options: ASR1006RP1 (in slots “r0 & “r1)ESP10SIP10SPAsRack Mounts and Cable Mgt not shownSystem Architecture - DataplaneRoute Processor (standby)RPInterconn.Embedded ServicesProcessor(active)FECPInterconn.SPI4.2CPP subsys-temCrypto assistEmbedded Services

9、Processor(standby)FECPInterconn.SPI4.2CPP subsys-temCrypto assistSPASPAIOCPSPA Agg.Interconn.SPASPAIOCPSPA Agg.Interconn.SPASPAIOCPSPA Agg.Interconn.MidplaneRoute Processor (active)RPInterconn.SPA-SPI, 11.2GbpsHypertransport, 10Gbps ESI, 11.5GbpsAll data forwarding is through FPException: Punt path

10、for Legacy protocols handled by the RPInterconnect ASIC in each of the functional elements provides the backplane connection through ESI linksESI (Enhanced Services Interface) links are used for Data forwardingSPA-SPI links connect to the backplane through the SPA-Agg ASICDDR2-500 SDRAM MiniDIMM2.5

11、Hard disk or Solid-state driveUSB InterfaceUSB 2.0 controllerStratum-3 Network clock circuitConsole and AuxDDR2-500 SDRAM MiniDIMMMgmt ENETFP1FP0GE Switch4 CCsFP0 FP1Output clocksOther RPI2C Muxbootflash :1GB(Bulk Storage, NVRAM)Temp SensorPower CtlrEEPROMRTCUSBPowerPC CPU(SC854x SOC PowerQUICC III)

12、Interconn.SIPsESPsRPSIPsESPsRPESPsMisc.CtrlSATA controllernvarm: 32MB x 2 (part of bootflash: device)BITSSIPsSIPsIn ref clocksRPRP1 Block DiagramGE, 1GbpsI2C Inter-ICSPA ControlSPA BusESI, 11.2GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps OtherESP10 Block DiagramGE, 1GbpsI2CSPA ControlSPA BusESI, 11.2

13、GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps OtherFECP(SC854x SOC PowerQUICC III)Temp SensorPower CtlrEEPROMBoot Flash (OBFL, )JTAG CtrlDDR2-500 SDRAM MiniDIMMInterconn.Interconn.Reset / Pwr CtrlPkt Buffer DRAM (128MB)Part Len/ BW SRAMResource DRAM (512MB)SPI MuxCryptoRPsRPsRPsESPSIPsTCAM4 (10Mbit)E-

14、RP*PCI*E-CSRSA table DRAMProcessor poolPPE0PPE0PPE0PPE1PPE0PPE0PPE0PPE6PPE0PPE0PPE0PPE2PPE0PPE0PPE0PPE5PPE0PPE0PPE0PPE3PPE0PPE0PPE0PPE40PPE0PPE0PPE0PPE4Buffer, queue, schedule (BQS)QFPBuffer, queue, schedule (BQS)Buffer, queue, schedule (BQS)Dispatcher/Pkt BufferASR System BWSIP10 Block DiagramIOCP(

15、SC854x SOC)Temp SensorPower CtlrEEPROMBoot Flash (OBFL, )JTAG CtrlDDR2-500 SDRAM MiniDIMMReset / Pwr CtrlRPsRPsInterconn.Ingress classifierIngress SchedulerEgress Buffer StatusGE, 1GbpsI2CSPA ControlSPA BusESI, 11.2GbpsSPA-SPI, 11.2GbpsHypertransport, 10Gbps Other4 SPAs4 SPAsIngress Buffers (per por

16、t)Egress Buffers (per port)ESPs4 SPAsC2WEV-FCEV-RPNetwork clock distributionIn ref clocksNetwork clocks4 SPAs 4 SPAsRPsRPsSPA Agg.SPA Aggregation ASIC IOS-XE IOS XE Virtual MachineIOS UpgradeASR 1002 & 1004 (No HW Redundancy)Zero Packet LossIOS UpgradeZero Packet LossIOS UpgradeISSUISSUIOS XE Vi

17、rtual MachineIOS XE Virtual MachineIOS ActiveIOS StandbyIOS ActiveIOS StandbyIOS StandbyIOS ActiveStep 1Step 2Software VirtualizationIndustry first, delivering hitless upgrades without costly hardware redundancyCapable of broad scope of services: SP and enterprise, hosted or managedDecreases OpEx, i

18、ncreases return on training investmentFeatureBenefitCombines rich edge feature set of IOSProvides IOS command line, common look and feel for transparency to operatorSoftware Architecture IOS XEEmbedded Services ProcessorRoute ProcessorSPA Interface ProcessorControl MessagingKernelKernelKernelQFPClient/Driver IOS XE = IOS + IOS XE Middleware + Platform Software Operational Consistency - same look and feel as IOS Router IOS runs as its own Linux process for control p