數(shù)字邏輯設(shè)計(jì)及應(yīng)用課程(1-6)講稿

1、第一次課：課程介紹及要求 一學(xué)時(shí)課程教學(xué)內(nèi)容安排：第一章 引論第二章 數(shù)系與代碼 第三章 數(shù)字電路第四章 組合邏輯設(shè)計(jì)原理 第五章 組合邏輯設(shè)計(jì)實(shí)踐第七章 時(shí)序邏輯設(shè)計(jì)原理 第八章 時(shí)序邏輯設(shè)計(jì)實(shí)踐 第十章 存儲(chǔ)器及其在數(shù)字邏輯系統(tǒng)實(shí)現(xiàn)中的運(yùn)用 第十一章 其他的實(shí)際問題 補(bǔ)充內(nèi)容 模數(shù)轉(zhuǎn)換器、數(shù)模轉(zhuǎn)換器(ADC/DAC)原理及應(yīng)用簡(jiǎn)介課程教學(xué)時(shí)間安排：第一章 引論 （計(jì)劃學(xué)時(shí)數(shù)：2學(xué)時(shí)）介紹數(shù)字邏輯電路的特點(diǎn)、數(shù)字邏輯電路在電子系統(tǒng)設(shè)計(jì)中的地位、數(shù)字邏輯電路與模擬電子電路之間的關(guān)系、簡(jiǎn)單介紹EDA設(shè)計(jì)工具、VHDL語言對(duì)數(shù)字邏輯設(shè)計(jì)作用和影響。 第二章 數(shù)系與代碼 （計(jì)劃學(xué)時(shí)數(shù)：6學(xué)時(shí)）十進(jìn)制

2、、二進(jìn)制、八進(jìn)制和十六進(jìn)制數(shù)的表示方法以及它們之間的相互轉(zhuǎn)換、非十進(jìn)制數(shù)的加減運(yùn)算；符號(hào)數(shù)的表達(dá)格式以及它們之間的相互轉(zhuǎn)換以及帶符號(hào)數(shù)的補(bǔ)碼的加減運(yùn)算；BCD碼、格雷碼的特點(diǎn)，它們與二進(jìn)制數(shù)之間的轉(zhuǎn)換關(guān)系；簡(jiǎn)介二進(jìn)制數(shù)的浮點(diǎn)數(shù)表達(dá)（補(bǔ)充）；第三章 數(shù)字電路 （計(jì)劃學(xué)時(shí)數(shù)：4學(xué)時(shí)）作為電子開關(guān)運(yùn)用的二極管、雙極型晶體管、MOS場(chǎng)效應(yīng)管的工作方式；以CMOS倒相器電路的構(gòu)成及工作狀態(tài)分析；邏輯電路的靜態(tài)、動(dòng)態(tài)特性分析，等價(jià)的輸入、輸出模型；特殊的輸入輸出電路結(jié)構(gòu)：CMOS傳輸門、施密特觸發(fā)器輸入結(jié)構(gòu)、三態(tài)輸出結(jié)構(gòu)、漏極開路輸出結(jié)構(gòu)；學(xué)習(xí)了解其他類型的邏輯電路： TTL,ECL等；不同類型、不同工作

3、電壓的邏輯電路的輸入輸出邏輯電平規(guī)范值以及它們之間的連接配合的問題。第四章 組合邏輯設(shè)計(jì)（計(jì)劃學(xué)時(shí)數(shù)：10學(xué)時(shí)）邏輯代數(shù)的公理、定理，對(duì)偶關(guān)系，以及在邏輯代數(shù)化簡(jiǎn)時(shí)的作用；邏輯函數(shù)的表達(dá)形式：積之和與和之積標(biāo)準(zhǔn)型、真值表；組合電路的分析：邏輯函數(shù)表達(dá)式的產(chǎn)生過程及邏輯函數(shù)表達(dá)式的基本化簡(jiǎn)方法；組合電路的綜合過程：將功能敘述表達(dá)為組合邏輯函數(shù)的表達(dá)形式、邏輯函數(shù)表達(dá)式的化簡(jiǎn)函數(shù)化簡(jiǎn)方法卡諾圖化簡(jiǎn)方法、使用與非門、或非門表達(dá)的邏輯函數(shù)表達(dá)式、邏輯函數(shù)的最簡(jiǎn)表達(dá)形式及綜合設(shè)計(jì)的其他問題：無關(guān)項(xiàng)的處理、冒險(xiǎn)問題和多輸出邏輯化簡(jiǎn)的方法。 第五章 組合邏輯設(shè)計(jì)實(shí)踐（計(jì)劃學(xué)時(shí)數(shù)：10學(xué)時(shí)）利用基本的邏輯門完

4、成規(guī)定的組合邏輯功能（如譯碼器、編碼器、多路選擇器、多路分配器、異或門、比較器、全加器等）的電路設(shè)計(jì)任務(wù)；利用基本的邏輯門和已有的邏輯功能電路作為設(shè)計(jì)的基本元素完成更為復(fù)雜的組合邏輯電路設(shè)計(jì)的方法。第七章 時(shí)序邏輯設(shè)計(jì)原理 （計(jì)劃學(xué)時(shí)數(shù)：10學(xué)時(shí)）基本時(shí)序元件R-S型,D型,J-K型,T型鎖存器、觸發(fā)器的電路結(jié)構(gòu)，工作原理，時(shí)序特性等；掃描觸發(fā)器(Scan Flip-Flop)特性及基本應(yīng)用；鐘控同步狀態(tài)機(jī)的模型圖，狀態(tài)機(jī)類型及基本分析方法和步驟，使用狀態(tài)圖表示狀態(tài)機(jī)狀態(tài)轉(zhuǎn)換關(guān)系；時(shí)序狀態(tài)機(jī)的設(shè)計(jì)：狀態(tài)轉(zhuǎn)換過程的建立，狀態(tài)的化簡(jiǎn)與編碼賦值、未用狀態(tài)的處理-最小風(fēng)險(xiǎn)方案和最小代價(jià)方案、使用狀態(tài)轉(zhuǎn)

5、換表的設(shè)計(jì)方法、使用狀態(tài)圖的設(shè)計(jì)方法。第八章 時(shí)序邏輯設(shè)計(jì)實(shí)踐 （計(jì)劃學(xué)時(shí)數(shù)：10學(xué)時(shí)）利用基本的邏輯門、時(shí)序元件作為設(shè)計(jì)的基本元素完成規(guī)定的鐘控同步狀態(tài)機(jī)電路的設(shè)計(jì)任務(wù)：計(jì)數(shù)器、位移寄存器、序列檢測(cè)電路和序列發(fā)生器的設(shè)計(jì)；利用基本的邏輯門和已有的中規(guī)模集成電路（MSI）時(shí)序功能器件作為設(shè)計(jì)的基本元素完成更為復(fù)雜的時(shí)序邏輯電路設(shè)計(jì)的方法。時(shí)序電路設(shè)計(jì)中的其他問題：組合電路與時(shí)序電路的比較，大型時(shí)序電路的結(jié)構(gòu)劃分，時(shí)鐘歪斜，異步輸入處理等。第十章 存儲(chǔ)器及其在數(shù)字邏輯系統(tǒng)實(shí)現(xiàn)中的運(yùn)用 （計(jì)劃學(xué)時(shí)數(shù)：4學(xué)時(shí)）學(xué)習(xí)了解：存儲(chǔ)器（ROM,SRAM）的基本工作原理和結(jié)構(gòu)；學(xué)習(xí)掌握：存儲(chǔ)器在數(shù)字邏輯系統(tǒng)設(shè)

6、計(jì)的硬件實(shí)現(xiàn)中的運(yùn)用。 第十一章 其他的實(shí)際問題（計(jì)劃學(xué)時(shí)數(shù)：2學(xué)時(shí)）數(shù)字邏輯電路(組合電路和時(shí)序邏輯電路)設(shè)計(jì)的描述說明方法；數(shù)字邏輯系統(tǒng)設(shè)計(jì)的其他問題：數(shù)字邏輯設(shè)計(jì)中設(shè)計(jì)工具的作用、設(shè)計(jì)的可測(cè)試性問題、數(shù)字邏輯系統(tǒng)可靠性的問題、高速數(shù)字邏輯系統(tǒng)中信號(hào)傳輸?shù)南嚓P(guān)問題。 補(bǔ)充內(nèi)容：模數(shù)轉(zhuǎn)換器、數(shù)模轉(zhuǎn)換器(ADC/DAC)原理及應(yīng)用簡(jiǎn)介（計(jì)劃學(xué)時(shí)數(shù)：4學(xué)時(shí)）數(shù)字-模擬轉(zhuǎn)換器(Digit to Analog Converter,DAC)的基本電路結(jié)構(gòu)（R-2R結(jié)構(gòu)的DAC），工作原理；模擬-數(shù)字轉(zhuǎn)換器(Analog to Digit Converter,ADC) 的基本電路結(jié)構(gòu)（逐次逼近式的ADC

7、），工作原理；模擬-數(shù)字轉(zhuǎn)換器、數(shù)字-模擬轉(zhuǎn)換器(ADC/DAC)在電子系統(tǒng)中的作用和應(yīng)用，特別是在波形發(fā)生方面的運(yùn)用。 課程教學(xué)實(shí)驗(yàn)內(nèi)容安排：課外上機(jī)實(shí)驗(yàn)教學(xué)（計(jì)劃學(xué)時(shí)數(shù)：16學(xué)時(shí)） 實(shí)驗(yàn)?zāi)康模和ㄟ^使用CAD設(shè)計(jì)工具 對(duì)教材中相關(guān)例題的分析，加深對(duì)教材內(nèi)容的理解，更好地掌握相關(guān)知識(shí)。1、學(xué)習(xí)使用PSPICE電路分析工具仿真分析CMOS基本邏輯門的靜態(tài)特性和動(dòng)態(tài)特性、了解電路結(jié)構(gòu)和負(fù)載特性對(duì)邏輯門靜態(tài)特性和動(dòng)態(tài)特性的影響。2、學(xué)習(xí)數(shù)字邏輯電路仿真工具M(jìn)AX+plusII的基本使用方法；進(jìn)行基本組合電路基本功能單元，時(shí)序電路的基本功能單元進(jìn)行仿真，加深對(duì)基本功能單元功能作用的理解；對(duì)教材中大型例

8、題進(jìn)行仿真分析，加強(qiáng)對(duì)大型綜合性設(shè)計(jì)的分析理解能力。課程考核課程考核的內(nèi)容有：平時(shí)課外作業(yè)練習(xí)；課程隨堂練習(xí)與測(cè)驗(yàn)；期中考試和期末考試。最終成績(jī)組成：平時(shí)成績(jī)占40%，期末考試成績(jī)占60%。期中考試成績(jī)、平時(shí)課外作業(yè)練習(xí)成績(jī)和隨堂練習(xí)與測(cè)驗(yàn)成績(jī)?cè)谄綍r(shí)成績(jī)中分占50%，25%，25%。數(shù)字邏輯電路課程結(jié)構(gòu)數(shù)字邏輯電路與其他課程的相關(guān)關(guān)系CHAPTER 1 INTRODUCTIONANALOG VERSUS DIGITALAnalog signals are the time-varying signals that can take on any value across a continuou

9、s range of voltage or current.For example: the signal sin(t )Analog circuits and systems process analog signal.A digital signal is modeled as taking on, at any time, only one of two discrete values(0 or 1, low or high, false or true)Digital circuits and systems process digital signal.Digital circuit

10、s and systems have many uses in our life : Still pictures. Video and audio recordingsAutomobile carburetorsThe telephone systemsMovie effects 。Why has there now been a digital revolution?Reproducibility of results（結(jié)果的可重現(xiàn)性）Easy of design （設(shè)計(jì)的方便性）Flexibility and functionalityProgrammabilitySpeedEconom

11、ySteadily advancing technologyDigital devicesThe gates: AND gates OR gates NOT gates (inverter)The combinational logic gates: NOT-AND (NAND) gates, NOT-OR (NOR) gates,.The flip-flop devices（觸發(fā)器）Electronic Aspects of digital design See the figure 1-2Integrated circuitsICWAFERDIESSI: SMALL-SCALE INTEG

12、RATIONMSI: MEDIUM -SCALE INTEGRATIONLSI: LARGE -SCALE INTEGRATIONPACKAGECHAPTER 2 Number Systems and Codes2.1 Positional Number SystemsIn this system, a number is represented by a string of digits, where each digit position has an associated weight, and the value of a number is a weighted sum of the

13、 digits.For example A decimal number 1734 can be written as : 1734=1*1000 + 7*100 + 3*10 + 4 =1*103+7*102+3*101+4*100where, 10 is called the base or radix of the number system, and 103 is the weight of the position 3.In general, a number N of the form np-1np-2n2n1n0 . n-1n-2n-k ,the radix is r (r2),

14、has the value N= np-1rp-1np-2rp-2n2r2n1r1n0r0n-1r-1n-2r-2n-kr-k ni=(0,1r-1)If r=2, then ni=(0,1), the number system is BINARY number system.A binary number B of the form 10101110, the value is B=1*27+0*26+1*25+0*24+1*23+1*22+1*21+0*20 =1*128+0*64+1*32+0*16+1*8+1*4+1*2+0*1 =174We write a binary numbe

15、r as bp-1bp-2b2b1b0 . b-1b-2b-k, the leftmost bit is called the most significant bit(MSB), and the rightmost bit is the least significant bit(LSB).If r=8, then ni=(0,17), the number system is OCTAL number system.If r=16, then ni=(0,19,A,B,C,D,E,F), the number system is HEXADECIMAL number system.When

16、 dealing with binary and other nondecimal numbers, we use a subscript to indicate the radix of each number. For examples, 100112 means a binary number 1001110 for a decimal number17868 for an octal number178616 for a hexadecimal number. 2.3 General Positional-Number-System ConversionsSigned Number B

17、inary Codes Signed binary numbers provide the means by which both positive and negative numbers may be represented. Binary signed magnitude convention uses the most significant bit position to indicate sign (sign bit) and the remaining lesser significant bits to represent magnitude.The sign bit is 0

18、 for positive number, 1 for negative one. Three main signed number binary codes are used: signed-magnitude code, 2s complement, and 1s complement.Signed-Magnitude Codes The most significant bit(MSB) position is 0 for all positive values and 1 for negative value. There are two possible representation

19、 of zero, “+0” and “-0”, but both have same value. An n-bit signed-magnitude integer lies within the range : -(2n-1-1) through +(2n-1-1) .Some 8-bit signed-magnitude integers+ 8510 =0 10101012 - 8510=1 10101012+12710 =0 11111112 -12710=1 11111112 + 010 =0 00000002 - 010=1 000000022s Complement Numbe

20、rNumber A is a n-bit signed binary codeWay 1: the complement of A is equivalent to 2n +A|mod(2n).Way 2: If A 0 , If A n, we must append m-n copies of Xs sign bit to the left of X.If mn,we discard Xs n-m leftmost bits, the result is valid only if all of the discarded bits are the same as the sign bit

21、 of the result.Get -A 2s complement from A 2s complementWe have an n-bit complement number A 2s complement ,to obtain the -A 2s complement -A 2s complement = 2n - A 2s complement EX: A2s complement =01010101B -A2s complement=10101011B 1s complement numberNumber A is a n-bit signed binary codeIf A 0

22、,the complement of A is equivalent to A.If A 0 , the complement of A is equivalent to 2n -1+AZero is a positive numberSome examples for 1s complement number010101011s complement=01010101B110101011s complement=10101010B 000000001s complement=00000000 BGet 1s complement from signed magnitude numberWe

23、have an n-bit signed-magnitude number A , to obtain the A 1s complement .we must to:If A 0, A 1s complement =AIf A0, save the sign bit of A and complement the remaining lesser significant bits (that is,change 0s to 1s and 1s to 0s)EX: A signed-magnitude =11010101B A 1s complement =10101010BGet 2s co

24、mplement from 1s complement numberWe have A 1s complement, By following way ,we can get A 2s complementA 2s complement = A 1s complement, +1Ex: A 1s complement =10101010B + 1 A 2s complement =10101011B2s COMPLEMENT ADDITION AND SUBTRACTIONADDITION RULES2s-complement number can be added by ordinary b

25、inary addition, ignoring any carries beyond the MSB.The result will always be the correct sum as long as the range of the number system is not exceeded.A+B 2s complement = A 2s complement +B 2s complement EX: +3 0011 -2 1110 + +4 +0100 + -5 + 1011 +7 0111 -7 11001 +6 0110 +4 0100 +-3 +1101 + -7 + 10

26、01 +3 10011 -3 1101OVERFLOWIf an addition operation produces a result that exceeds the range of the number system,overflow is said to occur.There is a simple rule for detecting overflow in addition: An addition overflows if the carry bits cin into and cout out of the sign position bit are different.

27、Using double sign bit to detect overflow +3 00 011 -2 11 110 +4 +00 100 + -5 +11 011 +7 00 111 -7 11 001 -3 11 101 +5 00 101 +-6 +11 010 +6 + 00 110 -9 10 111 +11 01 011If the sign bits have same sign, the sum is valid; If the sign bits are different , the addition overflowsSUBTRACTION RULEA-B 2s co

28、mplement =A 2s complement +-B 2s complement AND -A 2s complement = 2n - A 2s complementEX: A2s complement =01010101B -A2s complement=10101011B Overflow in subtraction can be detected by examining the sign of the minuend and the complemented subtrahend, using the same rule as in addition.Combinationa

29、l Logic Design Practices5.1Documentation Standard（文檔要求）Circuit Specification（說明書）Block Diagram（方框圖）Schematic Diagram(原理圖)Timing Diagram（定時(shí)圖）Structured logic device descriptionCircuit description5.1.1 BLOCK DIAGRAMA block diagram shows the inputs, outputs, function modules, internal data paths,and im

30、portant control signal of a system.A good block diagram shows in fig 5-1Fig 5-2(c) is too much detailBUS（總線）: A bus is a collection of two or more related signal lines. A slash and a number may indicate how many individual signal lines are contained in a bus( the width of a bus). Sometime size may b

31、e denoted in the bus name (e.g., INBUS31.0).page 3155.1.2 GATE SYMBOLS5.1.3 Signal names and Active level5.1.4 Active level for pins5.1.5 Bubble-to-bubble logic design5.1.6 Drawing layoutline crossings and connectionsa single page schematic diagramflat schematic structure (fig 5-14)hierarchical sche

32、matic structure (fig 5-15)5.1.7 Buses in schematic diagramsfig 5-165.1.8 Additional schematic information FIG 5-185.2 TIMING DIAGRAM 5.2.1 Timing diagrams 5.2.2 Propagation Delay We defined the propagation delay of a signal path as the time that it takes for a change at the input of the path to prod

33、uce a change at the output of the path. 5.2.3 Timing Specificationstphl and tplhMaximum delayTypical delayMinimum delay 5.2.4 Timing AnalysisTo accurately analyze the timing of a complex circuit is very difficulty.A signal worst-case delay specification that is the maximum of tphl and tplh specifica

34、tion. By it, the design time can be saved.5.4 DECODERS（譯碼器） A decoder is a multiple_input, multiple_output logic circuit. The number of circuit input is n_bit and the number of circuit output is 2n.The most commonly used output code is one-out-of-m code, which contains m bits, where one bit is asser

35、ted at any time.INPUTSOUTPUTSENI1I0Y3Y2Y1Y0000000010000011010010110010011110002-to-4 binary decoder with an enable controlThe output functions:Y0=ENI1 I0 Y1=ENI1 I0 Y2=ENI1I0 Y3=ENI1 I02-to-4 binary decoder circuit with an enable control3-bit Gray-code output of a mechanical encoding diskDisk positi

36、onI2I1I0Binary decoder output0000Y0=145001Y1=190011Y2=1135010Y3=1180110Y4=1225111Y5=1270101Y6=1315100Y7=174X139 Dual 2-to-4 Decoderthe truth tableINPUTSOUTPUTSG_LBAY3_LY2_LY1_LY0_L1XX11110001110001110101010110110111The output functions:Y0_L=G_L+B+A=G_LBAY1_L=G_L+B+A=G_LBAY2_L=G_L+B+A=G_LBAY3_L=G_L+B

37、+A=G_LBA1/2-74X139 74X13974X138 3-to-8 Decoder The truth tableINPUTSOUTPUTSG1G2A_LG2B_LCBAY7_LY6_LY5_LY4_LY3_LY2_LY1_LY0_L0XXXXX11111111X1XXXX11111111XX1XXX111111111000001111111010000111111101100010111110111000111111011110010011101111100101110111111001101011111110011101111111Y0_L=EN_L+C+B+A =ENCBAY1

38、_L=EN_L+C+B+A =ENCBAY2_L=EN_L+C+B+A =ENCBAY3_L=EN_L+C+B+A =ENCBAY4_L=EN_L+C+B+A =ENCBAY5_L=EN_L+C+B+A =ENCBAY6_L=EN_L+C+B+A =ENCBAY7_L=EN_L+C+B+A =ENCBAEN_L= G1+G2A_L+G2B_L ; EN= G1G2A_LG2B_LONE FACT:Y0=EN(I1 I0) Y1=EN(I1 I0) Y2=EN(I1I0) Y3=EN(I1 I0)Y0_L=G_L+B+A=G_LBA=G_L+(BA)Y1_L=G_L+B+A=G_LBA =G_L

39、+(BA)Y2_L=G_L+B+A=G_LBA =G_L+(BA)Y3_L=G_L+B+A=G_LBA =G_L+(BA)Y0_L = G1G2A_LG2B_LCBA=(EN_L) +(CBA)Y1_L= (EN_L)+(CBA)Y2_L= (EN_L)+(CBA)Y3_L= (EN_L)+(CBA)Y4_L=(EN_L)+(CBA)Y5_L= (EN_L)+(CBA)Y6_L= (EN_L)+(CBA)Y7_L= (EN_L)+(CBA)ONE OUTPUT OF DECODER MAP TO ONE MINTERM (OR THE NOT, IF THE OUTPUT IS LOW ACT

40、IVE).A 4-to-16 decoder using two 74x138A 5-to-32 decorder with 4 74x138 and 1/2 74x139EX1: The truth table shows in table 5-11. design the logic circuit with 74x138. INPUTSOUTPUTSCS_LRD_LA2A1A0BILL_LMARY_LKATE_LJOAN_LPAUL_LANNA_LFRED_LDAVE_L1XXXX11111111X1XXX11111111000000011111100001100111110001011

41、10111100011111101110010011111011001011111110100110111111100011111011111BILL_L=CS_LRD_LA2A1A0 =( CS_L+RD_L)( A2A1A0)MARY_L=CS_LRD_LA2A1A0+CS_LRD_LA2A1A0 =(CS-L+RD_L)(A2A1A0+A2A1A0)KATE_L=(CS-L+RD_L)(A2A1A0+A2A1A0)JOAN_L=( CS_L+RD_L)( A2A1A0)PAUL_L=( CS_L+RD_L)( A2A1A0)ANNA_L=( CS_L+RD_L)( A2A1A0)FRED

42、_L=( CS_L+RD_L)( A2A1A0)DAVE_L=( CS_L+RD_L)( A2A1A0)EX2: To bluid the logic function by 74x138 F=WXYZ(3,6,9,11,13,15)Let mi for the minterm i F=WXYZ(3,6,9,11,13,15)=m3+m6+m9+m11+m13+m15 = m3m6m9m11m13m15SEVEN-SEGMENT DECODERSINPUT: 8421 BCD CODE, BI_L(BLANKING INPUT)OUTPUT: SEVEN-SEGMENT CODEINPUTSO

43、UTPUTSBI_LDCBAabcdefg0XXXX0000000100001111110100010110000100101101101100111111001101000110011101011011011101100011111101111110000110001111111110011110011110100001101110110011001111000100011111011001011111100001111111110000000THE CIRCUIT SHOWN IN FIGTURE 5-45 PAGE 3735.5 ENCODERSTHE OUTPUT CODE HAS FEWER BITS THAN THE INPUT CODE.BINARY ENCODERSINPUTS: 1- OUT- OF-M CODEOUTPUT: BINARY CODEY0=I7+I5+I3+I1Y1=I7+I6+I3+I2Y2=I7+I6+I5+I4THE TRUTH TABLE:INPUTSOUTPUTSI7I6I5I4I3I2I1I0Y2Y1Y0100000001110100000011000100000101000