Allegro高速PCB設(shè)計(jì)布線工具演示教學(xué)

1、Good is good, but better carries it.精益求精，善益求善。Allegro高速PCB設(shè)計(jì)布線工具Allegro高速PCB布線工具AllegroPCB設(shè)計(jì)布線工具專用應(yīng)用領(lǐng)域特點(diǎn)介紹中文翻譯AllegroPCB設(shè)計(jì)布線工具專用應(yīng)用領(lǐng)域特點(diǎn)介紹（英文版）AllegroPCB設(shè)計(jì)教程精要附：AllegroPCBDesignv16.2)軟件下載地址：AllegroPCB設(shè)計(jì)布線工具專用應(yīng)用領(lǐng)域特點(diǎn)介紹中文翻譯語言：英語網(wǎng)址：/products/pcb/pcb_design/pages/default.aspx類別：PCB設(shè)計(jì)Cadence是世界上最大的電子設(shè)計(jì)技術(shù)和配套

2、服務(wù)的EDA供貨商之一。CadenceAllegro則是Cadence推出的先進(jìn)PCB設(shè)計(jì)布線工具。Allegro提供了良好且交互的工作接口和強(qiáng)大完善的功能，和它前端產(chǎn)品Capture的結(jié)合，為當(dāng)前高速、高密度、多層的復(fù)雜PCB設(shè)計(jì)布線提供了最完美解決方案。Allegro擁有完善的Constraint設(shè)定，用戶只須按要求設(shè)定好布線規(guī)則，在布線時(shí)不違反DRC就可以達(dá)到布線的設(shè)計(jì)要求，從而節(jié)約了煩瑣的人工檢查時(shí)間，提高了工作效率！更能夠定義最小線寬或線長等參數(shù)以符合當(dāng)今高速電路板布線的種種需求。軟件中的ConstraintManger提供了簡潔明了的接口方便使用者設(shè)定和查看Constraint宣告

3、。它與CadenceOrCADCapture的結(jié)合讓E.E.電子工程師在繪制線路圖時(shí)就能設(shè)定好規(guī)則數(shù)據(jù)，并能一起帶到Allegro工作環(huán)境中，自動(dòng)在擺零件及布線時(shí)依照規(guī)則處理及檢查，而這些規(guī)則數(shù)據(jù)的經(jīng)驗(yàn)值均可重復(fù)使用在相同性質(zhì)的電路板設(shè)計(jì)上。Allegro除了上述的功能外，其強(qiáng)大的自動(dòng)推擠push和貼線hug走線以及完善的自動(dòng)修線功能更是給用戶提供極大的方便；強(qiáng)大的貼圖功能，可以提供多用戶同時(shí)處理一塊復(fù)雜板子，從而大大地提高了工作效率?；蚴抢眠x購的切圖功能將電路版切分成各個(gè)區(qū)塊，讓每個(gè)區(qū)塊各有專職的人同時(shí)進(jìn)行設(shè)計(jì)，達(dá)到同份圖多人同時(shí)設(shè)計(jì)并能縮短時(shí)程的目的。用戶在布線時(shí)做過更名、聯(lián)機(jī)互換以及修

4、改邏輯后，可以非常方便地回編到Capture線路圖中，線路圖修改后也可以非常方便地更新到Allegro中；用戶還可以在Capture與Allegro之間對(duì)對(duì)象的互相點(diǎn)選及修改。對(duì)于業(yè)界所重視的銅箔的繪制和修改功能，Allegro提供了簡單方便的內(nèi)層分割功能，以及能夠?qū)φ?fù)片內(nèi)層的檢閱。對(duì)于鋪銅也可分動(dòng)態(tài)銅或是靜態(tài)銅，以作為鋪大地或是走大電流之不同應(yīng)用。動(dòng)態(tài)銅的參數(shù)可以分成對(duì)所有銅、單一銅或單一對(duì)象的不同程度設(shè)定，以達(dá)到銅箔對(duì)各接點(diǎn)可設(shè)不同接續(xù)效果或間距值等要求，來配合因設(shè)計(jì)特性而有的特殊設(shè)定。在輸出的部分，底片輸出功能包含274D、274X、BarcoDPF、MDA以及直接輸出ODB+等多樣化

5、格式數(shù)據(jù)當(dāng)然還支持生產(chǎn)所需的Pick&Place、NCDrill和Bare-BoardTest等等原始數(shù)據(jù)輸出。Allegro所提供的強(qiáng)大輸入輸出功能更是方便與其它相關(guān)軟件的溝通，例如ADIVA、UGS(Fabmaster)、VALOR、AgilentADS或是機(jī)構(gòu)的DXF、IDF。為了推廣整個(gè)先進(jìn)EDA市場(chǎng),Allegro提供了OrCADLayout、PADS、P-CAD等接口，讓想轉(zhuǎn)換PCBLayout軟件的使用者，對(duì)于舊有的圖檔能順利轉(zhuǎn)換至Allegro中。Allegro有著操作方便，接口友好，功能強(qiáng)大，整合性好等諸多優(yōu)點(diǎn)，是一家公司投資EDA軟件的理想選擇！二、AllegroPCB設(shè)計(jì)

6、布線工具專用應(yīng)用領(lǐng)域特點(diǎn)介紹（英文版）Withitscomprehensivefeatureset,CadenceAllegroPCBDesignofferstheleadingphysicalandelectricalconstraint-drivenPCBlayoutandinterconnectroutingsystem.Thefullyintegrateddesignflowincludesdesigncreation,librarycreation,placement,interactiveroutingandediting,automaticrouting,andinterface

7、sformanufacturingandmechanicalCAD.Theuserinterfaceisintuitive,easy-to-use,andconsistentthroughoutthedesignflow.Large,densePCBdesignswithhigh-speedinterfacescanutilizeGlobalRoutingEnvironmenttechnologyforintelligentinterconnectplanningandroutingautomation.Features/BenefitsProvidesascalable,full-featu

8、redPCBdesignsolutionEnablesaconstraint-drivendesignflowtoreducedesigniterationsProvidesasingle,consistent,front-to-backconstraintmanagementenvironmentDeliversanintegratedRF/analogdesignandmixed-signaldesignenvironmentProvidesinteractivefloorplanningandcomponentplacementProvidesdesignpartitioningforl

9、arge,disperseddevelopmentteamsEnablesreal-time,interactivepush/shoveetcheditingAllowsreal-timeplowing/healingwithdynamicshapetechnologyManagesnetscheduling,timing,crosstalk,layersetrouting,andgeometricconstraintsProvidesprovenPCBRoutertechnologyforauto-routingofrandomsignalsCapturesdesignintentforin

10、terconnectsthroughhierarchicalflowplanningShortensinterconnectplanningandroutingtimefordensedesignswithhigh-speedinterfacesOutputsdesigndatainavarietyofmanufacturingformatsNFO:代碼Cadence.Allegro.PCB.Design.v16.2100101001010001001001010100100010010010011010101000101010010001010100111010010100110101011

11、001110101010100010001010101010100010001110101011AllegroPCBDesignquicklytakessimpleorcomplexdesignsfromconcepttoproductioninaconstraint-drivendesignsystem.Itsscalableplatformallowsdesignerstocost-effectivelymatchtheneedsofsmalltolargeprojects.Withitscomprehensivefeatureset,CadenceAllegroPCBDesignoffe

12、rstheleadingphysicalandelectricalconstraint-drivenPCBlayoutandinterconnectroutingsystem.Thefullyintegrateddesignflowincludesdesigncreation,librarycreation,placement,interactiveroutingandediting,automaticrouting,andinterfacesformanufacturingandmechanicalCAD.Theuserinterfaceisintuitive,easy-to-use,and

13、consistentthroughoutthedesignflow.Large,densePCBdesignswithhigh-speedinterfacescanutilizeGlobalRoutingEnvironmenttechnologyforintelligentinterconnectplanningandroutingautomation.Features/Benefits:-Providesascalable,full-featuredPCBdesignsolution-Enablesaconstraint-drivendesignflowtoreducedesignitera

14、tions-Providesasingle,consistent,front-to-backconstraintmanagementenvironment-DeliversanintegratedRF/analogdesignandmixed-signaldesignenvironment-Providesinteractivefloorplanningandcomponentplacement-Providesdesignpartitioningforlarge,disperseddevelopmentteams-Enablesreal-time,interactivepush/shovee

15、tchediting-Allowsreal-timeplowing/healingwithdynamicshapetechnology-Managesnetscheduling,timing,crosstalk,layersetrouting,andgeometricconstraints-ProvidesprovenPCBRoutertechnologyforauto-routingofrandomsignals-Capturesdesignintentforinterconnectsthroughhierarchicalflowplanning-Shortensinterconnectpl

16、anningandroutingtimefordensedesignswithhigh-speedinterfaces-Outputsdesigndatainavarietyofmanufacturingformats/products/pcb/pcb_design/pages/default.aspx1010010100010010100101000100101010010010101010011110010010010101010101011.)unpackthefiles2.)burnormounttheimage3.)install4.)CheckSHootersDirReadme.t

17、xtIfyoucantgetit-youarenotworthit.#ENJOYANOTHERFiNERELEASEBROUGHTTOYOUBYTEAMSHooTERS#1.Youworkatanyreseller,distributororsoftwarecompanyandhaveaccesstonewunreleasedsoftware2.Youareatalentedcrackerandabletohandle:Dongle,FlexLM,Armadillo,Asprotect,HASPoRWibu3.YouareakeygennerandabletohandleMD5,RSA,TEA

18、orVB4.YouhaveagoodatSecureShell/BNCorwasSiteopfromagood.EUSiteno.deor.ustocontactwritetooSHOOTERSHUSH.COMGreetingsto:Oddity,Paradox,ENiGMA,ViRiLiTY,nGENandNUll!HYPERLINKt_topPCB設(shè)計(jì)Allegro學(xué)習(xí)教程三、AllegroPCB設(shè)計(jì)教程精要第一節(jié)Allegro元件封裝組成在我們進(jìn)行一個(gè)電子產(chǎn)品設(shè)計(jì)時(shí),先要繪制好電路原理圖.Allegro系統(tǒng)有兩種繪制原理圖的方法可供選擇,他們是Concept和Capture.選擇Orca

19、dcapture繪制電路原理圖可以說是更普遍的選擇,本文講述的也是從Capture到Allegro.至于OrcadCapture軟件的使用請(qǐng)參考有關(guān)書籍,本書就不再介紹.用OrcadCapture繪制好電路原理圖以后,下一個(gè)PCB設(shè)計(jì)流程為建立元件封裝.在Allegro中,元件的封裝包括Padstack,Symbol和Device三部分.如圖4-1-1所示圖形為SOP14型封裝的PackageSymbol圖.圖4-1-1SOP14封裝圖Padstack元件封裝焊盤,*.PAD圖形文件,有插針式焊盤和貼片式焊盤兩種.如圖3-5-1所示的SOP14封裝有十四個(gè)圓角矩形貼片焊盤.Symbol可編輯的

20、元件封裝外形,沒任何電氣特性.Symbol中包含Padstack和元件封裝外框等圖形符號(hào).如圖3-5-1所示即為SOP14的Symbol.Device元件封裝的電氣特性描述文本文件,此文件包含元件封裝的Symbol信息及腳位定義等.如元件在布線時(shí)會(huì)做門電路或腳位互換的動(dòng)作則必須在Device文件中定義.例如SN74LS00的封裝為SOP14,其Device文件SOP14.TXT描述如下:(DEVICEFILE:SOP14)PACKAGESOP14CLASSICPINCOUNT14PINORDERSOP14ABYPINUSESOP14ININOUTPINSWAPSOP14ABFUNCTIONG1

21、SOP14123FUNCTIONG2SOP14456FUNCTIONG3SOP149108FUNCTIONG4SOP14121311GROUNDGND;7POWERVCC;14END所有元件的Padstack組成一子目錄,所有元件的Symbol組成一子目錄,所有元件的Device組成一子目錄.此三個(gè)子目錄就構(gòu)成了元件封裝中央零件庫.第二節(jié)焊盤設(shè)計(jì)器介紹一、啟動(dòng)焊盤設(shè)計(jì)器執(zhí)行開始/程序/Cadencepsd14.2/AllegroUtilities/PadstackEditor,啟動(dòng)焊盤設(shè)計(jì)器,如圖4-2-1所示.圖4-2-1焊盤設(shè)計(jì)器二、焊盤設(shè)計(jì)器菜單1、File欄(1)、New:新建焊盤。(

22、2)、Open:打開焊盤。(3)、Save:以當(dāng)前文件名保存當(dāng)前設(shè)計(jì)。(4)、SaveAs:將當(dāng)前設(shè)計(jì)以另一文件名保存。(5)、Check:檢查當(dāng)前設(shè)計(jì)中的錯(cuò)誤。(6)、Properties(7)、scripting(8)、Exit2、Reports欄(1)、PadstackSummary三、焊盤設(shè)計(jì)器界面(1).Parameters介紹.如圖4-2-2所示.圖4-2-2PadstackParameters圖Type欄:在此欄定義設(shè)計(jì)焊盤的類型Through選擇此項(xiàng)表示要設(shè)計(jì)一個(gè)插針式焊盤.Blind/Buried選擇此項(xiàng)表示要設(shè)計(jì)一個(gè)盲/埋孔.Single選擇此項(xiàng)表示要設(shè)計(jì)一個(gè)貼片式焊盤.Internallayers欄:控制單一的沒與任何其它網(wǎng)絡(luò)連接的焊盤在出內(nèi)層Gerber時(shí)的輸出方式.Fixed鎖定焊盤,在輸出內(nèi)層Gerber時(shí)不能設(shè)置單一焊盤的輸出方式,會(huì)按照本來面貌輸出.Optional選擇此項(xiàng),可以允許在輸出內(nèi)層Gerber時(shí)通過設(shè)置ArtworkControlForm中FilmControl欄的SuppressUnconnectedpads來控制單一焊盤的輸出方式.如你現(xiàn)在對(duì)Internallayers欄的設(shè)置不是很清楚,請(qǐng)選擇Optional項(xiàng).Units欄:單位及精度選擇欄.Units點(diǎn)擊下拉菜單,有