2014下-自動化數(shù)字邏輯設計課件1第五章

1、Chapter 5Combinational Logic Design PracticesDigital Design Pinciples and PracticesDigital Design Pinciples and PracticesDocumentation StandardsDocumentation (文檔) 1. Ciruit specification：線路的詳細說明。2. Block Diagram：方框圖，系統(tǒng)的主要功能模塊 及其基本互連的非正式圖示說明。3. Schematic Diagram：原理圖，元件及互連的詳細圖示。4. Bill of Materials (B

2、OM)：材料清單，一般由原理圖生成。5. Timing diagram：定時圖(波形圖)，輸入、輸出等波形 的時間關系，包括其延時。6. Circuit Description：電路內(nèi)部功能的描述。Documentation Standards Block Diagram 顯示系統(tǒng)的輸入、輸出、功能模塊內(nèi)部數(shù)據(jù)通路和重要控制信號等。BUS (總線) Bus is a collection of two or more related signal lines. In a block diagram, buses are drawn with a double or heavy line.Bus

3、 name Data31.0 Address31:0Documentation Standards Block Diagram 移位相加乘法器Documentation Standards Gate Symbols Documentation Standards Gate Symbols Equivalent Gate SymbolsInverter (反相器)Buffer (緩沖器)Documentation Standards Signal Name and Active Levels Name a Signal (信號的命名) 最好以字母開頭，可包含下劃線和數(shù)字。An Active Le

4、vel Associated with a Signal (與信號相關的有效電平) 信號的描述以 有效 / 無效 來取代 高 / 低，1 / 0Active High （高電平有效）Active Low （低電平有效）Documentation Standards Signal Name and Active Levels Active LowActive HighREADY-READY+ERROR.LERROR.HADDR15(L)ADDR15(H)RESET*RESETENABLEENABLEGOGO/RECEIVERECEIVETRANSMIT_LTRANSMITDocumentatio

5、n Standards Signal Name and Active Levels Signal NamesExpressions Equations DistinguishREADYREADY , READY_LREADY_L = READYDocumentation Standards Active Levels for PinsAn Inversion Bubble to Indicate an Active-Low Pin(有反相圈的引腳 表示低電平有效)與門可描述為：所有輸入有效時，輸出才有效?；蜷T可描述為：一個輸入有效時，輸出就有效。反相器/緩沖器可描述為：當且僅當輸入有效時，輸出

6、才有效。Documentation Standards Active Levels for Pins內(nèi)部電路相同，只是描述方式不同。Documentation Standards Bubble-to-Bubble Logic Design反相門快于非反相門，采用“低電平有效”更有意義。ANDNORSlowFastDocumentation Standards Bubble-to-Bubble Logic DesignEasy to understand信號與器件引腳的有效電平應保持一致！Documentation Standards Drawing Layout 相連交叉線應采用 T 型畫法！

7、而非十字畫法！Crossing LineDocumentation Standards Drawing Layout MultipleSchematic 不同頁中的同名信號等同于連在一起！Hierarchical Structure功能模塊可重用BusesPage No.Documentation Standards Additional Schematic InformationIC TypeReference DesignatorPin No.Circuit Timing A signal path as the time that it takes for a change at the

8、 Input to produce a change at the Output of the path.(信號通路輸入端的變化引起輸出端變化所需的時間)t HL and t LH may be different Propagation Delay (傳播延遲)t pHL : Propagation delay from High to Lowt pLH : Propagation delay from Low to HighVINVOUTt tLH : Transition time from Low to Hight tHL : Transition time from High to

9、Lowt tLHt tHLt pHLt pLHCircuit Timing Timing Diagram(定時圖/時序圖)GOREADYDATGOREADYDATtpDATtpDATtpRDYtpRDY因果關系取中間點Circuit Timing Timing Diagram(定時圖/時序圖)Propagation Delay (傳播延遲)Maximum Delay (最大延遲)Typical Delay (典型延遲)Minimum Delay (最小延遲)最壞情況延遲：即選取 t pHL 和 t pLH 中的最大者作為計算延遲Circuit Timing Timing Diagram(定時圖/時序圖)Certain