計(jì)算機(jī)組成原理課程設(shè)計(jì)vhdl設(shè)計(jì)cpu

1、 TOC o 1-5 h z 課程設(shè)計(jì)目的3開發(fā)工具選擇3方案選擇3指令系統(tǒng)設(shè)計(jì)4模型機(jī)框圖設(shè)計(jì)4指令流程圖5微指令格式（微程序控制器）設(shè)計(jì)6微程序（微程序控制器）設(shè)計(jì)7VHDL程序代碼9調(diào)試仿真16課程設(shè)計(jì)回顧總結(jié) 18參考文獻(xiàn)18課程設(shè)計(jì)目的（1）、計(jì)算機(jī)組成原理課程設(shè)計(jì)的主要任務(wù)是讓學(xué)生通過動(dòng)腦和動(dòng)手解決計(jì)算機(jī)設(shè)計(jì)中的實(shí) 際問題。綜合運(yùn)用所學(xué)計(jì)算機(jī)組成原理知識(shí)，在掌握部件單元電路實(shí)驗(yàn)的基礎(chǔ)上，進(jìn)一步將 其組成系統(tǒng)構(gòu)造一臺(tái)基本的模型計(jì)算機(jī)，掌握整機(jī)概念，并設(shè)計(jì)機(jī)器指令系統(tǒng)，編寫程序， 在所設(shè)計(jì)的模型計(jì)算機(jī)上調(diào)試運(yùn)行。（2）、通過一臺(tái)模型機(jī)的設(shè)計(jì)過程，明確計(jì)算機(jī)的控制原理與控制過程，鞏固和靈

2、活應(yīng)用所 學(xué)的理論知識(shí)，掌握計(jì)算機(jī)組成的一般設(shè)計(jì)方法，提高學(xué)生設(shè)計(jì)能力和實(shí)踐操作技能，為從 事計(jì)算機(jī)研制與設(shè)計(jì)打下基礎(chǔ)。開發(fā)工具選擇使用QUARTUS 5.0軟件編寫并調(diào)試VHDL程序，然后做功能仿真。方案選擇本次實(shí)習(xí)的內(nèi)容為16位模型計(jì)算機(jī)的設(shè)計(jì)，單總線，采用微程序控制方式，有四種尋 址方式：直接尋址、寄存器尋址、寄存器間接尋址和變址尋址。微程序控制方式由微指令譯碼產(chǎn)生。微程序中一條機(jī)器指令往往分成幾步執(zhí)行，將每一 步操作所需的若干為命令以代碼編寫在一條微指令中，若干條微指令組成一段微程序，對(duì)應(yīng) 一條機(jī)器指令。然后根據(jù)系統(tǒng)的需要，事先編制各段微程序，將它存入一個(gè)專用寄存器（即 控制存儲(chǔ)器）中

3、。微程序執(zhí)行過程：如圖1所示，為微程序控制基本框：（1）從控存中逐條取出“取指令操作”，執(zhí)行取指令公共操作。（2）根據(jù)指令的操作碼，經(jīng)過微地址形成部件，得到這條指令的入口地址，并送入微 地址寄存器中。（3）從控存中逐條的取出對(duì)應(yīng)的微指令并執(zhí)行。（4）執(zhí)行完一條機(jī)器指令對(duì)應(yīng)的微程序后又回到取指微程序的入口地址，繼續(xù)第（1） 步，以完成取下一條機(jī)器指令的公共操作。2圖1微程序控制基本框4.指令系統(tǒng)設(shè)計(jì)Q操作碼目的操作數(shù)尋址方式目的操作數(shù)源操作數(shù)尋址方式源操作數(shù)模擬機(jī)采用了定長的指令格式，每條指令字長為16位。采用的尋址方式為直接尋址（00）、 寄存器尋址（01）、寄存器間接尋址（10）和變址尋址（

4、11）,操作碼類型及編碼方式如下操作碼staaddsuband1or1shl編碼方式000000010010001101000101模型機(jī)框圖設(shè)計(jì)模擬機(jī)數(shù)據(jù)通路如圖2所示，模型機(jī)采用單總線結(jié)構(gòu)，主要包括運(yùn)部件ALU,以及程 序計(jì)數(shù)器PC、累加器ACC、指令寄存器IR、數(shù)據(jù)寄存器MDR、地址寄存器MAR和通用 寄存器R, RAM為內(nèi)存圖2：模型機(jī)數(shù)據(jù)通路（1）寄存器的位數(shù)：所有的寄存器都均為16位A通用寄存器R0, R1該模擬機(jī)有2個(gè)通用寄存器，用于提供操作數(shù)。B指令寄存器IR為了提高取指令的速度，將指令從內(nèi)存中讀出，經(jīng)數(shù)據(jù)總線直接置入IR。C數(shù)據(jù)寄存器MDR、地址寄存器MAR地址寄存器MAR提

5、供訪問主存的地址；數(shù)據(jù)寄存器MDR，把從內(nèi)存取出的數(shù)據(jù)暫存于MDR中，在用到該數(shù)據(jù)進(jìn)行運(yùn)算時(shí)， 再從MDR中取出數(shù)據(jù)進(jìn)行運(yùn)算。D程序計(jì)數(shù)器PC用于存放下一條指令的內(nèi)存地址。（2）總線寬度：該模擬機(jī)只有一條總線，且總線寬度為16位。（3）ALU位數(shù)及運(yùn)算功能ALU可以實(shí)現(xiàn)16位操作數(shù)的運(yùn)算，即ALU的位數(shù)為16位。ALU運(yùn)算功能為：可以實(shí)現(xiàn)簡單的加（0001： add）、減（0010： sub）、邏輯與（0011： andl）、或（0100： or1）操作。（4）微命令的設(shè)置（各標(biāo)識(shí)的含義）經(jīng)過認(rèn)真分析各信息傳送路徑，對(duì)指令過程基本掌握，并為相應(yīng)的微命令做了一下設(shè)置:1716PC loadbus

6、 IR3029ACC ACCaddD addC333215 load .MAR28D_ bus 3114MDRbus27loadD13load-MDR26C_bus121716PC loadbus IR3029ACC ACCaddD addC333215 load .MAR28D_ bus 3114MDRbus27loadD13load-MDR26C_bus12ALUACC25loadC11INCPC24R1_bus10987AddrCS busR_ ALUNW addALUsub5-0地址23222120load R0 load loadR1 bus R0 PC19ACC18loadbus

7、ACCALUALUALUand or srl指令流程圖指令的流程圖如圖3所示，共有6條指令，每條指令都要經(jīng)過取指令、分析指令和執(zhí) 行指令3個(gè)步驟。在取指令階段，8條指令是一樣的，首先程序計(jì)數(shù)器PC的內(nèi)容通過總線送入地址寄存 器MAR，存儲(chǔ)信息，PC+1傳送給PC，把讀出的內(nèi)容傳送給指令寄存器IR。再接下來的 操作中，根據(jù)不同的指令，執(zhí)行順序也不同。圖3指令流程圖微指令格式（微程序控制器）設(shè)計(jì)微指令格式設(shè)計(jì)如表：控制信號(hào)描 述load_PC將總線上的數(shù)據(jù)裝載至PCACC_bus用ACC的內(nèi)容驅(qū)動(dòng)總線load_ACC將總線上的數(shù)據(jù)載入ACCPC_bus用PC的內(nèi)容驅(qū)動(dòng)總線load_IR將總線上的數(shù)

8、據(jù)裝載至IRload_MAR將總線上的數(shù)據(jù)裝載至MARMDR_bus用MDR的內(nèi)容驅(qū)動(dòng)總線load_MDR將總線上的數(shù)據(jù)裝載至MDRALU_ACC用ALU的結(jié)果裝載ACCINC_PCPC+1并將結(jié)果存至PC中Addr_bus用IR指令中的地址部分驅(qū)動(dòng)總線CS片選。用MAR的內(nèi)容設(shè)置存儲(chǔ)器地址R_NW讀取，不可寫。當(dāng)R_NW無效且CS有效時(shí)，MBR的內(nèi)容存儲(chǔ)于存儲(chǔ)器中ALU_addC在ALU中執(zhí)行ACC和C的邏輯加操作ALU_addD在ALU中執(zhí)行ACC和D的邏輯加操作ALU_add在ALU中執(zhí)行邏輯加操作ALU_sub在ALU中執(zhí)行減操作ALU_and在ALU中執(zhí)行與操作ALU_or在ALU中

9、執(zhí)行與操作ALU_shl在ALU中執(zhí)行左移操作R0_bus用寄存器R0的內(nèi)容驅(qū)動(dòng)總線load_R0將總線上的數(shù)據(jù)裝載至R0R1_bus用寄存器R1的內(nèi)容驅(qū)動(dòng)總線load_R1將總線上的數(shù)據(jù)裝載至R1C_bus用暫存器C的內(nèi)容驅(qū)動(dòng)總線load_C將總線上的數(shù)據(jù)裝載至CD_bus用暫存器D的內(nèi)容驅(qū)動(dòng)總線load_D將總線上的數(shù)據(jù)裝載至D表1微指令格式微程序（微程序控制器）設(shè)計(jì)根據(jù)微處理器的數(shù)據(jù)通路和指令系統(tǒng)，可得出微程序的流程圖如圖4所示。微程序的編碼采用直接編碼方法，每一個(gè)控制信號(hào)對(duì)應(yīng)一位，共有28個(gè)控制信號(hào)，根據(jù)微指令格式48456789104845678910根據(jù)圖4微程序流程圖的下地址,4

10、可程共程督條微指令，該模擬機(jī)微程序的編碼如下0= 00000000000000001010001000000000011= 00000000000000000000000011000000102= 00000000000000000101000000000000113= 00000000000000000000000000001111114= 00000000000000000000000011000001015= 00000000100000000001000000000001106= 00000000010000010000100000000001117= 0000100000000000

11、0000010000000010008= 00000000000000100010000000000010019= 000000000000000000000000110000101010= 000000001000100000010000000000000011= 000000001000000000000000000000110012= 000000000000000010100010000000110113= 000000000000000000000000110000111014= 000000100000000000010000000000111115= 00000000000100

12、0100001000000001000016= 000100000000000000000100000001000117= 000000000000001000100000000001001018= 000000000000000000000000110001001119= 000000100000000000010000000001010020= 000000000000000000000100001001010121= 000000000000001000001000000001011022= 000000000000000000000000100000000023= 0000000000

13、00000000000000110001100024= 000000001000000000010000000001100125= 000000000100000000001000000001101026= 000000100000000000000000000001101127= 000000000000000000000100000101110028= 000000000000001000001000000001110129= 000000000010000000000000000000000030= 000000001000000000000000000001111131= 000000

14、000100000000100000000010000032= 000000000000000000000000110010000133= 000001000000000000010000000010001034= 100000000000000000000100000010001135= 000000000000001000001000000010010036= 000000000000000000000000100000000037= 000000001000000000000000000010011038= 000000000100000000001000000010011139= 00

15、0000100000000000000000000010100040= 010000000000000000000100000010100141= 000000000000001000001000000010101042= 000000000010000000000000000000000043= 000000000000000000000000110010110044= 000000001000000000010000000010110145= 001000000000000000000100000010111046= 000000000000001000000000010010111147

16、= 000000000000100000000000000000000048= 000000000000000010100010000000010049= 000000000100000000001000000000101150= 000000000001000000100000000001011151= 000000000001000000001000000001111052= 000000000001000000001000000010010153= 00000000000000000010000100001010119. VHDL程序代碼-頭文件LIBRARY IEEE;USE IEEE

17、.STD_LOGIC_1164.ALL;PACKAGE cpu_defs ISTYPE opcode IS (sta, add, sub,and1,or1, shl,jmp, nop);TYPEregcode IS (r0, r1);TYPExzhcode IS (zh,j,jj,bi);CONSTANT word_w: NATURAL :=16;CONSTANT op_w: NATURAL :=4;CONSTANT reg_w: NATURAL :=4;CONSTANT xzh_w: NATURAL :=2;CONSTANT rfillop: STD_LOGIC_VECTOR(op_w-1

18、downto 0):=(others =0);CONSTANT rfillreg: STD_LOGIC_VECTOR(reg_w-1 downto 0):=(others =0);CONSTANT rfillxzh: STD_LOGIC_VECTOR(xzh_w-1 downto 0):=(others =0);-FUNCTIOn slv2op(slv:IN STD_LOGIC_VECTOR) RETURN opcode;FUNCTION op2slv(op:in opcode) RETURN STD_LOGIC_VECTOR;FUNCTION regslv(reg:in regcode) R

19、ETURN STD_LOGIC_VECTOR;FUNCTION xzhslv(xzh:in xzhcode) RETURN STD_LOGIC_VECTOR;END PACKAGE cpu_defs;PACKAGE BODY cpu_defs ISTYPE optable IS ARRAY(opcode) OF STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);TYPE regtable IS ARRAY(regcode) OF STD_LOGIC_VECTOR(reg_w-1 DOWNTO 0);TYPE xzhtable IS ARRAY(xzhcode) OF STD_

20、LOGIC_VECTOR(xzh_w-1 DOWNTO 0);CONSTANT trans_tableop:optable :=(0000, 0001, 0010, 0011, 0100, 0101, 0110,0111);CONSTANT trans_tabler:regtable :=(0000”,0001”);CONSTANT trans_tablex:xzhtable :=(00”,01”,10”,11”);FUNCTION op2slv(op:IN opcode) RETURN STD_LOGIC_VECTOR ISBEGINRETURN trans_tableop(op);END

21、FUNCTION op2slv;FUNCTION regslv(reg:in regcode) RETURN STD_LOGIC_VECTOR ISBEGINRETURN trans_tabler(reg);END FUNCTION regslv;FUNCTION xzhslv(xzh:in xzhcode) RETURN STD_LOGIC_VECTOR ISBEGINRETURN trans_tablex(xzh);END FUNCTION xzhslv;END PACKAGE BODY cpu_defs;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL,I

22、EEE.NUMERIC_STD.ALL;USE WORK.CPU_DEFS.ALL;ENTITY CPU ISPORT( clock : IN STD_LOGIC;reset: IN STD_LOGIC;mode: IN STD_LOGIC_VECTOR(3 DOWNTO 0);mem_addr : INUNSIGNED(word_w-op_w-1 DOWNTO 0);output: OUTSTD_LOGIC_VECTOR(word_w-1 DOWNTO 0);data_r_out : OUT STD_LOGIC_VECTOR(33 DOWNTO 0);op_out: OUTSTD_LOGIC

23、_VECTOR(op_w-1 DOWNTO 0);add_r_out: OUTUNSIGNED(5 DOWNTO 0);END ENTITY;ARCHITECTURE rtl OF CPU ISTYPE mem_array IS ARRAY (0 TO 2*5) OF STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);SIGNAL mem : mem_array;CONSTANT prog : mem_array:=(0= op2slv(sta) & xzhslv(j) & regslv(r0)& xzhslv(bi)& regslv(r1),1= STD_LOGIC_V

24、ECTOR(TO_UNSIGNED(3,word_w),2= op2slv(add) & xzhslv(bi)& regslv(r0)& xzhslv(j) & regslv(r1),3= STD_LOGIC_VECTOR(TO_UNSIGNED(0,word_w),4= op2slv(sub) & xzhslv(j) & regslv(r1) & xzhslv(jj)& regslv(r0),5= op2slv(and1)& xzhslv(jj)& regslv(r1)& xzhslv(j) & regslv(r0),6= op2slv(or1) & xzhslv(j) & regslv(r

25、l) & xzhslv(j) & regslv(r0),7= op2slv(shl) & xzhslv(j) & regslv(r0) & xzhslv(zh)& STD_LOGICVECTOR(TO_UNSIGNED(10,reg_w),8= STD_LOGIC_VECTOR(TO_UNSIGNED(9,word_w),9= STD_LOGIC_VECTOR(TO_UNSIGNED(8,word_w),10= STD_LOGIC_VECTOR(TO_UNSIGNED(15,word_w),OTHERS = (OTHERS =0);TYPE microcode_array IS ARRAY (

26、0 TO 53) OF STD_LOGIC_VECTOR(33 DOWNTO 0);CONSTANT code : microcode_array:=(0= 0000000000000000101000100000000001”,1= 0000000000000000000000001100000010,2= 0000000000000000010100000000000011,3= 0000000000000000000000000000111111,4= 0000000000000000000000001100000101,5= 000000001000000000010000000000

27、0110,6= 0000000001000001000010000000000111,7= 0000100000000000000001000000001000,8= 0000000000000010001000000000001001,9= 0000000000000000000000001100001010,10= 0000000010001000000100000000000000,11= 0000000010000000000000000000001100,12= 0000000000000000101000100000001101,13= 0000000000000000000000

28、001100001110,14= 0000001000000000000100000000001111,15= 0000000000010001000010000000010000,16= 0001000000000000000001000000010001,17= 0000000000000010001000000000010010,18= 0000000000000000000000001100010011,19= 0000001000000000000100000000010100,20= 0000000000000000000001000010010101,21= 0000000000

29、000010000010000000010110,22= 0000000000000000000000001000000000,23= 0000000000000000000000001100011000,24= 0000000010000000000100000000011001,25= 0000000001000000000010000000011010,26= 0000001000000000000000000000011011,27= 0000000000000000000001000001011100,28= 0000000000000010000010000000011101,29

30、= 0000000000100000000000000000000000,30= 0000000010000000000000000000011111,31= 0000000001000000001000000000100000,32= 0000000000000000000000001100100001,33= 0000010000000000000100000000100010,34= 1000000000000000000001000000100011,35= 0000000000000010000010000000100100”,36= 000000000000000000000000

31、1000000000,37= 0000000010000000000000000000100110,38= 0000000001000000000010000000100111,39= 0000001000000000000000000000101000,40= 0100000000000000000001000000101001,41= 0000000000000010000010000000101010,42= 0000000000100000000000000000000000,43= 0000000000000000000000001100101100,44= 000000001000

32、0000000100000000101101,45= 0010000000000000000001000000101110,46= 0000000000000010000000000100101111,47= 0000000000001000000000000000000000,48= 0000000000000000101000100000000100,49= 0000000001000000000010000000001011,50= 0000000000010000001000000000010111,51= 0000000000010000000010000000011110,52=

33、0000000000010000000010000000100101,53= 0000000000000000001000010000101011);SIGNAL countSIGNAL opSIGNAL z_flagSIGNAL mdr_outSIGNAL countSIGNAL opSIGNAL z_flagSIGNAL mdr_outSIGNAL mar_outSIGNAL IR_outSIGNAL acc_out:STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);:STD_LOGIC;:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);:UNSI

34、GNED(reg_w-1 DOWNTO 0);:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);:UNSIGNED(word_w-1 DOWNTO 0);SIGNAL sysbus_out : STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);SIGNAL cc : STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);SIGNAL rr1 : STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);BEGINPROCESS(reset,clock)VARIABLE instr_reg : STD_LOGIC_VE

35、CTOR(word_w-1 DOWNTO 0);-IRVARIABLE accCONSTANT zeroVARIABLE mdrVARIABLE accCONSTANT zeroVARIABLE mdrVARIABLE r0VARIABLE r1VARIABLE cVARIABLE dVARIABLE marVARIABLE sysbus:UNSIGNED(word_w-1 DOWNTO 0):=(OTHERS =0);:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);:STD_LOGIC_VEC

36、TOR(word_w-1 DOWNTO 0);:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);:UNSIGNED(word_w-1 DOWNTO 0);:UNSIGNED(reg_w-1 DOWNTO 0);:STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);VARIABLE microcode : microcode_array;VARIABLE add_rVARIABLE data_rVARIABLE temp BEGINVARIABLE add_rVARIABLE data_rVARIABLE temp BEGIN:STD_LOGIC_VE

37、CTOR(33 DOWNTO 0);:STD_LOGIC_VECTOR(5 DOWNTO 0);IF reset=0 THENadd_r:=(OTHERS =0);count 0);instr_reg := (OTHERS =0);acc := (OTHERS =0);mdr := (OTHERS =0);mar := (OTHERS =0);z_flag =0;mem 0);r0 :=x0005”;r1 :=x0006;c := (OTHERS =0);d := (OTHERS =0);ELSIF RISING_EDGE(clock) THEN-microprogram controller

38、data_r := code(TO_INTEGER(add_r);IF data_r(5 DOWNTO 0)=111111 THEN -判斷下地址 temp:=11 & op(3 DOWNTO 0);add_r := UNSIGNED(temp);ELSEadd_r := UNSIGNED(data_r(5 DOWNTO 0);END IF;data_r_out =data_r;add_r_out = add_r;-PCIF data_r(17)=1 THEN -PC_bus=1sysbus := rfillop & STD_LOGIC_VECTOR(count);END IF;IF data

39、_r(20)=1 THEN -load_PC=1count = UNSIGNED(mdr(word_w-op_w-1 DOWNTO 0);ELSIF data_r(11)=1 THEN -INC_PC=1 count = count+1;ELSEcount = count;END IF;-IRIF data_r(16)=1 THEN -load_IR instr_reg := mdr;END IF;IF data_r(10)=1 THEN -Addr_bus=1 sysbus := rfillop & rfillxzh & rfillreg & rfillxzh & instr_reg(reg

40、_w-1DOWNTO 0);END IF;op = instr_reg(word_w-1 DOWNTO word_w-op_w);IR_out = instr_reg;op_out =op;-ALUIF data_r(22)=1 THEN -R0_bus=1sysbus := STD_LOGIC_VECTOR(r0);END IF;IF data_r(21)=1 THEN -load_R0=1 r0:= mdr;END IF;IF data_r(24)=1 THEN -R1_bus=1sysbus := STD_LOGIC_VECTOR(r1);END IF;IF data_r(23)=1 T

41、HEN -load_R1=1 r1:= mdr;END IF;IF data_r(26)=1 THEN -c_bus=1 sysbus := STD_LOGIC_VECTOR(c);END IF;IF data_r(25)=1 THEN -load_c=1 c:= mdr;END IF;IF data_r(28)=1 THEN -d_bus=1 sysbus := STD_LOGIC_VECTOR(d);END IF;IF data_r(27)=1 THEN -load_d=1 d:= UNSIGNED(mdr);END IF;IF data_r(19)=1 THEN -ACC_bus=1 s

42、ysbus := STD_LOGIC_VECTOR(acc);END IF;IF data_r(18)=1 THEN -load_ACC=1acc:=UNSIGNED(sysbus);END IF;IF data_r(14)=1 THEN -MDR_bus=1 sysbus:=mdr;END IF;IF data_r(12)=1 THEN -ALU_ACC=1IF data_r(6)=1 THEN -ALU_sub=1 acc := UNSIGNED(c)-d;ELSIF data_r(7)=1 THEN -ALU_add=1 acc := UNSIGNED(c)+d;ELSIF data_r(29)=1 THEN -ALU_add_c=1 acc := UNSIGNED(c)+acc;ELSIF data_r(30)=1 THEN -ALU_add_d=1 acc := UNSIGNED(d)+acc;ELSIF data_r(33)=1 THEN -ALU_and=1 acc := UNSIGNED(c) and d;E