計算機組織與結(jié)構(gòu)：版7-12-Processor Structure and Function

WilliamStallings

ComputerOrganization

andArchitecture

7thEditionChapter12CPUStructureandFunction1/60Keytermsinstructioncycleinstructionpipelineinstructionprefetchpipelineinstructionpipelineconditioncodeflagbranchpredictionbranchpredictiondelayedbranchprogramstatusword(PSW)2CPUStructureCPUmust:FetchinstructionsInterpretinstructionsFetchdataProcessdataWritedata3CPUWithSystemsBus4CPUInternalStructure5RegistersCPUmusthavesomeworkingspace(temporarystorage)CalledregistersNumberandfunctionvarybetweenprocessordesignsOneofthemajordesigndecisionsToplevelofmemoryhierarchy6UserVisibleRegistersGeneralPurposeDataAddressConditionCodes7GeneralPurposeRegisters(1)MaybetruegeneralpurposeMayberestrictedMaybeusedfordataoraddressingDataAccumulatorAddressingSegment8GeneralPurposeRegisters(2)MakethemgeneralpurposeIncreaseflexibilityandprogrammeroptionsIncreaseinstructionsize&complexityMakethemspecializedSmaller(faster)instructionsLessflexibilitySpecialized英音：['spe??laizd]1.特化2.專門1.專門的，專用的9HowManyGPRegisters?Between8-32Fewer=morememoryreferencesMoredoesnotreducememoryreferencesandtakesupprocessorrealestateSeealsoRISC

Estate英音：[is'teit]屋；產(chǎn)業(yè)

10Howbig?LargeenoughtoholdfulladdressLargeenoughtoholdfullwordOftenpossibletocombinetwodataregistersCprogrammingdoubleinta;longinta;11ConditionCodeRegistersSetsofindividualbitse.g.resultoflastoperationwaszeroCanberead(implicitly)byprogramse.g.JumpifzeroCannot(usually)besetbyprogramsindividual英音：[,indi'vidju?l]個別的，個人的，單獨的

12Control&StatusRegistersProgramCounter(PC)InstructionDecodingRegister(IDR)MemoryAddressRegister(MAR)MemoryBufferRegister(MBR)Revision:whatdothesealldo?

Revision復習

13ProgramStatusWord(PSW)AsetofbitsIncludesConditionCodesSignoflastresultZeroCarryEqualOverflowInterruptenable/disableSupervisor

Supervisor監(jiān)督人;管理人;指導者

14SupervisorModeIntelringzeroKernelmodeAllowsprivilegedinstructionstoexecuteUsedbyoperatingsystemNotavailabletouserprograms

privileged英音：['privilid?d]特許的，有特權(quán)的

15OtherRegistersMayhaveregisterspointingto:Processcontrolblocks(seeO/S)InterruptVectors(seeO/S)N.B.CPUdesignandoperatingsystemdesignarecloselylinked16ExampleRegisterOrganizations17InstructionCycleRevisionStallingsChapter318IndirectCycleMayrequirememoryaccesstofetchoperandsIndirectaddressingrequiresmorememoryaccessesCanbethoughtofasadditionalinstructionsubcycle19InstructionCyclewithIndirect20InstructionCycleStateDiagram21DataFlow(InstructionFetch)DependsonCPUdesignIngeneral:FetchPCcontainsaddressofnextinstructionAddressmovedtoMARAddressplacedonaddressbusControlunitrequestsmemoryreadResultplacedondatabus,copiedtoMBR,thentoIRMeanwhilePCincrementedby122DataFlow(DataFetch)IRisexaminedIfindirectaddressing,indirectcycleisperformedRightmostNbitsofMBRtransferredtoMARControlunitrequestsmemoryreadResult(addressofoperand)movedtoMBR23DataFlow(FetchDiagram)(1)(2)(2)(3)(4)24DataFlow(IndirectDiagram)(1)(1)(2)25DataFlow

(IndirectDiagram)(1)(2)(2)(3)(5)(4)(6)(7)(8)26DataFlow(Execute)MaytakemanyformsDependsoninstructionbeingexecutedMayincludeMemoryread/writeInput/OutputRegistertransfersALUoperations27DataFlow(Interrupt)SimplePredictableCurrentPCsavedtoallowresumptionafterinterruptContentsofPCcopiedtoMBRSpecialmemorylocation(e.g.stackpointer)loadedtoMARMBRwrittentomemoryPCloadedwithaddressofinterrupthandlingroutineNextinstruction(firstofinterrupthandler)canbefetched28DataFlow(InterruptDiagram)(2)(3)(1)(4)(5)29PrefetchFetchaccessingmainmemoryExecutionusuallydoesnotaccessmainmemoryCanfetchnextinstructionduringexecutionofcurrentinstructionCalledinstructionprefetch

prefetch預讀取(文件夾)

30ImprovedPerformanceButnotdoubled:FetchusuallyshorterthanexecutionPrefetchmorethanoneinstruction?AnyjumporbranchmeansthatprefetchedinstructionsarenottherequiredinstructionsAddmorestagestoimproveperformance31PipeliningFetchinstructionDecodeinstructionCalculateoperands(i.e.EAs)FetchoperandsExecuteinstructionsWriteresultOverlaptheseoperationsPipelining英音：[,paip‘laini?](電腦)流水線操作技術(shù)

overlap英音：['?uv?'l?p]與...部分重疊

32TwoStageInstructionPipeline33TimingDiagramfor

InstructionPipelineOperation34TheEffectofaConditionalBranchonInstructionPipelineOperationpenalty英音：['pen?lti]處罰;刑罰

35SixStage

InstructionPipeline36AlternativePipelineDepictionDepiction英音：[di'pik??n]描寫;敘述

37SpeedupFactors

withInstruction

Pipeliningk=6,n=100,Sk=?38DealingwithBranchesMultipleStreamsPrefetchBranchTargetLoopbufferBranchpredictionDelayedbranching39MultipleStreamsHavetwopipelinesPrefetcheachbranchintoaseparatepipelineUseappropriatepipelineLeadstobus®istercontentionMultiplebranchesleadtofurtherpipelinesbeingneeded

ADDA,BJZ100

SUBA,BJNZ20040PrefetchBranchTargetTargetofbranchisprefetchedinadditiontoinstructionsfollowingbranchKeeptargetuntilbranchisexecutedUsedbyIBM360/9141LoopBufferVeryfastmemoryMaintainedbyfetchstageofpipelineCheckbufferbeforefetchingfrommemoryVerygoodforsmallloopsorjumpsc.f.cacheUsedbyCRAY-142LoopBufferDiagram43BranchPrediction(1)PredictnevertakenAssumethatjumpwillnothappenAlwaysfetchnextinstruction68020&VAX11/780VAXwillnotprefetchafterbranchifapagefaultwouldresult(O/SvCPUdesign)PredictalwaystakenAssumethatjumpwillhappenAlwaysfetchtargetinstruction44BranchPrediction(2)PredictbyOpcodeSomeinstructionsaremorelikelytoresultinajumpthanthersCangetupto75%successTaken/NottakenswitchBasedonprevioushistoryGoodforloops45BranchPrediction(3)DelayedBranchDonottakejumpuntilyouhavetoRearrangeinstructions46BranchPredictionFlowchart47BranchPredictionStateDiagram(11)(10)(00)(01)48DealingWith

BranchesDJNZ120.If(Acc=0)goto150.

1001200130150149Intel80486PipeliningFetchFromcacheorexternalmemoryPutinoneoftwo16-byteprefetchbuffersFillbufferwithnewdataassoonasolddataconsumedAverage5instructionsfetchedperloadIndependentofotherstagestokeepbuffersfullDecodestage1Opcode&address-modeinfoAtmostfirst3bytesofinstructionCandirectD2stagetogetrestofinstructionDecodestage2ExpandopcodeintocontrolsignalsComputationofcomplexaddressmodesExecuteALUoperations,cacheaccess,registerupdateWritebackUpdateregisters&flagsResultssenttocache&businterfacewritebuffers50804