制備基本流程課件

2.1

CMOS制造工藝流程簡介

We

will

describe

a

modern

CMOS

process

flow.Process

described

here

requires

16

masksand

>

100

process

steps.1第二章CMOS制備基本流程2.1CMOS制造工藝流程簡介WewilldStagesofICFabrication2StagesofICFabrication2?

In

the

simplest

CMOS

technologies,

we

need

to

realizesimply

NMOS

and

PMOS

transistors

forcircuits

like

those

illustrated

below.CMOS

Digital

Gates反相電路或非門：同時輸入低電平時才能獲得高電平輸出3?InthesimplestCMOStechnPMOS

and

NMOSwafer

crosssection

afterfabrication2-Level

Metal

CMOS兩層互連布線的CMOS4有源器件（MOS、BJT等類似器件），必須在外加適當(dāng)?shù)钠秒妷呵闆r下，器件才能正常工作。對于MOS管，有源區(qū)分為源區(qū)和漏區(qū)，在進(jìn)行互聯(lián)之前，兩者沒有差別。PMOSandNMOS2-LevelMetalCMO????????Choosing

a

SubstrateActive

RegionN

and

P

WellGateTip

or

ExtensionSource

and

DrainContact

and

Local

InterconnectMultilevel

MetalizationProcessing

Phases5?ChoosingaSubstrateProcessin1

μmPhotoresist40

nmSiO2Choose

the

substrate(type,

orientation,resistivity,

wafer

size)?

Initial

processing: -

Wafer

cleaning -

thermal

oxidation,

H2O

(≈

40

nm,

15

min.

@

900oC) -

nitride

LPCVD(低壓化學(xué)氣相沉積)

(≈

80

nm@

800oC)?

Substrate

selection:-moderately

high

resistivity(25-50

ohm-cm)-(100)

orientation-P-

type.80

nmSi3N4Choosing

a

SubstrateSi,(100),PType,25~50Ωcm1st

Mask

Photoresist

?

spinning

and

baking@

100oC(≈

0.5

-

1.0

μm)62.2有源區(qū)的形成1μmPhotoresist40nmSiO2Choo?

Photolithography-Mask

#1

pattern

alignmentand

UV

exposure-Rinse

away

non-pattern

PR-Dry

etch

the

Nitride

layer--Plasma

etch

with

FluorineCF4

or

NF4

Plasma-Strip

Photoresist(H2SO4或O2plasma)Active

Area

Definition(主動區(qū))SiO2Si3N4Photoresist7?PhotolithographyActiveAre?

Wet

Oxide

(thick

SiO2)-

H2O

(≈

500

nm,90min.

@1000oC)?

Strip

Nitride

layer

-

Phosophoric

acid(磷酸)

orplasma

etch，選擇性問題Field

Oxide

Growth

-

LOCOS:

Local

Oxidation

ofSilicon(局部硅氧化工藝)SiO2Si3N4?

薄的SiO2層，厚的Si3N4層，避免鳥喙(bird’sbeak)的影響8?場區(qū):很厚的氧化層，位于芯片上不做晶體管、電極接觸的區(qū)域，可以起到隔離晶體管的作用。?WetOxide(thickSiO2)??

Photolithography(套刻)-

Mask

#2

pattern

alignmentand

UV

exposure?

IonImplantation離子注入

-

B+

ion

bombardmentPenetrate

thin

SiO2

and

fieldSiO2

--反型：半導(dǎo)體表面的少數(shù)載流子濃度等于體內(nèi)的多數(shù)載流子濃度時，半導(dǎo)體表面開始反型。-

150-200keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentrationP-well

Fabrication?

Strip

Photoresist-

Rinse

away

non-pattern

PR2.3N阱和P阱的形成SiO2Photoresist9?Photolithography(套刻)?I?

Ion

Implantation

-

P+

ion

bombardment-

Penetrate

thin

SiO2

and

field

SiO2-

300-400keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentration?

Strip

PhotoresistN-well

Fabrication?

Photolithography

-Mask

#3

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR10?IonImplantation-Penetr?

ThermalAnneal(熱退火)-

Repair

crystal

lattice

structuredamage

due

to

implantation?

Dry

Furnace

(N2

ambient，防止氧化層生成)

-

Anneal30

min

@

800?C

orRTA(快速熱退火)

10

sec

@

1000?C-

Drive-in4-6

hours

@

1000

?C

-

1100

?CThermal

Anneal

and

Diffusion?

NandPDrive-in(擴(kuò)散推進(jìn))-

Thermal

diffusion

of

dopant

toshallower

than

desired

depth--

Drive-in

is

a

cumulativeprocess!11?ThermalAnneal(熱退火)?D?

Photolithography

-

Mask

#4

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

B+

ion

bombardment-

50-75keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration?

Strip

PhotoresistThreshold

Adjustment,

P-type

NMOS?

Ion

Implantation2.4柵電極的制備開啟電壓調(diào)整12調(diào)整之前P阱的摻雜濃度調(diào)整時的注入劑量?Photolithography-B+ionThreshold

Adjustment,

N-type

PMOS?

Photolithography

-

Mask

#5

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

As+

ion

bombardment-

75-100keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration?

Strip

Photoresist?

Ion

Implantation13ThresholdAdjustment,N-typeP?

Remove

existing

gate

regionoxide?

Furnace

Steps -

Thermal

Anneal-

Oxide

growth

3-5

nm--O2

ambient--0.5-1hour@800°CGate

Oxide

Growth柵極氧化層生長-HF

etch，具有良好的選擇性--Dry

Furnace

(N2

ambient)--30

min

@

800?C14?Removeexistinggateregio?LPCVD

Deposition

of

Si-

Silane硅烷?

Amorphous

or

polycrystalline

silicon

layer

results

Ion

Implantation -

P+

or

As+

(N+)

implant

dopes

the

poly(typically

5

×

1015

cm-2)

Polysilicon

Gate

Deposition?

0.3-0.5

umSiO2多晶硅薄膜15熱分解?LPCVDDepositionofSi??

Photolithography

-

Mask

#6

pattern

alignmentand

UV

exposure?

Plasma

Etch

-

Anisotropic

etch各向異性蝕刻

--

Vertical

etch

rate

high

--

Lateral

etch

rate

lowGate

Patterning（柵極的圖形化）-

Rinse

away

non-pattern

PR?

Clorine(氯)or

Bromine(溴)

based

forSiO2

selectivity16?Photolithography?Plasma目標(biāo)：NMOS器件中的N-注入?yún)^(qū)PMOS器件中的P-注入?yún)^(qū)多晶硅柵的兩側(cè)形成側(cè)壁隔離層的薄氧化層2.5前端或延伸區(qū)(LDD)的形成17目標(biāo)：NMOS器件中的N-注入?yún)^(qū)PMOS器件中的P-注入?yún)^(qū)多LDD:?

Lightly

Doped

Drain(輕摻雜漏)?

Reduce

short

channel

effects

due

to

gate

voltagemagnitudes

and

electric

fields?

Source

and

Drain

must

be

layered

asNMOS:N+N-P

or

PMOS:

P+P-NExtension

(LDD)

Formation

NMOS?

Photolithography

-

Mask

#7

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-P+

ion

bombardment-

50keV

for

5

×

1013cm-2?

Strip

Photoresist?

Ion

Implantation18LDD:?LightlyDopedDrain(輕?

Photolithography

?

Mask

#8

pattern

alignment

and

UV

exposure

?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

B+

ion

bombardment

?

50keV

for

5

×

1013cm-2?

Strip

PhotoresistExtension

(LDD)

Formation

PMOS19?Photolithography andUVeSiO2

隔離介質(zhì)層CVDorLPCVDDepositionofSiO2?SilaneandOxygenOr0.5um?Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition20SiO2隔離介質(zhì)層CVDorLPCVDDeposi?

Photolithography

?

Mask

#6

oversized

pattern

alignment

and

UV

exposure

?

Rinse

away

non-pattern

PR?

Vertical

etch

rate

high?

Lateral

etch

rate

low?

Strip

PhotoresistAnisotropic

Spacer

Etch?

Plasma

Etch

?

Anisotropic

etch?

Flourine

based21?Photolithography ?Mask?

Screen

Oxide

Growth?

Thin

SiO2

layer

~10

nm

toscatter

the

implanted

ions?

Photolithography?

Mask

#9

pattern

alignment

and

UV

exposure?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

As+

ion

bombardment

?

75

keV

for

2-4

×

1015cm-2?

Strip

PhotoresistNMOS

Source

and

Drain

Implant2.6源漏區(qū)的形成Arsenic?

Reduce

channeling22?ScreenOxideGrowth?Pho?

Photolithography?

Mask

#10

pattern

alignment

and

UV

exposure?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

B+

ion

bombardment

?

5-10

keV

for

1-3

×1015cm-2

?

Strip

PhotoresistPMOS

Source

and

Drain

Implant23?Photolithography?Mask#?

N+

and

P+

Drive-in?

Thermal

diffusion

of

dopant

toshallower

than

desired

depth

?Drive-in

is

a

cumulativeprocess!?

Dry

Furnace

(N2

ambient)

?

Anneal30

min

@

900?C

orRTA

60

sec

@

1000

?C

-

1050

?CTransient

Enhanced

Diffusion

(TED瞬態(tài)增強(qiáng)擴(kuò)散)

?

Higher

than

normal

diffusivity

due

tocrystal

damageThermal

Annealing?ThermalAnneal?Repaircrystallatticestructuredamageduetoimplantation24?N+andP+Drive-in?Therma2.7接觸與局部互聯(lián)的形成

Contacts

and

Interconnects?Titaniumsputteringlocalcontacts?ConformalCoatwithSiO2?Planarization?TungstenPlugvias?AluminumMetalDeposition?Repeat–Coat–Planarize–Plug–Metaldeposition252.7接觸與局部互聯(lián)的形成 ?Titaniumspu?

HF

etch

to

remove

thin

SiO2

?

Remove

screen

oxide

fromdrain,

source

and

ploy

gateregions

?

Dip(浸)

for

a

few

secondswithHFContact

OpeningsLDDandSidewallstructure?NMOS:LateralN+N-PN-N+?PMOS:LateralP+P-NP-P+26?HFetchtoremovethinSiO

Titanium

Deposition?

Ti

is

deposited

bysputtering(typically

100

nm).

?

Ti

target

hit

withAr+

ions

in

avacuum

chamber?

The

Ti

is

reacted

in

anN2

ambient?

Forms

TiSi2

and

TiN(typically

1

min

@

600

-700

?C).?

TiSi2

has

excellentcontact

characteristics(良好的導(dǎo)體)?

TiN

does

not,

but

canbe

used

for

local

wiring(導(dǎo)電材料，短程互連布線)TiSi2TiN27 ?Tiisdepositedbysputter?Photolithography?Mask#11patternalignmentand

UV

exposure?

Rinse

away

non-pattern

PR?

TiN

etch

?

NH4OH:H2O2:H2O(1:1:5)?

Strip

PhotoresistLocal

TiN

InterconnectThermalTreatinAr減小電阻

?1min@800°C28用TiN作為局部互連引線?Photolithography?TiNetc?

Conformal

layer

ofSiO2

is

deposited

byCVD

or

LPCVD(typically

1

μm)?PSG(磷硅玻璃)

or

BPSG(硼磷硅玻璃)?磷：Surface

passivation(表面鈍化)?硼：Glass

reflow

forpartialplanarization(加熱，令表面平整)?

Chemical

MechanicalPolishing

(CMP化學(xué)機(jī)械拋光)?Planarize

the

wafersurface平坦化

?Polish

with

high

pHsilicaslurry(硅酸鹽研磨漿料)Conformal

Coat

and

Planarize2.8多層金屬互連的形成SiO229

表面不平坦帶來很多問題,兩種解決方法：?ConformallayerofSiO2isd?

Photolithography?

Mask

#12

pattern

alignmentand

UV

exposure?

Rinse

away

non-pattern

PR?

SiO2

plasma

etch

?

Anisotropic

etch?

Strip

PhotoresistVias

to

1st

Metal30?

選擇第一層金屬布線需要與下層器件結(jié)構(gòu)形成連接的接觸孔位置?

接觸孔形成?Photolithography?Rinsea

Via

Deposition

–

Tungsten

Plugs(插頭)?

TiN

or

Ti/TiN

barrier

layer粘結(jié)層/阻擋層，增強(qiáng)金屬與SiO2的粘附性?

Sputtering

or

CVD(few

tens

of

nm)?

CVD

Tungsten

(W)?Chemical

MechanicalPolishing

(CMP)?

Planarize

the

wafersurface?

Polish

with

high

pHsilica

slurry31 ?TiNorTi/TiNbarrierlay?

Etch

Contact

Holes(接觸孔的蝕刻)or

Line

Trenches(溝道)

?

Fill

etched

regions(蝕刻區(qū)的填充)

?

Planarize(平坦化)

–

CMP

process

–

Also

removes

material

that

“overflowed

holes

or

trenches”Damascene

Process大馬士革鑲嵌工藝32大馬士革鑲嵌工藝包括：?EtchContactHoles(接觸孔的蝕刻

?

Strip

PhotoresistMetal

#1

Deposition第一層金屬布線Photolithography?Mask#13patternalignmentandUVexposure?Rinseawaynon-patternPR?Anisotropicplasmaetch33SiO2Al光刻膠?SputteredAluminum?AlwithsmallamountsofSiandCu-Cureduceselectromigration避免電遷移現(xiàn)象帶來的斷路

-Si降低接觸電阻 Metal#1Deposition第一層金屬布線Ph

Multiple

Metal

Layers?DepositsOxideLayer?CMP?PhotolithographyMask#14?EtchVias?Depositviamaterial?CMP?DepositNextMetalLayer?PhotolithographyMask#15?FinalpassivationlayerofSi3N4isdepositedbyPECVDandpatternedwithMask#16.防止Na+、K+污染和封裝中的機(jī)械損傷?Finalannealandalloyinforminggas(10%H2inN2)

?30min@400-450°C?形成良好的歐姆接觸，降低Si/SiO2界面的電荷34SiO2WTiNSi3N4或SiO2 ?DepositsOxideLayer?FinalIntel

μprocessor

chip52MB

SRAM

chips

on

a

12”

wafer

?

Photos

of

state-of-the-art

CMOS

chips

(from

Intel

website).

?

90

nm

technology.35Intelμprocessorchip52MBSRAMSummary

of

Key

ideas?ThischapterservesasanintroductiontoCMOStechnology.?Itprovidesaperspectiveonhowindividualtechnologieslikeoxidationandionimplantationareactuallyused.?TherearemanyvariationsonCMOSprocessflowsusedinindustry.?Theprocessdescribedhereisintendedtoberepresentative,althoughitissimplifiedcomparedtomanycurrentprocessflows.Perhapsthemostimportantpointisthatwhileindividualprocessstepslikeoxidationandionimplantationareusuallystudiedasisolatedtechnologies,theiractualuseiscomplicatedbythefactthatICmanufacturingconsistsofmanysequentialsteps,eachofwhichmustintegratetogethertomakethewholeprocessflowworkinmanufacturing.36SummaryofKeyideas?Thischa作業(yè)：MEMS

器件制備最早的MEMS執(zhí)行器之一：靜電驅(qū)動的微馬達(dá)37作業(yè)：MEMS器件制備最早的MEMS執(zhí)行器之一：靜電驅(qū)動的演講完畢，謝謝觀看！演講完畢，謝謝觀看！2.1

CMOS制造工藝流程簡介

We

will

describe

a

modern

CMOS

process

flow.Process

described

here

requires

16

masksand

>

100

process

steps.39第二章CMOS制備基本流程2.1CMOS制造工藝流程簡介WewilldStagesofICFabrication40StagesofICFabrication2?

In

the

simplest

CMOS

technologies,

we

need

to

realizesimply

NMOS

and

PMOS

transistors

forcircuits

like

those

illustrated

below.CMOS

Digital

Gates反相電路或非門：同時輸入低電平時才能獲得高電平輸出41?InthesimplestCMOStechnPMOS

and

NMOSwafer

crosssection

afterfabrication2-Level

Metal

CMOS兩層互連布線的CMOS42有源器件（MOS、BJT等類似器件），必須在外加適當(dāng)?shù)钠秒妷呵闆r下，器件才能正常工作。對于MOS管，有源區(qū)分為源區(qū)和漏區(qū)，在進(jìn)行互聯(lián)之前，兩者沒有差別。PMOSandNMOS2-LevelMetalCMO????????Choosing

a

SubstrateActive

RegionN

and

P

WellGateTip

or

ExtensionSource

and

DrainContact

and

Local

InterconnectMultilevel

MetalizationProcessing

Phases43?ChoosingaSubstrateProcessin1

μmPhotoresist40

nmSiO2Choose

the

substrate(type,

orientation,resistivity,

wafer

size)?

Initial

processing: -

Wafer

cleaning -

thermal

oxidation,

H2O

(≈

40

nm,

15

min.

@

900oC) -

nitride

LPCVD(低壓化學(xué)氣相沉積)

(≈

80

nm@

800oC)?

Substrate

selection:-moderately

high

resistivity(25-50

ohm-cm)-(100)

orientation-P-

type.80

nmSi3N4Choosing

a

SubstrateSi,(100),PType,25~50Ωcm1st

Mask

Photoresist

?

spinning

and

baking@

100oC(≈

0.5

-

1.0

μm)442.2有源區(qū)的形成1μmPhotoresist40nmSiO2Choo?

Photolithography-Mask

#1

pattern

alignmentand

UV

exposure-Rinse

away

non-pattern

PR-Dry

etch

the

Nitride

layer--Plasma

etch

with

FluorineCF4

or

NF4

Plasma-Strip

Photoresist(H2SO4或O2plasma)Active

Area

Definition(主動區(qū))SiO2Si3N4Photoresist45?PhotolithographyActiveAre?

Wet

Oxide

(thick

SiO2)-

H2O

(≈

500

nm,90min.

@1000oC)?

Strip

Nitride

layer

-

Phosophoric

acid(磷酸)

orplasma

etch，選擇性問題Field

Oxide

Growth

-

LOCOS:

Local

Oxidation

ofSilicon(局部硅氧化工藝)SiO2Si3N4?

薄的SiO2層，厚的Si3N4層，避免鳥喙(bird’sbeak)的影響46?場區(qū):很厚的氧化層，位于芯片上不做晶體管、電極接觸的區(qū)域，可以起到隔離晶體管的作用。?WetOxide(thickSiO2)??

Photolithography(套刻)-

Mask

#2

pattern

alignmentand

UV

exposure?

IonImplantation離子注入

-

B+

ion

bombardmentPenetrate

thin

SiO2

and

fieldSiO2

--反型：半導(dǎo)體表面的少數(shù)載流子濃度等于體內(nèi)的多數(shù)載流子濃度時，半導(dǎo)體表面開始反型。-

150-200keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentrationP-well

Fabrication?

Strip

Photoresist-

Rinse

away

non-pattern

PR2.3N阱和P阱的形成SiO2Photoresist47?Photolithography(套刻)?I?

Ion

Implantation

-

P+

ion

bombardment-

Penetrate

thin

SiO2

and

field

SiO2-

300-400keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentration?

Strip

PhotoresistN-well

Fabrication?

Photolithography

-Mask

#3

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR48?IonImplantation-Penetr?

ThermalAnneal(熱退火)-

Repair

crystal

lattice

structuredamage

due

to

implantation?

Dry

Furnace

(N2

ambient，防止氧化層生成)

-

Anneal30

min

@

800?C

orRTA(快速熱退火)

10

sec

@

1000?C-

Drive-in4-6

hours

@

1000

?C

-

1100

?CThermal

Anneal

and

Diffusion?

NandPDrive-in(擴(kuò)散推進(jìn))-

Thermal

diffusion

of

dopant

toshallower

than

desired

depth--

Drive-in

is

a

cumulativeprocess!49?ThermalAnneal(熱退火)?D?

Photolithography

-

Mask

#4

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

B+

ion

bombardment-

50-75keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration?

Strip

PhotoresistThreshold

Adjustment,

P-type

NMOS?

Ion

Implantation2.4柵電極的制備開啟電壓調(diào)整50調(diào)整之前P阱的摻雜濃度調(diào)整時的注入劑量?Photolithography-B+ionThreshold

Adjustment,

N-type

PMOS?

Photolithography

-

Mask

#5

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-

As+

ion

bombardment-

75-100keV

for

1-5

×

1012cm-2--

Implantation

Energy

and

total

dose

adjusted

for

depth

and

concentration?

Strip

Photoresist?

Ion

Implantation51ThresholdAdjustment,N-typeP?

Remove

existing

gate

regionoxide?

Furnace

Steps -

Thermal

Anneal-

Oxide

growth

3-5

nm--O2

ambient--0.5-1hour@800°CGate

Oxide

Growth柵極氧化層生長-HF

etch，具有良好的選擇性--Dry

Furnace

(N2

ambient)--30

min

@

800?C52?Removeexistinggateregio?LPCVD

Deposition

of

Si-

Silane硅烷?

Amorphous

or

polycrystalline

silicon

layer

results

Ion

Implantation -

P+

or

As+

(N+)

implant

dopes

the

poly(typically

5

×

1015

cm-2)

Polysilicon

Gate

Deposition?

0.3-0.5

umSiO2多晶硅薄膜53熱分解?LPCVDDepositionofSi??

Photolithography

-

Mask

#6

pattern

alignmentand

UV

exposure?

Plasma

Etch

-

Anisotropic

etch各向異性蝕刻

--

Vertical

etch

rate

high

--

Lateral

etch

rate

lowGate

Patterning（柵極的圖形化）-

Rinse

away

non-pattern

PR?

Clorine(氯)or

Bromine(溴)

based

forSiO2

selectivity54?Photolithography?Plasma目標(biāo)：NMOS器件中的N-注入?yún)^(qū)PMOS器件中的P-注入?yún)^(qū)多晶硅柵的兩側(cè)形成側(cè)壁隔離層的薄氧化層2.5前端或延伸區(qū)(LDD)的形成55目標(biāo)：NMOS器件中的N-注入?yún)^(qū)PMOS器件中的P-注入?yún)^(qū)多LDD:?

Lightly

Doped

Drain(輕摻雜漏)?

Reduce

short

channel

effects

due

to

gate

voltagemagnitudes

and

electric

fields?

Source

and

Drain

must

be

layered

asNMOS:N+N-P

or

PMOS:

P+P-NExtension

(LDD)

Formation

NMOS?

Photolithography

-

Mask

#7

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-P+

ion

bombardment-

50keV

for

5

×

1013cm-2?

Strip

Photoresist?

Ion

Implantation56LDD:?LightlyDopedDrain(輕?

Photolithography

?

Mask

#8

pattern

alignment

and

UV

exposure

?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

B+

ion

bombardment

?

50keV

for

5

×

1013cm-2?

Strip

PhotoresistExtension

(LDD)

Formation

PMOS57?Photolithography andUVeSiO2

隔離介質(zhì)層CVDorLPCVDDepositionofSiO2?SilaneandOxygenOr0.5um?Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition58SiO2隔離介質(zhì)層CVDorLPCVDDeposi?

Photolithography

?

Mask

#6

oversized

pattern

alignment

and

UV

exposure

?

Rinse

away

non-pattern

PR?

Vertical

etch

rate

high?

Lateral

etch

rate

low?

Strip

PhotoresistAnisotropic

Spacer

Etch?

Plasma

Etch

?

Anisotropic

etch?

Flourine

based59?Photolithography ?Mask?

Screen

Oxide

Growth?

Thin

SiO2

layer

~10

nm

toscatter

the

implanted

ions?

Photolithography?

Mask

#9

pattern

alignment

and

UV

exposure?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

As+

ion

bombardment

?

75

keV

for

2-4

×

1015cm-2?

Strip

PhotoresistNMOS

Source

and

Drain

Implant2.6源漏區(qū)的形成Arsenic?

Reduce

channeling60?ScreenOxideGrowth?Pho?

Photolithography?

Mask

#10

pattern

alignment

and

UV

exposure?

Rinse

away

non-pattern

PR?

Ion

Implantation

?

B+

ion

bombardment

?

5-10

keV

for

1-3

×1015cm-2

?

Strip

PhotoresistPMOS

Source

and

Drain

Implant61?Photolithography?Mask#?

N+

and

P+

Drive-in?

Thermal

diffusion

of

dopant

toshallower

than

desired

depth

?Drive-in

is

a

cumulativeprocess!?

Dry

Furnace

(N2

ambient)

?

Anneal30

min

@

900?C

orRTA

60

sec

@

1000

?C

-

1050

?CTransient

Enhanced

Diffusion

(TED瞬態(tài)增強(qiáng)擴(kuò)散)

?

Higher

than

normal

diffusivity

due

tocrystal

damageThermal

Annealing?ThermalAnneal?Repaircrystallatticestructuredamageduetoimplantation62?N+andP+Drive-in?Therma2.7接觸與局部互聯(lián)的形成

Contacts

and

Interconnects?Titaniumsputteringlocalcontacts?ConformalCoatwithSiO2?Planarization?TungstenPlugvias?AluminumMetalDeposition?Repeat–Coat–Planarize–Plug–Metaldeposition632.7接觸與局部互聯(lián)的形成 ?Titaniumspu?

HF

etch

to

remove

thin

SiO2

?

Remove

screen

oxide

fromdrain,

source

and

ploy

gateregions

?

Dip(浸)

for

a

few

secondswithHFContact

OpeningsLDDandSidewallstructure?NMOS:LateralN+N-PN-N+?PMOS:LateralP+P-NP-P+64?HFetchtoremovethinSiO

Titanium

Deposition?

Ti

is

deposited

bysputtering(typically

100

nm).

?

Ti

target

hit

withAr+

ions

in

avacuum

chamber?

The

Ti

is

reacted

in

anN2

ambient?

Forms

TiSi2

and

TiN(typically

1

min

@

600

-700

?C).?

TiSi2

has

excellentcontact

characteristics(良好的導(dǎo)體)?

TiN

does

not,

but

canbe

used

for

local

wiring(導(dǎo)電材料，短程互連布線)TiSi2TiN65 ?Tiisdepositedbysputter?Photolithography?Mask#11patternalignmentand

UV

exposure?

Rinse

away

non-pattern

PR?

TiN

etch

?

NH4OH:H2O2:H2O(1:1:5)?

Strip

PhotoresistLocal

TiN

InterconnectThermalTreatinAr減小電阻

?1min@800°C66用TiN作為局部互連引線?Photolithography?TiNetc?

Conformal

layer

ofSiO2

is

deposited

byCVD

or

LPCVD(typically

1

μm)?PSG(磷硅玻璃)

or

BPSG(硼磷硅玻璃)?磷：Surface

passivation(表面鈍化)?硼：Glass

reflow

forpartialplanarization(加熱，令表面平整)?

Chemical

MechanicalPolishing

(CMP化學(xué)機(jī)械拋光)?Planarize

the

wafersurface平坦化

?Polish

with

high

pHsilicaslurry(硅酸鹽研磨漿料)Conformal

Coat

and

Planarize2.8多層金屬互連的形成SiO267

表面不平坦帶來很多問題,兩種解決方法：?ConformallayerofSiO2isd?

Photolithography?

Mask

#12

pattern

alignmentand

UV

exposure?

Rinse

away

non-pattern

PR?

SiO2

plasma

etch

?

Anisotropic

etch?

St