計(jì)算機(jī)組成與結(jié)構(gòu)體系英文課件：Chapter 8 – The Memory System - 1

ComputerOrganization&Architecture

Chapter8–TheMemorySystem-1ContentofthislectureTheMemorySystemOverviewInternalMemoryandExternalMemory2.1MemoryLocationsandAddresses8.1MemoryOperationsCharacteristicsofMemorySystems8.2SemiconductorRAMMemoriesSRAMDRAMStructureofLargerMemoryTheMemorySystemOverview(1)InternalMemoryandExternalMemoryThetypicalcomputersystemisequippedwithahierarchyofmemorysubsystems.InternalMemory(PrimaryStorage)Internaltothesystem,directlyaccessiblebytheprocessor.Example:MainMemory,Cache,ProcessorRegistersExternalMemory(SecondaryStorage)Externaltothesystem,accessiblebytheprocessorviaanI/Omodule.TheMemorySystemOverview(2)MemoryLocationsandAddressesHowthememoryisorganized?Example:

Threewaysoforganizinga96-bitmemoryTheMemorySystemOverview(3)MemoryLocationsandAddresses(ctd.)Howthememoryisorganized?(ctd.)Thememoryconsistsofmanymillionsofstoragecells,eachofwhichcanstoreabitofinformationhavingthevalue0or1.Thememoryisorganizedsothatagroupoffixedsizeofbitscanbestoredorretrievedinasingle,basicmemoryoperation.Word:Eachgroupoffixedsizeofbitsisreferredtoasaword.Wordlength:Thenumberofbitsineachwordisreferredtoaswordlength.Ittypicallyrangesfrom16to64bits.TheMemorySystemOverview(4)MemoryLocationsandAddresses(ctd.)Howthememoryisorganized?(ctd.)Thememoryofacomputercanbeschematicallyrepresentedasacollectionofwords.TheMemorySystemOverview(5)MemoryLocationsandAddresses(ctd.)AddressandAddressSpaceAddressesarenumbersthatidentifymemorylocations.Itiscustomarytousenumbersfrom0through2k–1,forsomesuitablevalueofk,astheaddressesofsuccessivelocationsinthememory.The2kaddressesconstitutetheaddressspaceofthecomputer,andthememorycanhaveupto2kaddressablelocations.TheMemorySystemOverview(6)MemoryLocationsandAddresses(ctd.)Byte-addressableMemoryThemostpracticalassignmentistohavesuccessiveaddressesrefertosuccessivebytelocationsinthememory.Big-endianAssignmentInthisassignment,thelowerbyteaddressesareusedforthemoresignificantbytes(theleftmostbytes)oftheword.Example:

Big-endianassignmentfor32-bitword-lengthbyte-addressablememory.TheMemorySystemOverview(7)MemoryLocationsandAddresses(ctd.)Little-endianAssignmentInthisassignment,thelowerbyteaddressesareusedforthelesssignificantbytes(therightmostbytes)oftheword.Example:

Little-endianassignmentTheMemorySystemOverview(8)MemoryLocationsandAddresses(ctd.)Little-endianAssignment(ctd.)Note:Inbothcases,byteaddresses0,4,8,…,aretakenastheaddressesofsuccessivewordsinthememoryandaretheaddressesusedwhenspecifyingmemoryoperationsforwords.TheMemorySystemOverview(9)MemoryOperations

TheMemorySystemOverview(10)MemoryOperations(ctd.)

TheMemorySystemOverview(11)MemoryOperations(ctd.)Read(Load)OperationTransfersacopyofthecontentsofaspecificmemorylocationtotheprocessor.Processor:LoadtheaddressoftherequiredmemorylocationintotheMARregisterandsettheR/Wlineto1.Memory:PlacethedatafromtheaddressedlocationontothedatalinesandconfirmthisactionbyassertingtheMFCsignal.Processor:UponreceiptoftheMFCsignal,theprocessorloadsthedataonthedatalinesintotheMDRregister.TheMemorySystemOverview(12)MemoryOperations(ctd.)Write(Store)OperationTransferanitemofinformationfromtheprocessortoaspecificlocation,destroyingtheformercontentsofthatlocation.Processor:LoadtheaddressofthespecificlocationintoMARandloadthedataintoMDRregister.ItalsosettheR/Wlineto0.Memory:Whenthedatahavebeenwritten,itresponsesprocessorwithMFCsignal.TheMemorySystemOverview(13)CharacteristicsofMemorySystemsCapacityWordsize:#ofbitsinnaturalunitoforganizationUsuallyrelatedtolengthofaninstructionorthenumberofbitsusedtorepresentanintegernumberInternalmemory:usuallyexpressedintermsofnumbersofbytesorwords.Externalmemory:usuallyexpressedintermsofnumbersofbytes.UnitofTransferNumberofbitsreadfrom,orwrittenintomemoryatatime.Internalmemory:usuallyequaltothenumberofdatalinesintoandoutofthememorymodule.Itisoftenequaltothenumberofthewordlength,butitmaynotbe.Externalmemory:dataareoftentransferredinmuchlargerunitsthanaword,andthesearereferredtoasblocks.TheMemorySystemOverview(14)CharacteristicsofMemorySystems(ctd.)AccessModeSequentialAccessMemoryisorganizedintounitsofdata,calledrecords.Accessmustbemadeinaspecificlinearsequence.Thetimetoaccessanarbitraryrecordishighlyvariable.Example:MagneticTapelocationofintereststartreadtoherefirstlocationTheMemorySystemOverview(15)CharacteristicsofMemorySystems(ctd.)AccessMode(ctd.)RandomAccessAnymemorylocationcanbeselectedatrandomanddirectlyaddressedandaccessed.Thetimetoaccessagivenlocationisindependentofthelocation’saddressandisconstant.Example:

RAM...readhereTheMemorySystemOverview(16)CharacteristicsofMemorySystems(ctd.)ModeofAccessing(ctd.)DirectAccessIndividualblocksorrecordshaveauniqueaddressbasedonphysicallocation.Accessisaccomplishedbydirectaccesstoreachageneralvicinityplussequentialsearching,countingorwaitingtoreachthefinallocation.Accesstimeisvariable.Example:

MagneticDiskblocki...jumptoherereadtohereTheMemorySystemOverview(17)CharacteristicsofMemorySystems(ctd.)AddressableUnitSmallestlocationwhichcanbeuniquelyaddressedInternalmemory:wordorbyteExternalmemory:devicedependente.g.adisk“cluster”TheMemorySystemOverview(18)CharacteristicsofMemorySystems(ctd.)Performance(Speed)AccessTimeTimebetweenpresentingtheaddressandgettingthevaliddata(memoryorotherstorage)

Random-accessmemory:Thetimeittakestoperformareadorwriteoperation.Non-random-accessmemory:Thetimeittakestopositiontheread-writemechanismatthedesiredlocation.TheMemorySystemOverview(19)CharacteristicsofMemorySystems(ctd.)Performance(Speed)(ctd.)MemoryCycleTime(forrandomaccessmemory)Timefromamemoryaccesstothenextmemoryaccess

Itconsistsoftheaccesstimeplusanyadditionaltimerequiredbeforeasecondaccesscancommence.MemoryCycleTime=AccessTime+RecoveryTimeAccesstimeandmemorycycletimeareallmeasuresofthespeedofmemoryunits.TheMemorySystemOverview(20)CharacteristicsofMemorySystems(ctd.)PhysicalTypesSemiconductorExample:

MainMemoryMagneticSurfaceExample:

MagneticdiskandMagnetictapeOpticalExample:CD,CD-R,CD-RW,DVD,Blu-RayPhysicalCharacteristicVolatile/NonvolatileVolatile:Informationdecaysnaturallyorislostwhenelectricalpowerisswitchedoff.Nonvolatile:Informationoncerecordedremainswithoutdeteriorationuntildeliberatelychanged.Noelectricalpowerisneededtoretaininformation.TheMemorySystemOverview(21)CharacteristicsofMemorySystems(ctd.)PhysicalCharacteristic(ctd.)Volatile/Nonvolatile(ctd.)Example:Magneticsurfacememoriesarenonvolatile.Semiconductormemorymaybeeithervolatileornonvolatile.Erasable/Non-erasableErasable:Thecontentsofthememorycanbealtered.Non-erasable:Thecontentsofthememorycannotbealtered,exceptbydestroyingthestorageunit.SemiconductorRAMMemories(1)SemiconductorRAMMemory

Themostcommontypeofsemiconductormemoryisreferredtoasrandom-accessmemory(RAM).CharacteristicItispossiblebothtoreaddatafromthememoryandtowritenewdataintothememoryeasilyandrapidlyItisvolatile.Accesstimeisofjustafewnanoseconds(seconds).SemiconductorRAMMemories(2)MainMemoryStorageTechnologyDynamicRAM(DRAM)Madewithcellsthatstoredataaschargeoncapacitors.HighestdensitiesOptimizedforcost/bit->mainmemoryStaticRAM(SRAM)Binaryvaluesarestoredusingtraditionalflip-floplogic-gateconfigurations.Densities?to1/8ofDRAMSpeeds8-16xfasterthanDRAMCost8-16xmoreperbitOptimizedforspeed->cachesNoteBothstaticRAMsanddynamicRAMsarevolatile.SemiconductorRAMMemories(3)StaticRAM(SRAM)ImplementationofaSRAMCellYXWordlineBitlinesFigure8.4.AstaticRAMcell.bT2T1b￠SemiconductorRAMMemories(4)StaticRAM(SRAM)(ctd.)ImplementationofaSRAMCell(ctd.)Assumethatthecellisinstate1ifthelogicvalueatpointXis1andatpointYis0.ReadOperationThewordlineisathighlevel.Read“1”:Thesignalonthebitlinebishighandthesignalonthebitlineb’islow.Read“0”:Thesignalonthebitlinebislowandthesignalonthebitlineb’ishigh.Note:Sense/writecircuitsattheendofthebitlinesmonitorthestateofbandb’andsettheoutputaccordingly.SemiconductorRAMMemories(5)StaticRAM(SRAM)(ctd.)ImplementationofaSRAMCell(ctd.)WriteOperationThewordlineisathighlevel.Write“1”:Placehighlevelsignalonbitlinebandplacelowlevelsignalonbitlineb’.Write“0”:Placehighlevelsignalonbitlinebandplacelowlevelsignalonbitlineb’.Note:TherequiredsignalsonthebitlinesaregeneratedbytheSense/Writecircuit.MaintainStateThewordlineisatgroundlevel.SemiconductorRAMMemories(6)StaticRAM(SRAM)(ctd.)CMOSRealizationofaSRAMCellMOSICNMOSPMOSCMOS:ComplementaryMetal-OxideSemiconductor(互補(bǔ)金屬氧化物半導(dǎo)體)SemiconductorRAMMemories(7)StaticRAM(SRAM)(ctd.)CMOSRealizationofaSRAMCell(ctd.)Note:Ifpowerisinterruptedandthenitisrestored,thelatchwillsettleintoastablestate,butitwillnotnecessarilybethesamestatethecellwasinbeforetheinterruption.Thepowersupplyvoltageis5VinolderCMOSSRAMsor3.3Vinnewlow-voltageversions.CMOSSRAMs’powerconsumptionisverylow.AdvantageandDisadvantageofStaticRAMFastLowdensityHighcostSemiconductorRAMMemories(8)InternalOrganizationofStaticRAMChips

Organizationof128BitCells(16×8)FFFigure8.2.

Organizationofbitcellsinamemorychip.circuitSense/WriteAddressdecoderFFCScellsMemorycircuitSense/WriteSense/WritecircuitDatainput/outputlines:A0A1A2A3W0W1W15b7b1b0WR/b￠7b￠1b￠0b7b1b0???????????????????????????SemiconductorRAMMemories(9)InternalOrganizationofStaticRAMChips(ctd.)Organizationof128BitCells(ctd.)InternalOrganizationWordline:drivenbytheaddressdecoder.BitlinesSense/WritecircuitsExternalConnectionsAddresslines(Input):A0–A3Datalines(Input/Output):b0–b7Controllines(Input)R/W(Read/Write):SpecifytherequiredReadorWriteoperation.CS(ChipSelect):Selectagivenchipinamulti-chipmemorysystem.SemiconductorRAMMemories(10)InternalOrganizationofStaticRAMChips(ctd.)Organizationof128BitCells(ctd.)ExternalConnections(ctd.)PowerSupplylineGroundlineTotalConnections=4+8+2+1+1=16SemiconductorRAMMemories(11)InternalOrganizationofStaticRAMChips(ctd.)Organizationof1024(1K)BitCells

128×8OrganizationExternalConnectionsAddresslines(Input):A0–A6Datalines(Input/Output):b0–b7Controllines(Input):R/W,CSPowersupplylineGroundlineTotalConnections=7+8+2+1+1=19SemiconductorRAMMemories(12)InternalOrganizationofStaticRAMChips(ctd.)

Organizationof1024(1K)BitCells

(ctd.)1K×1OrganizationCSSense/Writecircuitryarraymemorycelladdress5-bitrowinput/outputData5-bitdecoderaddress5-bitcolumnaddress10-bitoutputmultiplexer32-to-1inputdemultiplexer3232′WR/W0W1W31andSemiconductorRAMMemories(13)InternalOrganizationofStaticRAMChips(ctd.)Organizationof1024(1K)BitCells

(ctd.)1K×1Organization(ctd.)ExternalConnectionsAddresslines(Input):A0–A9Datalines(Input/Output):b0Controllines(Input):R/W,CSPowersupplylineGroundlineTotalConnections=10+1+2+1+1=15LargechipshaveessentiallythesameorganizationasFigure5.3butusealargermemorycellarrayandhavemoreexternalconnections.SemiconductorRAMMemories(14)DynamicRAMExampleofaDRAMcellTCWordlineBitlineGroundSemiconductorRAMMemories(15)DynamicRAM(ctd.)ExampleofaDRAMcell(ctd.)ReadOperationPre-chargebitlinetoVcc/2.TakethewordlineHIGH.Detectwhethercurrentflowsintooroutofthecell.Note:cellcontentsaredestroyedbytheread!Mustwritethebitvaluebackafterreading.SemiconductorRAMMemories(16)DynamicRAM(ctd.)ExampleofaDRAMcell(ctd.)WriteOperationTakethewordlineHIGH.SetthebitlineLOWorHIGHtostore0or1.TakethewordlineLOW.Note:Thestoredchargefora1willeventuallyleakoff.MaintainStateThewordlineislow.DisadvantagesLongermemoryaccesstimeLeaky,needstoberefreshedCannotbeeasilyintegratedwithCMOSSemiconductorRAMMemories(17)DynamicRAM(ctd.)InternalOrganizationofanAsynchronousDRAMChipExampleSemiconductorRAMMemories(18)DynamicRAM(ctd.)InternalOrganizationofanAsynchronousDRAMChip(ctd.)Example(ctd.)14bitaddressbitsareneededtoselectarow.Another11bitsareneededtospecifyagroupof8bitsintheselectedrow.Total:25-bitaddressToreducethenumberofpinsneededforexternalconnections,therowandcolumnaddressesaremultiplexedon14pins.RowAddressStrobe(RAS)ColumnAddressStrobe(CAS)SemiconductorRAMMemories(19)DynamicRAM(ctd.)DRAMRefreshLeakystoragePeriodicrefreshacrossDRAMrowsUn-accessiblewhenrefreshingRead,andwritethesamedatabackExample:4KrowsinaDRAM,100nsreadcycle,Decayin64ms4096*100ns=410μstorefreshonce410μs/64ms=0.64%unavailabilitySemiconductorRAMMemories(20)AsynchronousDRAMThememoryisnotsynchronizedtothesystemclock.Amemoryaccessisbegun,andacertainperiodoftimelaterthememoryvalueappearsonthebus.Thesignalsarenotcoordinatedwiththesystemclockatall.Thetimingofthememoryiscontrolledasynchronously.Normal:RespondstoRASandCASsignals(noclock)Aspecializedmemorycontrollercircuitprovidesthenecessarycontrolsignals,RASandCASthatgovernthetiming.SemiconductorRAMMemories(21)AsynchronousDRAMQuestion:HowtoaccesstheotherbytesinthesamerowofaDRAMchip?FastPageMode(FPM)RowremainsopenafterRASformultipleCAScommandsItallowstransferringablockofdataatamuchfasterratethancanbeachievedfortransfersinvolvingrandomaddresses.SemiconductorRAMMemories(22)EnhancedDRAMsObsoleteTechnologiesFastpagemodeDRAM(FPMDRAM):Allowedre-useofrow-addressesExtendeddataoutDRAM(EDODRAM):EnhancedFPMDRAMwithmorecloselyspacedCASsignals.VideoRAM(VRAM):DualportedFPMDRAMwithasecond,concurrent,serialinterfaceExtrafunctionalityDRAMS(CDRAM,GDRAM):AddedSRAM(CDRAM)andsupportforgraphicsoperations(GDRAM)SemiconductorRAMMemories(23)EnhancedDRAMs(ctd.)DRAMCoreswithbetterinterfacelogicandfasterI/OSynchronousDRAM(SDRAM):UsesaconventionalclocksignalinsteadofasynchronouscontrolDoubleDataRateSynchronousDRAM(DDRSDRAM):DoubleedgeclockingsendstwobitspercycleperpinRambus?DRAM(RDRAM):Usesfastersignallingoverfewerwires(sourcedirectedclocking)withatransactionorientedinterfaceprotocolSemiconductorRAMMemories(24)SynchronousDRAMs(SDRAMs)Theiroperationisdirectlysynchronizedwithaclocksignal.StructureofaSDRAMChip

R/WRASCASCSClockCellarraylatchaddressRowdecoderRowdecoderColumnRead/Writecircuits&latchescounteraddressColumnRow/ColumnaddressDatainputregisterDataoutputregisterDataRefreshcounterModeregisterandtimingcontrolSemiconductorRAMMemories(25)SynchronousDRAMs(SDRAMs)(ctd.)StructureofaSDRAMChip(ctd.)Ifanaccessismadeforrefreshingpurposeonly,itwillmerelyrefreshthecontentsofthecells,notchangingthecontentsofthelatches.ItisnotnecessarytoprovideexternallygeneratedpulsesontheCASlinetoselectsuccessivecolumns.Thenecessarycontrolsignalsareprovidedinternallyusingacolumncounterandtheclocksignal.SDRAMshavebuilt-inrefreshcircuitry.Arefreshcounterisapartofbuilt-inrefreshcircuitry.SemiconductorRAMMemories(26)SynchronousDRAMs(SDRAMs)(ctd.)BurstOperationExample:

Burstreadoflength4inanSDRAMR/WRASCASClockRowColD0D1D2D3AddressDataSemiconductorRAMMemories(27)SynchronousDRAMs(SDRAMs)(ctd.)SpeedofSDRAMThespeedofSDRAMisratedinMHzratherthaninnanoseconds(ns).AdvantageThismakesiteasiertocomparethebusspeedandtheSDRAMchipspeed.ExampleIntelhasdefinedPC100andPC133busspecificationsinwhichthesystembusiscontrolledbya100or133MHzclockrespectively.Therefore,majormanufacturersofmemorychipsproduce100and133MHzSDRAMchips.

NoteConverttheSDRAMclockspeedtonanosecondsbydividingthechipspeedinto1billionns.SemiconductorRAMMemories(28)SynchronousDRAMs(SDRAMs)(ctd.)LatencyandBandwidth

LatencyandBandwidtharetwoparametersindicatingtheperformanceofamemorysystem.LatencyReferstotheamountoftimeittakestotransferawordofdatatoorfromthememory.NoteInblocktransfers,latencyisusedtodenotethetimeittakestotransferthefirstwordofdata.WhenbuyingDRAM,thelatencyratingthatyouseemostoftenisthememoryaccesstime.SemiconductorRAMMemories(29)SynchronousDRAMs(SDRAMs)(ctd.)LatencyandBandwidth(ctd.)Latency(ctd.)Example:Thefirstwordofdataistransferred5clockcycleslater.Thelatencyis5clockcycles.R/WRASCASClockFigure8.9.

Burstreadoflength4inanSDRAM.RowColD0D1D2D3AddressDataSemiconductorRAMMemories(30)SynchronousDRAMs(SDRAMs)(ctd.)LatencyandBandwidth(ctd.)BandwidthThenumberofbitsorbytesthatcanbetransferredinonesecondisreferredtoasbandwidth.Unit:bitpersecondorbytepersecondThebandwidthofamemoryunitdependsonthespeedofaccesstothestoreddataandonthenumberofbitsthatcanbeaccessedinparallel.Theeffectivebandwidthalsodependsonthetransfercapabilityofthelinksthatconnectthememoryandtheprocessor,typicallythespeedofthebus.EffectiveBandwidth=BusSpeed×BusWidthSemiconductorRAMMemories(31)SynchronousDRAMs(SDRAMs)(ctd.)DDRSDRAMDDR:doubledatarate在原有的SDRAM的架構(gòu)基礎(chǔ)上加以較小的改進(jìn)(可復(fù)用原有生產(chǎn)線)

ThelatencyofthesedevicesisthesameasforstandardSDRAMs.

Usesbothrising(positiveedge)andfalling(negative)edgeofclockfordatatransfer.(typical100MHzclockwith200MHztransfer).(bandwidth×2)(SDRAMonlycarriesinformationontherisingedgeofasignal)DDRSDRAMalsoconsumeslesspower,whichmakesitidealfornotebookcomputers.SDRAM和DDR均為開(kāi)放標(biāo)準(zhǔn)(JEDEC)Important!!SemiconductorRAMMemories(32)SynchronousDRAMs(SDRAMs)(ctd.)DDRSDRAM(ctd.)DDRTerminology(ctd.)NameClockFreq.DataRateModuleNameDDR200100MHz200MHzPC1600DDR266133MHz266MHzPC2100DDR333167MHz333MHzPC2700DDR400200MHz400MHzPC3200SemiconductorRAMMemories(33)SynchronousDRAMs(SDRAMs)(ctd.)DDR2SDRAM基于DDR技術(shù)，并在關(guān)鍵領(lǐng)域有所提升FBGApackage(更為良好的電氣性能與散熱性),1.8V4-bitprefetchbuffer,burstlength=4HigherlatencySemiconductorRAMMemories(34)SynchronousDRAMs(SDRAMs)(ctd.)DDR3SDRAMComeswithapromiseofapowerconsumptionreductionof30%,1.5V"Dual-gate"transistorstoreduceleakageofcurrent.8bitpre-fetchbuffer,burstlength=8NameClockFreq.DataRateModuleNameDDR3-800100

MHz

800MHzPC3-6400

DDR3-1066133

MHz1066MHzPC3-8500

DDR3-1333166

MHz1333MHzPC3-10600DDR3-1600200

MHz1600MHzPC3-12800SemiconductorRAMMemories(35)StructureofLargerMemoriesStaticMemorySystems由若干存儲(chǔ)器芯片組成所要求的主存。位擴(kuò)展法

芯片每個(gè)存儲(chǔ)單元的位數(shù)小于存儲(chǔ)器字長(zhǎng)，需進(jìn)行位擴(kuò)展。例：用1M×1位存儲(chǔ)芯片組成1M×8位（1MB）的RAM，每片存儲(chǔ)同一位權(quán)的一位數(shù)據(jù)（片的I/O端接Di），訪問(wèn)芯片需20位地址碼：A19~A0

：寫讀控制信號(hào)8

I/O……A0D07I/O6I/O5I/O4I/O3I/O2I/O11Mⅹ1I/O中央處理器(CPU)數(shù)據(jù)總線地址總線D7A19WESemiconductorRAMMemories(36)StructureofLargerMemories(ctd.)StaticMemorySystems(ctd.)位擴(kuò)展法(ctd.)

SemiconductorRAMMemories(37)StructureofLargerMemories(ctd.)StaticMemorySystems(ctd.)字?jǐn)U展法芯片每個(gè)存儲(chǔ)單元的位數(shù)等于存儲(chǔ)器字長(zhǎng)，但容量(字?jǐn)?shù))不夠，需進(jìn)行字?jǐn)U展。

例：用256K×8位芯片組成1MB的RAM1MB容量需20位地址碼(A19~A0)256KB芯片需18位片內(nèi)地址碼(A17~A0)用高二位地址A19A18經(jīng)2:4譯碼器（74139）選擇芯片讀/寫

每片8條I/O線分別接D7~D0

256Kⅹ8

256Kⅹ8256Kⅹ8256Kⅹ82:4譯碼器A19A18A0A17D0~D7CPU01231234CECECECESemiconductorRAMMemories(38)StructureofLargerMemories(ctd.)StaticMemorySystems(ctd.)字?jǐn)U展法(ctd.)SemiconductorRAMMemories(39)StructureofLargerMemories(ctd.)StaticMemorySystems(ctd.)字位同時(shí)擴(kuò)展法

單片芯片的字?jǐn)?shù)和位數(shù)均小于主存的容量要求，需進(jìn)行字、位的擴(kuò)展。

Example:

Using512K×8staticmemorychipstoimplementamemoryof2M×32.Totalchips==16FigureseenextpageConclusionAssumethatthecapacityofamemoryunitisM×Nbit,ifconstitutedofusingl×kbitchips,thenumberoftotalchipsneededis(M/l)×(N/k).SemiconductorRAMMemories(40)StructureofLargerMemories(ctd.)StaticMemorySystems(ctd.)例：（補(bǔ)充）

CPU的地址總線16根（A15~A0，A0為低位），雙向數(shù)據(jù)總線8根（D7~D0），控制總線中與主存有關(guān)的信號(hào)有（允許訪存，低電平有效），（高電平為讀命令，低電平為寫命令）。主存地址空間分配如下：0000H—3FFFH為系統(tǒng)程序區(qū)，由只讀存儲(chǔ)芯片組成；4000H－4FFFH為系統(tǒng)程序工作區(qū)，由SRAM組