課程設(shè)計(jì)報(bào)告-四人搶答器

PAGE/課程設(shè)計(jì)報(bào)告課程設(shè)計(jì)報(bào)告設(shè)計(jì)題目四人搶答器專專業(yè)******班級(jí)******姓名******學(xué)號(hào)******指導(dǎo)教師******提交日期******摘要在許多比賽活動(dòng)中,為了準(zhǔn)確、公正、直觀地判斷出第一搶答者,通常設(shè)置一臺(tái)搶答器。通過(guò)搶答器的數(shù)顯,燈光和音響等手段指示出第一搶答者。同時(shí)還可以設(shè)置定時(shí)、記分犯規(guī)及獎(jiǎng)懲等多種功能。本設(shè)計(jì)采用手動(dòng)搶答的方式,有人搶答后,系統(tǒng)自動(dòng)封鎖其他人的搶答按鈕,使其不能再搶答,從而實(shí)現(xiàn)搶答功能。數(shù)字搶答器由主體電路與擴(kuò)展電路組成。優(yōu)先編碼電路、鎖存器、譯碼電路將參賽隊(duì)的輸入信號(hào)在顯示器上輸出；用控制電路和主持人開(kāi)關(guān)啟動(dòng)報(bào)警電路,以上兩部分組成主體電路。通過(guò)定時(shí)電路和譯碼電路將秒脈沖產(chǎn)生的信號(hào)在顯示器上輸出實(shí)現(xiàn)計(jì)時(shí)功能,構(gòu)成擴(kuò)展電路。經(jīng)過(guò)模擬仿真,下載到開(kāi)發(fā)板等工作后數(shù)字搶答器成型。關(guān)鍵字搶答電路定時(shí)電路報(bào)警電路時(shí)序控制目錄摘要··········································································································1第1章概述·························································································3第2章課程設(shè)計(jì)任務(wù)及要求····························································42.1設(shè)計(jì)任務(wù)···············································································42.2設(shè)計(jì)要求···············································································4第3章系統(tǒng)設(shè)計(jì)··············································································53.1設(shè)計(jì)方案················································································53.2系統(tǒng)設(shè)計(jì)·················································································5結(jié)構(gòu)框圖及說(shuō)明·························································5系統(tǒng)原理圖及工作原理·············································63.3單元電路設(shè)計(jì)············································································7第4章軟件仿真·················································································124.1仿真電路圖··············································································124.2仿真過(guò)程··················································································124.3仿真結(jié)果··················································································14第5章安裝調(diào)試·················································································145.1安裝調(diào)試過(guò)程··········································································145.2故障分析··················································································15第6章心得體會(huì)··················································································16附錄使用元件清單··············································································18參考文獻(xiàn)·························································································18第1章概述隨著社會(huì)的不斷發(fā)展,人們的生活水平也在不斷的提高人們不斷要滿足物質(zhì)上的要求,同時(shí)對(duì)精神上的追求也在不斷的提高,現(xiàn)在的社會(huì)是一個(gè)娛樂(lè)的社會(huì)?，F(xiàn)在各電視臺(tái)的活動(dòng)和課外活動(dòng)都很多。人們?cè)趨⒓踊顒?dòng)的時(shí)候都對(duì)審判有很多的意見(jiàn),所以為了比賽的準(zhǔn)確和公正,就需要有儀器的輔佐。智力競(jìng)賽搶答器就是一種活潑的有趣的供人們娛樂(lè)的游戲裝置,通過(guò)搶答方式不僅能引起參賽者和觀眾的興趣,而且能夠提高參賽者的敏捷性,同時(shí)我們?cè)趨⑴c中能夠增加一些生活常識(shí)和科學(xué)知識(shí),因此,在許多比賽活動(dòng)中為了準(zhǔn)確,公正的進(jìn)行每一場(chǎng)比賽,特別設(shè)置了一臺(tái)具有顯示第一搶答者并鎖定、犯規(guī)警告等多種功能的搶答器,該設(shè)計(jì)針對(duì)各種要求設(shè)計(jì)出可供八名選手參賽使用的數(shù)字式競(jìng)賽搶答器,適用于各大中小電視臺(tái),學(xué)校等單位舉行的智力競(jìng)賽。數(shù)字電路組成的數(shù)字系統(tǒng)工作可靠,精度較高,抗干擾能力很強(qiáng),所以智力競(jìng)賽搶答器的設(shè)計(jì)就有數(shù)字電路來(lái)控制。第2章課程設(shè)計(jì)任務(wù)及要求2.1設(shè)計(jì)任務(wù)設(shè)計(jì)一個(gè)四位智力競(jìng)賽搶答器。準(zhǔn)確地理解有關(guān)要求,獨(dú)立完成系統(tǒng)設(shè)計(jì),要求所設(shè)計(jì)的電路具有以下功能：〔1設(shè)計(jì)4組參賽的搶答器,每組設(shè)置一個(gè)搶答按鈕。

〔2給節(jié)目主持人設(shè)置一個(gè)控制開(kāi)關(guān)S,這個(gè)開(kāi)關(guān)由主持人控制,進(jìn)行清零和搶答使能?！?搶答器具有鎖存與顯示功能。即選手按動(dòng)按鈕,鎖存相應(yīng)的編號(hào),并在LED數(shù)碼管上顯示?！?搶答器具有搶答計(jì)時(shí)功能,且一次搶答的時(shí)間由主持人設(shè)定〔如30秒。2.2設(shè)計(jì)要求1.分析設(shè)計(jì)任務(wù),擬定多種設(shè)計(jì)方案,根據(jù)當(dāng)時(shí)的制作條件,選定其中的一種方案繪制設(shè)計(jì)系統(tǒng)框圖和設(shè)計(jì)流程。2.設(shè)計(jì)各部分單元電路圖〔或VHDL描述。計(jì)算參數(shù),選定元器件型號(hào)、確定數(shù)量,提出元件清單。3.安裝、調(diào)試硬件電路,或制作以FPGA/CPLD為基礎(chǔ)的專用集成電路芯片ASIC。4.電路測(cè)試、分析所要求的各項(xiàng)功能和指標(biāo),或?qū)HDL描述的電路作功能仿真和時(shí)序仿真,對(duì)ASIC芯片作脫機(jī)運(yùn)行。5.運(yùn)行制作的硬件電路,操作各項(xiàng)設(shè)計(jì)功能是否正常穩(wěn)定,交驗(yàn)并演示所設(shè)計(jì)制作的電路裝置6總結(jié)設(shè)計(jì)中各主要環(huán)節(jié)的資料,整理打印出規(guī)范的設(shè)計(jì)報(bào)告。第3章系統(tǒng)設(shè)計(jì)3.1設(shè)計(jì)方案該電路由搶答模塊,鎖存模塊,定時(shí)模塊,報(bào)警模塊組成。搶答模塊：由5個(gè)按鈕組成,包括4個(gè)選手按鈕和1個(gè)主持人按鈕。當(dāng)主持人按鈕為低電平時(shí),進(jìn)行電路清零；為高電平時(shí),選手開(kāi)始搶答。當(dāng)?shù)谝粋€(gè)選手搶到題后,發(fā)光二極管亮,顯示其編號(hào),并且揚(yáng)聲器響。鎖存模塊：當(dāng)?shù)谝粋€(gè)選手搶到題后,若再有選手按按鈕,不再識(shí)別其搶答信號(hào)。定時(shí)模塊：主持人發(fā)出搶答信號(hào)后,電路進(jìn)行自動(dòng)計(jì)時(shí),規(guī)定選手搶答在一定時(shí)間內(nèi)完成。報(bào)警模塊：與定時(shí)模塊共同作用,如給定時(shí)間內(nèi)無(wú)人搶答,揚(yáng)聲器響應(yīng)報(bào)警,該題作廢,進(jìn)行下一題搶答。3.2系統(tǒng)設(shè)計(jì)結(jié)構(gòu)框圖及說(shuō)明分析各項(xiàng)設(shè)計(jì)要求后,可繪制如下系統(tǒng)原理框圖結(jié)構(gòu)圖說(shuō)明第一信號(hào)鑒別電路是搶答器的關(guān)鍵電路,其任務(wù)是鑒別并鎖存第一搶答者的信號(hào),這類電路可以選用各種觸發(fā)器、鎖存器構(gòu)成,也可用VHDL語(yǔ)言語(yǔ)言自己編寫(xiě)。其他模塊的功能如前面所述,這里不再重復(fù)。系統(tǒng)原理圖及工作原理工作原理：主持人按鈕〔Q0撥向低電平,U1,U2的清零端CLR為低電平,實(shí)現(xiàn)電路清零,當(dāng)主持人按鈕撥向高電平,CLR高電平無(wú)效,此刻搶答開(kāi)始,由于Q1~Q4原始狀態(tài)為高電平,使得四輸入與門(mén)輸出為高電平,cp=‘1’,不能觸發(fā)。當(dāng)?shù)谝粋€(gè)人按下?lián)尨鸢粹o,輸入低電平,四輸入與門(mén)電平值由‘1’跳變?yōu)椤?’,此刻cp=‘0’,觸發(fā)U1,使得U1輸出端q=‘1’,此后無(wú)論其他選手再按按鈕,cp=‘0’不變,實(shí)現(xiàn)對(duì)其他選手的鎖存功能,U1輸出q也一直保持為1,所以對(duì)于U2器件,只有一個(gè)脈沖觸發(fā),其輸出q1~q4僅為s0~s1的第一個(gè)狀態(tài),在經(jīng)U3器件進(jìn)行轉(zhuǎn)換后,由發(fā)光二極管輸出〔點(diǎn)亮第一個(gè)搶答選手對(duì)應(yīng)的發(fā)光二極管。而答題計(jì)時(shí)部分,由U2的輸出端alm=‘1’使能U4,進(jìn)行計(jì)時(shí),計(jì)時(shí)輸出由發(fā)光二極管顯示。當(dāng)在規(guī)定的時(shí)間沒(méi)有答題結(jié)束,則蜂鳴器發(fā)出報(bào)警聲。單元電路設(shè)計(jì)<1>.Catch元件器件生成所使用的VHDL語(yǔ)言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycatchisPort<cp:instd_logic;clr:instd_logic;q:outstd_logic>;endcatch;architectureBehavioralofcatchisbeginprocess<cp,clr>beginifclr='0'thenq<='0';elsifcp'eventandcp='0'thenq<='1';endif;endprocess;endBehavioral;器件描述：clr：clr=‘0’,清零,且q=‘0’；clr=‘cp：cp=‘1’,q=‘0’；cp=‘0’,q=<2>.Lock元件器件生成所使用的VHDL語(yǔ)言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitylockisPort<d1:instd_logic;d2:instd_logic;d3:instd_logic;d4:instd_logic;clk:instd_logic;clr:instd_logic;q1:outstd_logic;q2:outstd_logic;q3:outstd_logic;q4:outstd_logic;alm:outstd_logic>;endlock;architectureBehavioraloflockisbeginprocess<clk>beginifclr='0'then低電平有效q1<='0';q2<='0';q3<='0';q4<='0';alm<='0';elsifclk'eventandclk='1'thenq1<=d1;q2<=d2;q3<=d3;q4<=d4;alm<='1';endif;endprocess;endBehavioral;器件描述：clk：當(dāng)clk=‘0’時(shí),q1~q4=‘0’,alm=‘0’；當(dāng)clk=‘1’時(shí),q1<=d1;q2<=d2;q3<=d3;q4<=d4;d1~d4：d1~d4=s1~s4；<3>.ch41a元件器件生成所使用的VHDL語(yǔ)言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitych41aisPort<d1:instd_logic;d2:instd_logic;d3:instd_logic;d4:instd_logic;q:outstd_logic_vector<3downto0>>;endch41a;architectureBehavioralofch41aisbeginprocess<d1,d2,d3,d4>variabletmp:std_logic_vector<3downto0>;begintmp:=d1&d2&d3&d4;casetmpiswhen"0111"=>q<="0001";when"1011"=>q<="0010";when"1101"=>q<="0010";when"1110"=>q<="0100";whenothers=>q<="1111";endcase;endprocess;endBehavioral;器件描述：該器件主要實(shí)現(xiàn)d1~d4輸入的轉(zhuǎn)換功能,也就是將最原始的搶答輸入進(jìn)行轉(zhuǎn)換,通過(guò)該器件,將原始搶答時(shí)刻s1~s4狀態(tài)輸出至發(fā)光二極管,也就最終實(shí)現(xiàn)誰(shuí)先搶答,對(duì)應(yīng)的發(fā)光二極管點(diǎn)亮。<4>.Count元件器件生成所使用的VHDL語(yǔ)言：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycountisPort<clk:instd_logic;en:instd_logic;h:outstd_logic_vector<3downto0>;l:outstd_logic_vector<3downto0>;sound:outstd_logic>;endcount;architectureBehavioralofcountisbeginprocess<clk,en>variablehh,ll:std_logic_vector<3downto0>;beginifclk'eventandclk='1'thenifen='1'thenifll=0andhh=0thensound<='1';elsifll=0thenll:="1001";hh:=hh-1;elsell:=ll-1;endif;elsesound<='0';hh:="1001";ll:="1001";endif;endif;h<=hh;l<=ll;endprocess;endBehavioral;器件描述：該器件主要是一個(gè)計(jì)時(shí)器件,計(jì)時(shí)可以由主持人自己設(shè)定,h為高位,l為地位,由alm輸入到使能端使能,開(kāi)始計(jì)時(shí),當(dāng)外部來(lái)一個(gè)時(shí)鐘脈沖,自減一,當(dāng)?shù)褂?jì)時(shí)結(jié)束時(shí),sound=‘1’,使得報(bào)警器響。第4章軟件仿真4.1仿真電路圖4.2仿真過(guò)程編譯無(wú)誤之后,將以上原理圖生成VHDL語(yǔ)言,繼而生成VHDTEST文件,將激勵(lì)信號(hào)輸入VHDTEST文件,進(jìn)行仿真。激勵(lì)信號(hào)：s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s3<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s2<='0';waitfor2ns;s1<='0';waitfor2ns;s3<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s3<='0';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s4<='0';waitfor5ns;s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';waitfor5ns;s0<='1';waitfor2ns;s4<='0';waitfor2ns;s1<='0';waitfor2ns;s2<='0';waitfor2ns;s3<='0';waitfor5ns;4.3仿真結(jié)果仿真波形如下：經(jīng)觀察檢測(cè),仿真結(jié)果符合預(yù)定要求。第5章安裝調(diào)試5.1安裝調(diào)試過(guò)程根據(jù)要求,下載原理圖設(shè)計(jì)如下經(jīng)計(jì)算,選用兩個(gè)256分頻,一個(gè)16分頻,即1M分頻,獲得所需脈沖；將count的sound引腳接蜂鳴器,實(shí)現(xiàn)報(bào)警；將Ch41a及Count的輸出通過(guò)J4B_4S接到8個(gè)LED上,其中,前4個(gè)用來(lái)顯示搶到題的選手序號(hào),后4個(gè)用來(lái)顯示時(shí)間,實(shí)現(xiàn)答題倒計(jì)時(shí)。5.2故障分析下載過(guò)程中有以下問(wèn)題〔1原理圖生成VHDL語(yǔ)言時(shí),出現(xiàn)錯(cuò)誤,經(jīng)檢查,原因主要有：部分輸出管腳為空；端口未定義屬性?！?蜂鳴器聲音刺耳經(jīng)查找資料,這是頻率選擇不合適的問(wèn)題,〔3未答題前