vhdl語言例程集錦(81)

lOctalBusTransceiverlQuad2-inputOR

vhdl

ExamplesofVHDLDescriptions

AdvancedElectronicDesignAutomation

ExamplesofVHDLDescriptions

Author:IanElliottofNorthumbriaUniversity

ThisaselectionofVHDLsourcefileswhichservetoillustratethediversityandpowerofthelanguagewhenusedtodescribevarioustypesofhardware.Theexamplesrangefromsimplecombinationallogic,describedin

termsofbasiclogicgates,tomorecomplexsystems,suchasabehaviouralmodelofamicroprocessorandassociatedmemory.AlloftheexamplescanbesimulatedusinganyIEEEcompliantVHDLsimulatorandmanycanbe

synthesisedusingcurrentsynthesistools.

Usethehierarchicallinksbelowtonavigateyourwaythroughtheexamples:lCombinationalLogic

lCounters

lShiftRegisters

lMemory

lStateMachines

lRegisters

lSystems

lADCandDAC

lArithmetic

CombinationalLogic

lExclusive-ORGate(Dataflowstyle)

lExclusive-ORGate(Behaviouralstyle)

lExclusive-ORGate(Structuralstyle)

lMiscellaneousLogicGates

lThree-inputMajorityVoter

lMagnitudeComparator

lQuad2-inputNand(74x00)

lBCDtoSevenSegmentDecoder

lDual2-to-4Decoder

l8-bitIdentityComparator

lHammingEncoder

lHammingDecoder

l2-to-4DecoderwithTestbenchandConfiguration

lMultiplexer16-to-4usingSelectedSignalAssignmentStatement

lMultiplexer16-to-4usingConditionalSignalAssignmentStatement

lMultiplexer16-to-4usingif-then-elsif-elseStatement

lM68008AddressDecoder

lHighestPriorityEncoder

lN-inputANDGate

Counters

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ExamplesofVHDLDescriptions

lCounterusingaConversionFunction

lGeneratedBinaryUpCounter

lCounterusingMultipleWaitStatements

lSynchronousDownCounterwithParallelLoad

lMod-16CounterusingJKFlip-flops

lPseudoRandomBitSequenceGenerator

lUniversalCounter/Register

ln-BitSynchronousCounter

ShiftRegisters

lUniversalShiftRegister/Counter

lTTL164ShiftRegister

lBehaviouraldescriptionofan8-bitShiftRegister

lStructuralDescriptionofan8-bitShiftRegister

Memory

lROM-basedWaveformGenerator

lAFirst-inFirst-outMemory

lBehaviouralmodelofa16-word,8-bitRandomAccessMemory

lBehaviouralmodelofa256-word,8-bitReadOnlyMemory

StateMachines

lClassic2-ProcessStateMachineandTestBench

lStateMachineusingVariable

lStateMachinewithAsynchronousReset

lPatternDetectorFSMwithTestBench

lStateMachinewithMooreandMealyoutputs

lMooreStateMachinewithExplicitStateencoding

lMealyStateMachinewithRegisteredOutputs

lMooreStateMachinewithConcurrentOutputLogic

Systems

lPelicanCrossingController

lSimpleMicroprocessorSystem

lBoothMultiplier

lLotteryNumberGenerator

lDigitalDelayUnit

lChessClock

ADCandDAC

lPackagedefiningaBasicAnaloguetype

l16-bitAnaloguetoDigitalConverter

l16-bitDigitaltoAnalogueConverter

l8-bitAnaloguetoDigitalConverter

l8-bitUnipolarSuccessiveApproximationADC

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ExamplesofVHDLDescriptions

Arithmetic

l8-bitUnsignedMultiplier

ln-bitAdderusingtheGenerateStatement

lAVarietyofAdderStyles

lBoothMultiplier

Registers

lUniversalRegister

lOctalD-TypeRegisterwith3-StateOutputs

lQuadD-TypeFlip-flop

l8-bitRegisterwithSynchronousLoadandClear

UniversalRegister

Description-Thisdesignisauniversalregisterwhichcanbeusedasastraightforwardstorageregister,abi-directionalshiftregister,anupcounterandadowncounter.Theregistercanbeloadedfromasetofparalleldatainputs

andthemodeiscontrolledbya3-bitinput.The'termcnt'(terminalcount)outputgoeshighwhentheregistercontainszero.

LIBRARYieee;

USEieee.Std_logic_1164.ALL;

USEieee.Std_logic_unsigned.ALL;

ENTITYunicntrIS

GENERIC(n:Positive:=8);--sizeofcounter/shifter

PORT(clock,serinl,serinr:INStd_logic;--serialinputs

mode:INStd_logic_vector(2DOWNTO0);--modecontrol

datain:INStd_logic_vector((n-1)DOWNTO0);--parallelinputsdataout:OUTStd_logic_vector((n-1)DOWNTO0);--paralleloutputs

termcnt:OUTStd_logic);--terminalcountoutput

ENDunicntr;

ARCHITECTUREv1OFunicntrIS

SIGNALint_reg:Std_logic_vector((n-1)DOWNTO0);

BEGIN

main_proc:PROCESS

BEGIN

WAITUNTILrising_edge(clock);

CASEmodeIS

--reset

WHEN"000"=>int_reg<=(OTHERS=>'0');

--parallelload

WHEN"001"=>int_reg<=datain;

--countup

WHEN"010"=>int_reg<=int_reg+1;

--countdown

WHEN"011"=>int_reg<=int_reg-1;

--shiftleft

WHEN"100"=>int_reg<=int_reg((n-2)DOWNTO0)&serinl;

--shiftright

WHEN"101"=>int_reg<=serinr&int_reg((n-1)DOWNTO1);

--donothing

WHENOTHERS=>NULL;

ENDCASE;

ENDPROCESS;

det_zero:PROCESS(int_reg)--detectswhencountis0

BEGIN

termcnt<='1';

FORiINint_reg'RangeLOOP

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ExamplesofVHDLDescriptions

IFint_reg(i)='1'THEN

termcnt<='0';

EXIT;

ENDIF;

ENDLOOP;

ENDPROCESS;

--connectinternalregistertodataoutport

dataout<=int_reg;

ENDv1;

OctalD-TypeRegisterwith3-StateOutputs

SimplemodelofanOctalD-typeregisterwiththree-stateoutputsusingtwoconcurrentstatements.

LIBRARYieee;

USEieee.std_logic_1164.ALL;

ENTITYttl374IS

PORT(clock,oebar:INstd_logic;

data:INstd_logic_vector(7DOWNTO0);

qout:OUTstd_logic_vector(7DOWNTO0));

ENDENTITYttl374;

ARCHITECTUREusing_1164OFttl374IS

--internalflip-flopoutputs

SIGNALqint:std_logic_vector(7DOWNTO0);

BEGIN

qint<=dataWHENrising_edge(clock);--d-typeflipflops

qout<=qintWHENoebar='0'ELSE"ZZZZZZZZ";--three-statebuffersENDARCHITECTUREusing_1164;

Exclusive-ORGate(Dataflowstyle)

--2inputexclusiveor

--ModeledattheRTLlevel.

entityx_oris

port(

in1:inbit;

in2:inbit;

out1:outbit);

endx_or;

architecturertlofx_oris

begin

out1<=in1xorin2after10ns;

endrtl;

Exclusive-ORGate(Behaviouralstyle)

--Exclusiveorgate

--modeledatthebehaviorallevel.

entityx_oris

port(

in1:inbit;

in2:inbit;

out1:outbit);

endx_or;

architecturebehaviorofx_oris

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ExamplesofVHDLDescriptions

begin

process(in1,in2)

begin

ifin1=in2then

out1<='0'after10ns;

elseout1<='1'after10ns;

endif;

endprocess;

endbehavior;

Exclusive-ORGate(Structuralstyle)

--2inputexclusive-orgate.

--Modeledatthestructurallevel.

entityx_oris

port(

in1:inbit;

in2:inbit;

out1:outbit);

endx_or;

entityand_gateis

port(

a:inbit;

b:inbit;

c:outbit);

endand_gate;

architecturebehaviorofand_gateis

begin

process(a,b)

begin

c<=aandbafter5ns;

endprocess;

endbehavior;

entityor_gateis

port(

d:inbit;

e:inbit;

f:outbit);

endor_gate;

architecturebehaviorofor_gateis

begin

process(d,e)

begin

f<=doreafter4ns;

endprocess;

endbehavior;

entityinverteris

port(

g:inbit;

h:outbit);

endinverter;

architecturebehaviorofinverteris

begin

process(g)

begin

h<=notgafter3ns;

endprocess;

endbehavior;

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ExamplesofVHDLDescriptions

architecturestructuralofx_oris

--signaldeclarations

signalt1,t2,t3,t4:bit;

--localcomponentdeclarations

componentand_gate

port(a,b:inbit;c:outbit);

endcomponent;

componentor_gate

port(d,e:inbit;f:outbit);

endcomponent;

componentinverter

port(g:inbit;h:outbit);

endcomponent;

begin

--componentinstantiationstatements

u0:and_gateportmap(a=>t1,b=>in2,c=>t3);

u1:and_gateportmap(a=>in1,b=>t2,c=>t4);

u2:inverterportmap(g=>in1,h=>t1);

u3:inverterportmap(g=>in2,h=>t2);

u4:or_gateportmap(d=>t3,e=>t4,f=>out1);

endstructural;

Three-inputMajorityVoter

Theentitydeclarationisfollowedbythreealternativearchitectureswhichachievethesamefunctionalityindifferentways.

ENTITYmajIS

PORT(a,b,c:INBIT;m:OUTBIT);

ENDmaj;

--Dataflowstylearchitecture

ARCHITECTUREconcurrentOFmajIS

BEGIN

--selectedsignalassignmentstatement(concurrent)

WITHa&b&cSELECT

m<='1'WHEN"110"|"101"|"011"|"111",'0'WHENOTHERS;

ENDconcurrent;

--Structuralstylearchitecture

ARCHITECTUREstructureOFmajIS

--declarecomponentsusedinarchitecture

COMPONENTand2PORT(in1,in2:INBIT;out1:OUTBIT);

ENDCOMPONENT;

COMPONENTor3PORT(in1,in2,in3:INBIT;out1:OUTBIT);

ENDCOMPONENT;

--declarelocalsignals

SIGNALw1,w2,w3:BIT;

BEGIN

--componentinstantiationstatements.

--portsofcomponentaremappedtosignals

--withinarchitecturebyposition.

gate1:and2PORTMAP(a,b,w1);

gate2:and2PORTMAP(b,c,w2);

gate3:and2PORTMAP(a,c,w3);

gate4:or3PORTMAP(w1,w2,w3,m);

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ExamplesofVHDLDescriptions

ENDstructure;

--Behaviouralstylearchitectureusingalook-uptable

ARCHITECTUREusing_tableOFmajIS

BEGIN

PROCESS(a,b,c)

CONSTANTlookuptable:BIT_VECTOR(0TO7):="00010111";VARIABLEindex:NATURAL;

BEGIN

index:=0;--indexmustbeclearedeachtimeprocessexecutes

IFa='1'THENindex:=index+1;ENDIF;

IFb='1'THENindex:=index+2;ENDIF;

IFc='1'THENindex:=index+4;ENDIF;

m<=lookuptable(index);

ENDPROCESS;

ENDusing_table;

MagnitudeComparator

--VHDLdescriptionofa4-bitmagnitudecomparatorwithexpansioninputs--firstarchitecturedemonstratesuseofrelationaloperatorson

--bitvectors(=,>,<).Secondarchitectureshowssequentialbehaviour--description.Bothdescriptionsdonotfullymodelbehaviourofreal--deviceforallpossiblecombinationsofinputs.

ENTITYmag4compIS

GENERIC(eqdel,gtdel,ltdel:TIME:=10ns);--outputdelayparameters

PORT(a,b:INBIT_VECTOR(3DOWNTO0);--inputwords,DOWNTOorderingneededforcomparisonoperators

aeqbin,agtbin,altbin:INBIT;--expansioninputs

aeqbout,agtbout,altbout:OUTBIT);--outputs

ENDmag4comp;

ARCHITECTUREdataflowOFmag4compIS

--thisarchitectureassumesthatonlyoneoftheexpansioninputs

--isactiveatanytime,ifmorethanoneexpansioninputisactive,

--morethanoneoutputmaybeactive.

BEGIN

aeqbout<='1'AFTEReqdelWHEN((a=b)AND(aeqbin='1'))

ELSE'0'AFTEReqdel;

agtbout<='1'AFTERgtdelWHEN((a>b)OR((a=b)AND(agtbin='1')))ELSE'0'AFTERgtdel;

altbout<='1'AFTERltdelWHEN((a<b)OR((a=b)AND(altbin='1')))ELSE'0'AFTERltdel;

ENDdataflow;

ARCHITECTUREbehaviourOFmag4compIS

BEGIN

PROCESS(a,b,aeqbin,agtbin,altbin)

BEGIN

IF(a>b)THEN

agtbout<='1'AFTERgtdel;

aeqbout<='0'AFTEReqdel;

altbout<='0'AFTERltdel;

ELSIF(a<b)THEN

altbout<='1'AFTERltdel;

aeqbout<='0'AFTEReqdel;

agtbout<='0'AFTERgtdel;

ELSE--a=b,expansioninputshavepriorityordering

IF(aeqbin='1')THEN

aeqbout<='1'AFTEReqdel;

agtbout<='0'AFTERgtdel;

altbout<='0'AFTERltdel;

ELSIF(agtbin='1')THEN

agtbout<='1'AFTERgtdel;

altbout<='0'AFTERltdel;

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ExamplesofVHDLDescriptions

aeqbout<='0'AFTEReqdel;

ELSIF(altbin='1')THEN

agtbout<='0'AFTERgtdel;

altbout<='1'AFTERltdel;

aeqbout<='0'AFTEReqdel;

ELSE

agtbout<='0'AFTERgtdel;

altbout<='0'AFTERltdel;

aeqbout<='0'AFTEReqdel;

ENDIF;

ENDIF;

ENDPROCESS;

ENDbehaviour;

8-bitRegisterwithSynchronousLoadandClear

Thedesignentityshowsthestandardwayofdescribingaregisterusingasynchronousprocess,ie.aprocesscontainingasinglewaitstatementwhichistriggeredbyarisingedgeontheclockinput.

libraryieee;

useieee.std_logic_1164.all;

entityreg8is

port(clock,clear,load:instd_logic;

d:instd_logic_vector(7downto0);

q:outstd_logic_vector(7downto0));

endentityreg8;

architecturev1ofreg8is

begin

reg_proc:process

begin

waituntilrising_edge(clock);

ifclear='1'then

q<=(others=>'0');

elsifload='1'then

q<=d;

endif;

endprocess;

endarchitecturev1;

BCDtoSevenSegmentDecoder

Theuseofthestd_logicliteral'-'(don'tcare)isprimarilyforthesynthesistool.Thisexampleillustratestheuseoftheselectedsignalassignment.

LIBRARYieee;

USEieee.std_logic_1164.ALL;

ENTITYseg7decIS

PORT(bcdin:INstd_logic_vector(3DOWNTO0);

segout:OUTstd_logic_vector(6DOWNTO0));

ENDseg7dec;

ARCHITECTUREver3OFseg7decIS

BEGIN

WITHbcdinSELECT

segout<="1000000"WHENX"0",

"1100111"WHENX"1",

"1101101"WHENX"2",

"0000011"WHENX"3",

"0100101"WHENX"4",

"0001001"WHENX"5",

"0001000"WHENX"6",

"1100011"WHENX"7",

"0000000"WHENX"8",

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ExamplesofVHDLDescriptions

"0000001"WHENX"9",

""WHENOTHERS;

ENDver3;

2-to-4DecoderwithTestbenchandConfiguration

ThissetofdesignunitsillustratesseveralfeaturesoftheVHDLlanguageincluding:lUsinggenericstopasstimedelayvaluestodesignentities.

lDesignhierarchyusinginstantiatedcomponents.

lTestbenchesfordesignverification.

lConfigurationdeclarationforbindingcomponentstodesignentitiesandsettingdelayvalues.

--ANATOMYOFAVHDLMODEL

--ThisVHDLsourcedescriptionillustratestheuse

--ofthebasicconstructsofVHDL.

--Themodeldescribesa2-input/4-outputdecoder

--comprisingtwobehaviouralprimitives'inv'and'and3'

--instancedinastructure.

ENTITYinvIS

GENERIC(tplh,tphl,tplhe,tphle:TIME:=1ns);

PORT(a:INBIT;b:OUTBIT);

ENDinv;

ARCHITECTUREbehaviourOFinvIS

BEGIN

PROCESS(a)

VARIABLEstate:BIT;

BEGIN

state:=NOT(a);

IFstate='1'THEN

b<=stateAFTER(tplh+tplhe);

ELSE

b<=stateAFTER(tphl+tphle);

ENDIF;

ENDPROCESS;

ENDbehaviour;

ENTITYand3IS

GENERIC(tplh,tphl,tplhe,tphle:TIME:=1ns);

PORT(a1,a2,a3:INBIT;o1:OUTBIT);

ENDand3;

ARCHITECTUREbehaviourOFand3IS

BEGIN

PROCESS(a1,a2,a3)

VARIABLEstate:BIT;

BEGIN

state:=a1ANDa2ANDa3;

IFstate='1'THEN

o1<=stateAFTER(tplh+tplhe);

ELSE

o1<=stateAFTER(tphl+tphle);

ENDIF;

ENDPROCESS;

ENDbehaviour;

ENTITYdec2to4IS

PORT(s0,s1,en:INBIT;y0,y1,y2,y3:OUTBIT);

ENDdec2to4;

ARCHITECTUREstructuralOFdec2to4IS

COMPONENTinv

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ExamplesofVHDLDescriptions

PORT(a:INBIT;b:OUTBIT);ENDCOMPONENT;

COMPONENTand3

PORT(a1,a2,a3:INBIT;o1:OUTBIT);ENDCOMPONENT;

SIGNALns0,ns1:BIT;

BEGIN

i1:invPORTMAP(s0,ns0);

i2:invPORTMAP(s1,ns1);

a1:and3PORTMAP(en,ns0,ns1,y0);

a2:and3PORTMAP(en,s0,ns1,y1);

a3:and3PORTMAP(en,ns0,s1,y2);

a4:and3PORTMAP(en,s0,s1,y3);

ENDstructural;

ENTITYdec2to4_stimIS

PORT(stimulus:OUTBIT_VECTOR(0TO2);response:INBIT_VECTOR(0TO3));ENDdec2to4_stim;

ARCHITECTUREbehaviouralOFdec2to4_stimIS

BEGIN

stimulus<=TRANSPORT"000"AFTER0ns,

"100"AFTER100ns,

"010"AFTER200ns,

"110"AFTER300ns,

"001"AFTER400ns,

"101"AFTER500ns,

"011"AFTER600ns,

"111"AFTER700ns;

ENDbehavioural;

ENTITYdec2to4_benchIS

ENDdec2to4_bench;

ARCHITECTUREstructuralOFdec2to4_benchIS

COMPONENTdec2to4

PORT(s0,s1,en:INBIT;y0,y1,y2,y3:OUTBIT);

ENDCOMPONENT;

COMPONENTdec2to4_stim

PORT(stimulus:OUTBIT_VECTOR(0TO2);response:INBIT_VECTOR(0TO3));ENDCOMPONENT;

SIGNALstimulus:BIT_VECTOR(0TO2);

SIGNALresponse:BIT_VECTOR(0TO3);

BEGIN

generator:dec2to4_stimPORTMAP(stimulus,response);

circuit:dec2to4PORTMAP(stimulus(1),stimulus(2),stimulus(0),

response(0),response(1),response(2),response(3));

ENDstructural;

CONFIGURATIONpartsOFdec2to4_benchIS

FORstructural

FORgenerator:dec2to4_stim

USEENTITYwork.dec2to4_stim(behavioural);

ENDFOR;

FORcircuit:dec2to4

USEENTITYwork.dec2to4(structural);

FORstructural

FORALL:inv

USEENTITYwork.inv(behaviour)

GENERICMAP(tplh=>10ns,

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ExamplesofVHDLDescriptions

tphl=>7ns,

tplhe=>15ns,

tphle=>12ns);

ENDFOR;

FORALL:and3

USEENTITYwork.and3(behaviour)

GENERICMAP(tplh=>8ns,

tphl=>5ns,

tplhe=>20ns,

tphle=>15ns);

ENDFOR;

ENDFOR;

ENDFOR;

ENDFOR;

ENDparts;

GeneratedBinaryUpCounter

ThefirstdesignentityisaT-typeflip-flop.Thesecondisanscalablesynchronousbinaryupcounterillustratingtheuseofthegeneratestatementtoproduceregularstructuresofcomponents.

libraryieee;

useieee.std_logic_1164.all;

entitytffis

port(clk,t,clear:instd_logic;q:bufferstd_logic);

endtff;

architecturev1oftffis

begin

process(clear,clk)

begin

ifclear='1'then

q<='0';

elsifrising_edge(clk)then

ift='1'then

q<=notq;

else

null;

endif;

endif;

endprocess;

endv1;

libraryieee;

useieee.std_logic_1164.all;

entitybigcntris

generic(size:positive:=32);

port(clk,clear:instd_logic;

q:bufferstd_logic_vector((size-1)downto0));

endbigcntr;

architecturev1ofbigcntris

componenttffis

port(clk,t,clear:instd_logic;q:bufferstd_logic);

endcomponent;

signaltin:std_logic_vector((size-1)downto0);

begin

genttf:foriin(size-1)downto0generate

ttype:tffportmap(clk,tin(i),clear,q(i));

endgenerate;

genand:foriin0to(size-1)generate

t0:ifi=0generate

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ExamplesofVHDLDescriptions

tin(i)<='1';

endgenerate;

t1_size:ifi>0generate

tin(i)<=q(i-1)andtin(i-1);

endgenerate;

endgenerate;

endv1;

CounterusingMultipleWaitStatements

Thisexampleshowsaninefficientwayofdescribingacounter.

--vhdlmodelofa3-statecounterillustratingtheuse

--oftheWAITstatementtosuspendaprocess.Ateachwait

--statementthesimulationtimeisupdatedonecycle,transferring

--thedrivervaluetotheoutputcount.

--Thisarchitectureshowsthatthereisnodifferencebetween

--WAITUNTIL(clock'EVENTANDclock='1')andWAITUNTILclock='1'

ENTITYcntr3IS

PORT(clock:INBIT;count:OUTNATURAL);

ENDcntr3;

ARCHITECTUREusing_waitOFcntr3IS

BEGIN

PROCESS

BEGIN

--WAITUNTIL(clock'EVENTANDclock='1');

WAITUNTILclock='1';

count<=0;

--WAITUNTIL(clock'EVENTANDclock='1');

WAITUNTILclock='1';

count<=1;

--WAITUNTIL(clock'EVENTANDclock='1');

WAITUNTILclock='1';

count<=2;

ENDPROCESS;

ENDusing_wait;

CounterusingaConversionFunction

Thiscounterusesanaturalnumbertoholdthecountvalueandconvertsitintoabit_vectorforoutput.Illustratestheuseofafunction.

--4-bitbinaryupcounterwithasynchronousreset2/2/93

ENTITYcntr4bitIS

PORT(reset,clock:INBIT;count:OUTBIT_VECTOR(0TO3));

ENDcntr4bit;

ARCHITECTUREdataflowOFcntr4bitIS

--interfacefunctiontogenerateoutputbit_vectorfrom

--internalcountvalue.

FUNCTIONnat_to_bv(input:NATURAL;highbit:POSITIVE)

RETURNBIT_VECTORIS

VARIABLEtemp:NATURAL:=0;

VARIABLEoutput:BIT_VECTOR(0TOhighbit);

BEGIN

temp:=input;

--checkthatinputfitsinto(highbit+1)bits

ASSERT(temp<=(2**(highbit+1)-1))

REPORT"inputno.isoutofrange"SEVERITYERROR;

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ExamplesofVHDLDescriptions

--generatebitvalues

FORiINhighbitDOWNTO0LOOP

IFtemp>=(2**i)

THENoutput(i):='1';

temp:=temp-(2**i);

ELSEoutput(i):='0';

ENDIF;

ENDLOOP;

RETURNoutput;

ENDnat_to_bv;

--signaltoholdcurrentcountvalue

SIGNALintcount:NATURAL:=0;

BEGIN

--conditionalnaturalsignalassignmentmodelscounter

intcount<=0WHEN(reset='1')ELSE

((intcount+1)MOD16)WHEN(clock'EVENTANDclock='1')

ELSEintcount;

--interfacefunctionconvertsnaturalcounttobit_vectorcount

count<=nat_to_bv(intcount,3);

END;

Quad2-inputNand

SimpleconcurrentmodelofaTTLquadnandgate.

--uses1993stdVHDL

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT00is

port(A1,B1,A2,B2,A3,B3,A4,B4:instd_logic;

Y1,Y2,Y3,Y4:outstd_logic);

endHCT00;

architectureVER1ofHCT00is

begin

Y1<=A1nandB1after10ns;

Y2<=A2nandB2after10ns;

Y3<=A3nandB3after10ns;

Y4<=A4nandB4after10ns;

endVER1;

Dual2-to-4Decoder

Asetofconditionalsignalassignmentsmodeladual2-to-4decoder

--uses1993stdVHDL

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT139is

port(A2,B2,G2BAR,A1,B1,G1BAR:instd_logic;

Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:outstd_logic);

endHCT139;

architectureVER1ofHCT139is

begin

Y10<='0'when(B1='0')and((A1='0')and(G1BAR='0'))else'1';

Y11<='0'when(B1='0')and((A1='1')and(G1BAR='0'))else'1';

Y12<='0'when(B1='1')and((A1='0')and(G1BAR='0'))else'1';

Y13<='0'when(B1='1')and((A1='1')and(G1BAR='0'))else'1';

Y20<='0'when(B2='0')and((A2='0')and(G2BAR='0'))else'1';

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ExamplesofVHDLDescriptions

Y21<='0'when(B2='0')and((A2='1')and(G2BAR='0'))else'1';

Y22<='0'when(B2='1')and((A2='0')and(G2BAR='0'))else'1';

Y23<='0'when(B2='1')and((A2='1')and(G2BAR='0'))else'1';

endVER1;

QuadD-TypeFlip-flop

Thisexampleshowshowaconditionalsignalassignmentstatementcouldbeusedtodescribesequentiallogic(itismorecommontouseaprocess).Thekeyword'unaffected'isequivalenttothe'null'statementinthesequentialpart

ofthelanguage.Themodelwouldworkexactlythesamewithouttheclause'elseunaffected'attachedtotheendofthestatement.

--uses1993stdVHDL

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT175is

port(D:instd_logic_vector(3downto0);

Q:outstd_logic_vector(3downto0);

CLRBAR,CLK:instd_logic);

endHCT175;

architectureVER1ofHCT175is

begin

Q<=(others=>'0')when(CLRBAR='0')

elseDwhenrising_edge(CLK)

elseunaffected;

endVER1;

OctalBusTransceiver

Thisexampleshowstheuseofthehighimpedanceliteral'Z'providedbystd_logic.Theaggregate'(others=>'Z')'meansallofthebitsofBmustbeforcedto'Z'.PortsAandBmustberesolvedforthismodeltoworkcorrectly(hencestd_logicratherthan

std_ulogic).

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT245is

port(A,B:inoutstd_logic_vector(7downto0);

DIR,GBAR:instd_logic);

endHCT245;

architectureVER1ofHCT245is

begin

A<=Bwhen(GBAR='0')and(DIR='0')else(others=>'Z');

B<=Awhen(GBAR='0')and(DIR='1')else(others=>'Z');

endVER1;

Quad2-inputOR

--uses1993stdVHDL

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT32is

port(A1,B1,A2,B2,A3,B3,A4,B4:instd_logic;

Y1,Y2,Y3,Y4:outstd_logic);

endHCT32;

architectureVER1ofHCT32is

begin

Y1<=A1orB1after10ns;

Y2<=A2orB2after10ns;

Y3<=A3orB3after10ns;

Y4<=A4orB4after10ns;

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ExamplesofVHDLDescriptions

endVER1;

8-bitIdentityComparator

--uses1993stdVHDL

libraryIEEE;

useIEEE.Std_logic_1164.all;

entityHCT688is

port(Q,P:instd_logic_vector(7downto0);

GBAR:instd_logic;PEQ:outstd_logic);

endHCT688;

architectureVER1ofHCT688is

begin

PEQ<='0'when((To_X01(P)=To_X01(Q))and(GBAR='0'))else'1';endVER1;

HammingEncoder

A4-bitHammingCodeencoderusingconcurrentassignments.Theoutputvectorisconnectedtotheindividualparitybitsusinganaggregateassignment.

ENTITYhamencIS

PORT(datain:INBIT_VECTOR(0TO3);--d0d1d2d3

hamout:OUTBIT_VECTOR(0TO7));--d0d1d2d3p0p1p2p4

ENDhamenc;

ARCHITECTUREver2OFhamencIS

SIGNALp0,p1,p2,p4:BIT;--checkbits

BEGIN

--generatecheckbits

p0<=(datain(0)XORdatain(1))XORdatain(2);

p1<=(datain(0)XORdatain(1))XORdatain(3);

p2<=(datain(0)XORdatain(2))XORdatain(3);

p4<=(datain(1)XORdatain(2))XORdatain(3);

--connectupoutputs

hamout(4TO7)<=(p0,p1,p2,p4);

hamout(0TO3)<=datain(0TO3);

ENDver2;

HammingDecoder

ThisHammingdecoderacceptsan8-bitHammingcode(producedbytheencoderabove)andperformssingleerrorcorrectionanddoubleerrordetection.

ENTITYhamdecIS

PORT(hamin:INBIT_VECTOR(0TO7);--d0d1d2d3p0p1p2p4

dataout:OUTBIT_VECTOR(0TO3);--d0d1d2d3

sec,ded,ne:OUTBIT);--diagnosticoutputs

ENDhamdec;

ARCHITECTUREver1OFhamdecIS

BEGIN

PROCESS(hamin)

VARIABLEsyndrome:BIT_VECTOR(3DOWNTO0);

BEGIN

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ExamplesofVHDLDescriptions

--generatesyndromebits

syndrome(0):=(((((((hamin(0)XORhamin(1))XORhamin(2))XORhamin(3))XORhamin(4))XORhamin(5))XORhamin(6))XORhamin(7));syndrome(1):=(((hamin(0)XORhamin(1))XORhamin(3))XORhamin(5));syndrome(2):=(((hamin(0)XORhamin(2))XORhamin(3))XORhamin(6));syndrome(3):=(((hamin(1)XORhamin(2))XORhamin(3))XORhamin(7));IF(syndrome="0000")THEN--noerrors

ne<='1';

ded<='0';

sec<='0';

dataout(0TO3)<=hamin(0TO3);

ELSIF(syndrome(0)='1')THEN--singlebiterror

ne<='0';

ded<='0';

sec<='1';

CASEsyndrome(3DOWNTO1)IS

WHEN"000"|"001"|"010"|"100"=>

dataout(0TO3)<=hami