2010計(jì)算機(jī)組成與體系結(jié)構(gòu)卷

學(xué)號(hào)學(xué)院 學(xué)號(hào)學(xué)院 專業(yè) 座位 (注意事項(xiàng)：1.請(qǐng)將密封線內(nèi)填寫清楚100120 ——二三四五單項(xiàng)選擇題（2pointsAnswerthequestion1-2basedonthefollowingAmemorysystemuses24-bitphysicaladdress.Ithasadirect-mappedcachewith64entries.Theblocksizeis4words(wordsizeis4bytes).Eachcacheentryhasa“validbit”,a“tagfield”,andspacefordata.Thenumberofbitsforthetagfield B. C. D.Thetotalnumberofbitsinthecache 26*(143)B.26*(33)C.28*(145)D.Whichoneofthefollowingaboutone-addressinstructionistrue? One-addressinstructionhasonlyoneOne-addressinstructionmayhaveoneoperandortwoOne-addressinstructionhastwooperands,andtheotheroperandisprovidedOne-addressinstructionmayhavethreeoperands,andtheothertwooperandsareprovidedimplicitlyCPUresponsestheinterrupt afteritcompletesitsfetchafteritcompletesitsexecutionwhentheinterruptsourceissuestheinterruptwhenthebusisnotTheadvantageofcarry-lookaheadadder OptimizethestructureoftheSavehardwareAcceleratethegenerationoftheAugmentthestructureoftheInmicroprogram-controlledmachines,therelationshipbetweenthemachineinstructionandthemicroinstructionis amachineinstructionisexecutedbyaamicroinstrucitoniscomposedofseveralmachineamachineinstructionisinterpretedbyamicroroutinecomposedofamicroroutineisexecutedbyamachineOncetheDMAcontrollerobtainsaccesstothesystembus,ittransfersonebyteofdataandthenreturnsthecontrolofsystemtotheprocessor.ThisDMAtransfermodeis.Burst C.CycleStealingBlock D.TransparentAssumethatthecapacityofakindofSRAMchipis16K×32,sothesumofaddresslinesanddatalinesofthischipis B. C. D.Assumethatthemultiplicandis110011andthemultiplieris101110.IfmultiplythemusingtheBoothalgorithm,thentheBoothrecodingmultiplieris –1–100–1 –1+100–1B.+1–100+1 1+100–1Themicroroutinesforallinstructionsintheinstructionsetofacomputerarestoredinthe memory controlmain D. istheprocessbywhichthenextdeviceto ethebusmasterisselectedandbusmastershipistransferredtoit.Bus BusBus D.Bus has/haveexternalfragmentation C.Segmentationwith D.SegmentationandsegmentationwithTherangeandaccuracyoffloating-pointnumbersdepend ThesizeofexponentandtherepresentationofThesizeofexponentandthesizeofThesizeofmantissaandtherepresentationofThesizeofmantissaandthesizeofInasynchronousbus,controllingofdatatransferonthebusisbasedon acommonclocksignalahandshakesignalbothclocksignalandhandshakeeitherclocksignalorhandshakeWhichoneofthefollowingisnotusedtopreventdatahazards? zeor簡(jiǎn)答題（5pointsWhatisthedifferencebetweenDRAMandSRAM,intermsofcharacteristicssuchasspeed,size,costandapplication?Inwhatcircumstancewillarithmeticoverflowoccurwhentworepresentedby2'scomplementformareadded?Andwriteoutthelogicexpressiontodetectoverflow.Describetheprocessofinterrupt(5points)Whataretheadvantagesanddisadvantagesofhardwiredmicroprogrammed綜合題（10pointsUsingnonrestoringdivisionalgorithm,performtheoperationsA÷Bonthe5-bitunsignednumbersA=10101andB=00101.Writethecomputationprocessesinacomputermachine.Abyte-addressablecomputerhas16addresslines,8datalines,WR(read/writecontrolsignal)andMREQsignal(accessmemorycontrolsignal).Itsaddressspaceincludes:systemprogramarearangingfrom0touserprogramarearangingfrom8192toandthelast2KaddressspaceforsystemprogramworkingareaTherearesomememorychips:ROM:SRAM:16K×1,2K×8,4K×8,PleasespecifyhowmanychipstoselecttodesignthemainmemoryoftheDrawthelogicstructurefigureofthemainmemory,andtheconnectionbetweenthemainmemoryandCPU.Thefollowingfiguregivespartofthemicroinstructionsequencecorrespondingoneofthemachineinstructionsofamicroprogrammedcomputer.MicroinstructionBisfollowedbyC,E,F,orI,dependingonbitsb6andb5ofthemachineinstructionregister.Comparethetwopossibleimplementationsdescribedbelow.Microinstructionsequencingis plishedbymeansofamicroprogramcounter.Branchingisachievedbymicroinstructionsoftheform:Ifb6b5branchtowhereb6b5isthebranchconditionandXisthebranchSameas(1)exceptthatthebranchmicroinstructionhastheBranchtoX,WhereXisabasebranchaddress.Thebranchaddressismodifiedbybit-ORingofbitsb5andb6withtheappropriatebitswithX.AAIEBDCGFHJJConsideracomputerwith4M×16memorycontains97instructionsinitsinstructionset.Theopcodelengthisfixed,andtheaddressingmodesaredirect,indirect,immediate,index,andrelative.(Assumethattheinstructionlengthequalstowordlength)Drawthefigureofone-addressinstructionformat,andspecifythefunctionofeachfield.Specifythemaxrangeofthedirectaddressingmode.(inSpecifytheaddressingrangeofone-levelindirectaddressingmode.(inSpecifytheoffsetoftherelativeaddressingmode.(inAlogiccircuitisneededtoimplementtheprioritynetworkshownlikethefollowingfigure.Thenetworkhandlesthreeinterruptrequestlines.WhenarequestisreceivedonlineINTRi,thenetworkgeneratesanacknowledgementonlineINTAi.Ifmorethanonerequestisreceived,onlythehighest-priorityre