【SoC設(shè)計(jì)方法與實(shí)現(xiàn)】可測(cè)試性設(shè)計(jì)-課件

第十章可測(cè)試性設(shè)計(jì)1PPT課件OutlinesOverviewofICTestingFaultModelingAutomaticTestPatternGeneration(ATPG)Design-for-test(DFT)techniquesScanchaintechniqueMBISTBoundaryScan2PPT課件Verificationvs.TestVerificationVerifiescorrectnessofdesign.Performedbysimulation,hardwareemulation,orformalverification,etc.Performedoncepriortomanufacturing.Responsibleforqualityofdesign.TestVerifiescorrectnessofmanufacturedhardware.Two-partprocess:1.Testgeneration:softwareprocessexecutedonceduringdesign2.Testapplication:electricaltestsappliedtohardwareTestapplicationperformedoneverymanufactureddevice.Responsibleforqualityofdevices.3PPT課件TestingPrincipleThreebasicelementAknowninputStimulusAknownstateAknownexpectedresponse4PPT課件AutomaticTestEquipment(ATE)5PPT課件OverviewofICTestingWaferFabricationDieAssemblyFinalTestReliabilityStressClassProbeDieSortProbeParameterVtPVtNIgSIdSLeffWeffRes...

CoverageleakagememoryCore...CoverageDCACDigitalAnalogSpeedTempPower...QualificationBurn-inTemp-CycleHVSTESDLatch-up...PackageBGAQFPPGATABCSPSIPMCM...Design6PPT課件TestChallengesReducethecostoftestReducethevectordatasizeReducethetestersequencingcomplexityReducethecostoftestequipmentReducethetesttimeIncreasethedefectcoverageHowmanyfunctiontestpatternscancoverallthedevices?7PPT課件OutlinesOverviewofICTestingFaultModelingAutomaticTestPatternGeneration(ATPG)Design-for-test(DFT)techniques8PPT課件TypesofTestVectorSetsExhaustiveApplyeverypossibleinputvectorAlongtime!FunctionalTesteveryfunctionofthedeviceHowtoguaranteethecoverage?FaultModelDerivedFindatestforevery“modeled”faultIndustrypracticecurrently9PPT課件WhyModelFaults?FaultmodelidentifiestargetfaultsFaultmodelmakesanalysispossibleEffectivenessmeasurablebyexperiments10PPT課件Defect&FaultModelingDefinitionDefect:PhysicalabnormallyfabricateddieE.g.missing/extramaterialFault:behaviordifferenceduetoadefectE.g.inputstuck-at‘1’,outputslow-to-riseError:machinefailureduetoafaultE.g.systemfunctionalfailureBug–functionalfailurecausedbydesignproblemE.g.systemfunctionalfailure11PPT課件Defect:shorttothegrandFault:signalbstuckatlogic0Error:happenswhena=1b=1Example12PPT課件FaultModelsFaultmodelsaretypicallydefinedonastructurebasisDifferentfaultmodelsfordigitallogic,memoriesandanalogcircuitTypicalfaultmodelsSinglestuck-atfaultsTransistoropen/shortfaultsBridgingfaultsDelayfaultsMemoryfaultsAnalogfaults13PPT課件Stuck-ATFaultsWhatisstuck-atfault?ApplicabletoanyphysicaldefectmanifestingasasignalthatisstuckatafixedlogiclevelOnestuck-atfaultcanmodelmorethanonekindofdefect14PPT課件TransitionDelayFaultModellargetransitiondelay

slowtoriseorslowtofalltransitionaninterconnectsignalhasagreaterthannormalpropagationdelayassociatedwithitThemodelbehavesasstuckatfaultforacertainperiodoftime15PPT課件PathDelayFaultItmodelsdefectsincircuitpathUnliketransitiondelayfault,pathdelayfaultsdonothavelocalizedfaultsites.AssociatedwithtestingtheACperformanceofspecificpathsTypicallycriticalpath16PPT課件MemoryFaults011100Stuck-AT-0Stuck-AT-1ORBridgingANDBridging01Transition/0Transition/10111ResetCouplingSetCoupling1010InversionCouplingInversionCoupling11101PassiveNeighborhoodPatternSensitiveActiveNeighborhoodPatternSensitive11010AdrEAdrEAdrEAdrEAdrEVariousFaultsWithAddressDecoder17PPT課件MemoryFault–cont.Neighborhoodpatternsensitivefault18PPT課件OutlinesOverviewofICTestingFaultModelingAutomaticTestPatternGeneration(ATPG)Design-for-test(DFT)Scan19PPT課件FaultCoverageFaultcoverageThepercentageoftotalfaultsforwhichtestpatternshavebeengenerated

FaultCoverage=100XNumberofDetectedFaultsTotalNumberofFaultsintheCUTFaultcoverageisinfluencedbyTestabilityofthecircuitQualityofappliedpatterns20PPT課件TestGenerationDefinitionsTestvectorsAninputvectorforthecircuit-under-testthatcausesthepresenceofafaulttobeobservableataprimaryoutputAutomatictestpatterngenerationWiththebuild-inDFTcircuit,testvectorsaregeneratedautomatically21PPT課件VectorGenerationUsingATPGToolReadinnetlistwithscanchainconnectedReadinIPandstandard-celllibrarymodelReadinSTILtestprotocolfile,generatedbyDFTcompilertool.(STIL-StandardTestInterfaceLanguageforDigitalTestVectord,IEEEStd.1450.0-1999)CheckDRCandmakeanynecessarycorrectionsPreparedesignforATPG,setupfaultlist,analyzebusesforcontentionandsettheATPGoptionsGeneratevectorsReviewthetestcoverageandre-runATPGifnecessaryCompressthevectorsConvertvectortoATEvectorformatSavetestvectorsandfaultlist22PPT課件OutlinesOverviewofICTestingFaultModelingAutomaticTestPatternGeneration(ATPG)Design-for-test(DFT)techniquesScanchainMBISTBoundaryscan23PPT課件WhatisDFT?Applydesign-for-testabilitytechniquestothedeviceduringthedesignphasetoassistwiththetestprocess,qualitymeasurementandthevectorgenerationTeststructuresisdesigned(added)intothedevice24PPT課件TraditionaldesignandtestflowAdvanceddesignandtestflow25PPT課件WhyAddtestLogic?Motivation:TestgenerationcomplexityincreasesexponentiallywiththesizeofthecircuitReasons:toincreasethetestcoverageandtoreducethetimeittakestoqualifythepart26PPT課件Pro&ConPerceptionsofDFTProsEasygeneratingvectorsEasydiagnosis&debuggingEnablesdeterministicmeasureofqualityReducesthecostoftestConsAddscomplexitytodesignmethodologyImpactsdesignpower&packagepinsImpactsdesignspeedorperformanceAddstosiliconareaReduceyield27PPT課件PopularDFTTechniquesforSoCTestingScanDealingwithsequentiallogiccircuitCommonlyusedfortestingdigitallogicBIST(Build-in-Self-Test)Commonlyusedtotestingmemoryblocks–MBISTAlsocanbefoundfortestingprocessor–LogicBISTAlsocanbefoundfortestinganalogcircuit–AnalogBISTBoundaryScanFortestingI/OconnectiononboardItalsoisacommoninterfacestandardforsystemdebuggingonboad28PPT課件ScanChain29PPT課件SequentialLogic–HardtoTest!Inreality,thesequentialalgorithmmethodisusuallyverycomplicatedandrequire:OneormoreclockpulsestolaunchthetestvectortothefaultysiteOneormoreclockcyclestopropagatethefaulteffectIngeneral,needasequenceofpatternstodetectafault!Abettersolutionistoinsertscancircuit–scandesigntechnique30PPT課件StepsofScanDesignConvertflip-flops(FF)toscanflip-flops(SFF)ConnectSFFtoscanchainsInnormalmode:SFFbehaveasusualInscanmode:SFFbehaveasshiftregister31PPT課件ScanFlip-Flop(SFF)Scancell:Mux-DScanFlipFloptypeDFFSDFFThemostwidelyacceptedscanstyleScancellwillcauselargerarea,largersetuptime,morepowerconsumption32PPT課件ScanChainConnectionReplaceallFFwithSFFConnecttoscanchains33PPT課件TestSequentialLogicUsingScanSFFs&scanchainhelptoinitializenodesandcaptureresults–controllability&observability34PPT課件ToolsforScanSynthesisandATPGFullysupportedbyEDAtoolsScaninsertionDFTcompilerfromSynopsysDFTAdvisorfromMentorTestvectorgeneration(ATPG)TetraMAXfromSynopsysFastScanfromMentorTestpatternverificationSTAisusedtocheckthescantesttiminginscanmodeSimulationisusedtoverifyATPGpattern35PPT課件ScanDesignRulesScandesignrules

governthecontrollabilityandobservabilityofscandesign(faultcoverage)Scandesignrulechecking

(DRC)providesyouwithfeedbackonthetestabilityofyourdesign(Doesthesignalscanpaththescanchain?)36PPT課件BasicScanDesignRulesUseonlyMux-Dtypeofflip-flopsforallstatevariablesAllclocks/resetmustbecontrolledfromPIs.Clocksmustnotfeedinputsofflip-flops(toDpinofFF)Donotusetri-statebusdesignordisablethetri-statebufferduringscantest37PPT課件Example:DealingwithTri-statebus

Tri-statebusDuringscanshifts,multipledriversonabusmaydrivethebussimultaneouslywhichcausesbuscontentionproblemornodriveronthebusleadtoafloatingbus.Fix:Muxaddedtomakethebuscontrollableduringscanmode38PPT課件Example:DealingwithBlackBoxBypassBlackBoxAnalogblocks,memories,hardmacros39PPT課件Example:MemoryBlockInterfaceBypassMemoryBlock:addingshadowregister(Optional)Ifthechip-testinggoalsincludescantestingforACcoverage(transitionandpathdelay),thenthepreviousbypassmethodmaynotbesufficient.Tomoreemulatethememorypathway,aregisterisplacedinthetransparentdatapathShadowregisterscanchainisinsertedbytool40PPT課件GeneralDFTConsiderationforSoCDesignAvoidasynchronousdesignstyle.Limitthenumberofdifferentclockdomainsinachip.Formultipleclocks,maketheFFsineachindividualclockdomainformtheirownscanchainstoavoidthebiggervariationinskew.Oraddmuxingattheclocksource,sothatonlyoneclockisusedduringscan-modeandclocktreesynthesisReplaceanyinternally-generated/dividedclocks/resetwithscanclocks/resetfromPIsduringtestingHighfanoutsignalpin,Scan_enable,shouldbetakencarebysynthesistools41PPT課件PrepareScanwrappersfornon-synthesizablemodules,suchasmemoryblockAvoidlongscanchain,max1000FFsperchainAvoidpowerconsumptionissue,mayneedtoseparatethewholechiptofewscanmodesandtheclockstothemodulenotbeingtestedshouldbedisabledScanchainreorderingmayneedinlayoutstageGeneralDFTConsideration-cont42PPT課件ScanOverhead:Scanpathimpacttiming,areaandpowergoalsModerateareaoverheadabout10%,speed5%Multiplexerdelayaddedincombinationalpath;approx.twogate-delaysFlip-flopoutputloadingduetooneadditionalfanout;approx.5-6%Atleastoneextrapinsforscanmodesignals:scan_mode,scan_enable,scan_clk,scan_reset,scan_in,scan_outGeneralDFTConsideration–cont.43PPT課件ScanDesignFlow44PPT課件TypicalQualityRequirements98%singlestuck-atfaultcoverage100%interconnectfaultcoverageRejectratio–1in100,000PleasecheckthetestcoverageafterscaninsertionaswellasafterATPGFixpossibleDFTviolation45PPT課件SummaryVariousdefects(faults)existinchipsFaultmodelsdescribethefaultsDFTdealswithwaysforimprovingtestabilityDFTareessentialtoanefficientandsuccessfultesting46PPT課件MemoryBuild-in-selftest(MVIST)47PPT課件ImportanceofMemoryTestMemoryisthemostdensephysicalstructure,makingthemmoresensitivetodefectsOn-chipmemoryisgettingbiggerforSoC48PPT課件MemoryModelThefunctionalmemorymodelcontainsthreemainpartsAddressdecoderMemorycellarrayRead/writecontrollogicBasicmemoryfaults:stuck-attransitioncouplingNeighborhoodpatternsensitive49PPT課件MemoryBuiltInSelfTest(MBIST)Generaltestdataon-chipCompareorcompressdataon-chipUsedtodetectfaultsinSRAM,ROM,SDRAMandFLASH50PPT課件MemoryBuiltInSelfTest(MBIST)ComponentsofBIST:PatterngeneratorBISTcontrollerResponseanalyzer51PPT課件BasicTestPortsTestpinnameDescriptionBIST_MODETestModeSelect(usedtoselecttomuxlogic)BIST_RESETTestModeSelect(UsedtoresetBISTlogic)BIST_CLKTestClockBIST_DONETestDataOutindicatingtestcompleteBIST_FAILTestDataOutindicatingtestfail52PPT課件MemoryBISTAlgorithmsCheckerboardMarchDataRetentionTest53PPT課件CheckerboardAlgorithmDetectsstuck-atfaultsformemorycellsandadjacentcellshortsThealgorithmdividesthecellsintotwogroups(cells_1andcells_2),suchthateveryneighboringcellisinadifferentgroup.Thealgorithmthenwrites(andreads)0sintoallcellsinthecells_1groupand1sintoallcellsinthecells_2group54PPT課件MarchAlgorithmFirstpresentedattheITCin1982,theMarchalgorithm,anditsmodifications,isnowthemostpopularalgorithmformemorytesting.Testsequence（9n）(w0)(r0,w1)(r1,w0)(r0,w1)(r1,w0)TheMarchAlgorithmdetectsthefollowingfaults:stuck-attransitioncoupling-unlinkedidempotentandinversion,andothercouplingfaultsonbit-orientedaddresses55PPT課件AlgorithmMATSMATS+MATS++MARCHXMARCHC—MARCHAMARCHYMARCHBDescription{(w0);(r0,w1);(r1)}{(w0);(r0,w1);(r1,w0)}{(w0);(r0,w1);(r1,w0,r0)}{(w0);(r0,w1);(r1,w0);(r0)}{(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)}{(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)}{(w0);(r0,w1,r1);(r1,w0,r0);(r0)}{(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)}ModifiedMarchAlgorithm56PPT課件MarchTestComplexityAlgorithmMATSMATS+MATS++MARCHXMARCHC—MARCHAMARCHYMARCHBComplexity4n5n6n6n10n15n8n17n57PPT課件Retentiontestingverifiesifmemorycellscanretaintheirinitialcontentsforacertainperiodoftime.Thetimeperiodcanvaryfrom10-80msdependingmainlyonthemanufacturingprocessandtheambienttemperatureduringthetestapplicationTheinserteddelaycanrefertotheAlgorithmMarchCandCheckerboardDataRetentionTest58PPT課件Sharecontrollerwithmemoryblocks59PPT課件MemoryWrapperforLogicScan60PPT課件ToolsCommercialtoolsareavailableforMBISTdesignandATPGmBISTArchitectfromMentorSoCBISTfromSynopsys61PPT課件BoundaryScan62PPT課件What’sthepurposeofBoundaryScan?

TesttheICconnectiononthePCB(printedcircuitboardtest):Missingdevices,Damageddevices,Openandshortcircuits,Misaligneddevices,Wrongdevices

Testingtheintegratedcircuititself(debugging)Observingormodifyingcircuitactivityduringthecomponent'snormaloperationIn-systemprogramming(systemlevelapplication)Allowingprogrammingprogrammabledevices,suchasCPLDsandflashmemories,ontheboard,afterPCBassembly63PPT課件Example:TestICConnectiononPCBTestingtheinterconnectionsofchipsonaprintedcircuitboardorothersubstrateICsononeboard64PPT課件IEEEStandard1149.1Developedinthemid-1980s

bytheJTAGgroup(JointTestActionGroup)SolvephysicalaccessproblemsonPCBscausedbyincreasinglycrowdedassembliesDefinestestaccessports,architectureandoperationofboundaryscanBecomeindustrystandardIEEE1149.1since199065PPT課件IEEEStd1149.1DeviceArchitectureTestAccessPort(TAP)TAPcontrollerwithinputsTCKandTMSInstructionRegister(IR)BypassRegisterIdentificationregisterBoundary-scanregister66PPT課件BasicFunctionsofBoundaryScanArchitectureParalleltaking-overoftestvectorsintotheBoundaryScancells(sample)Serialshiftinginoftestvectorsandsimultaneousshiftingoutoftestvectorsthatweretakenover(shift)Parallelapplicationofinsertedtestvectorstothecircuitpartstobetested(update)Test/stimulationoftheinnercircuitry(internaltest)Test/stimulationofoutsidesignalsconnectedtoacircuit(externaltest)67PPT課件JTAGPinsTestpinnameDescriptionTDITestDataIn(usedtoreceiveSerialtestinstructionanddata)TMSTestModeSelect(Usedtosequencethetestcontroller’sstatemachine)TCKTestClockTDOTestDataOutTRSTTestReset68PPT課件TAPControllerTestAccessPort(TAP)ControllerControlalltestlogic’soperations69PPT課件TAPController-contFiniteStateMachineofTAPControllerAlltestlogic’soperationiscontrolledbyTAPcontroller70PPT課件BoundaryScanCircuitinDetail71PPT課件BoundaryScanRegister(Cell)Amultipurposememoryelementcalleda“boundaryscancell”or“boundaryscanregister”PI-parallelinsignalPO-paralleloutputsignalSI-serialinsignalSO-serialoutsignal72PPT課件InstructionRegisterAtleast2bitslongTheinstructionregisterhasashiftsectionthatcanbeconnectedtoTDIandTDO,andaholdsection,whichholdsthecurren