cadence專(zhuān)業(yè)知識(shí)講座

Improvingyourprocessforhigh-speedPCBdesign“Closingtheloopbetweentiminganalysisandsignalintegrity”APCBKnowledgeSetOnlineSeminarfromCadencepresentedbyToddWesterhoffSystemTimingSignalIntegrity1第1頁(yè)AgendaBasicsofsystemtiminganalysisBasicsofsignalintegrityanalysisFlighttime,bufferdelay,standardloadsandTcoKeyprocessassumptionsCheckingandverifyingmodeldataTechniquesforclosingtheloopSummary2第2頁(yè)StaticTimingAnalysisSystematicanalysisofasynchronousASIC,PCBorSystemdesign,thatidentifies:LogichazardsClockedtimingpathsTimingerrorsRequiredinputsFunctionaldescriptionofcircuit(netlist)Component-leveltimingdataCircuitoperating(clock)speeds3第3頁(yè)Whatisa“ClockedTimingPath”?AtimingpathconsistsofallofthelogicbetweentwoclockedelementsthatoperateoffthesameclocksignalThetimingpathisanalyzedtoensurethatsetupandholdrequirementsaremetattheinputofeachclockedelementTheslack(delaymargin)inthepathcanbeusedtoderiveSIflighttimeconstraints4第4頁(yè)ModernSystemDesignModernsystemsaredominatedbyhighspeedbusinterconnectionsCombinationallogichasbeen“absorbed”intootherchipsTiminganalysisfordatabusescanbeperformedusingasimplified“bus-level”timingmodelCPUAGPDIMMPCI5第5頁(yè)StandardSynchronousDataTransfer6第6頁(yè)FlightTimeAccountsfortheelectricaldelayofinterconnect(PCBetch)betweenthedrivingdeviceandreceiversCanbeestimatedforslowspeedcircuits;mustbesimulated(signalintegrity)forhighspeeddesigns7第7頁(yè)IssuesinSynchronousDesignClockJitterincreases/decreasestheindividualclockcycle,decreasingthetimeleftfordatatransfer

ClockSkewchangestheeffectiveclockperioddependingonwhichdevicesaredriving/receivingD0D1D2ClockDriverD0D1D2t=0t=1t=28第8頁(yè)Crosstalk-ImpactonBusTimingCrosstalkbetweenadjacentbusbitsaffectsedgespeed(andthereforeflighttime)Denserroutingmakesbetteruseofboardspace,butattheexpenseoflargervariationsinflighttimePre-layoutcrosstalkanalysishelpsthedesignermakethebesttradeoffbetweenroutingdensityandsignalintegrityEvenModeReferenceOddModeD0D1D2D0D1D2D0D1D2D0D1D29第9頁(yè)Bus-LevelTimingBudgetForeachindependentDriverReceiverpath:Tflightmax<ClockPeriod-Driver(Tcomax)-Skew-Jitter-Crosstalk-Receiver(Setup)Tflightmin>Receiver(Hold)-Driver(Tcomin)+Skew+CrosstalkDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)+/-Crosstalk+/-Crosstalk10第10頁(yè)DeterminingDeviceTimingTimingstakenfrom“AC(dynamic)Specifications”sectionsofdatasheetsManydatasheetsavailableon-lineviaWWWImportantparametersClock

DataValidConditionsunderwhichthisismeasuredSetup/HoldrequirementsPLLJitter(ifspec’d)Example-PentiumPro11第11頁(yè)DeterminingFlightTimes:ExampleTflightmax=4.55nsTflightmin=0.05ns12第12頁(yè)WhatIsSignalIntegrityAnalysis?AnaloganalysisofdigitalswitchingbehaviorExtractsroutinginformationfromPCBdatabaseUsespecialanalogmodelsfordeviceinputs/outputsIBISmodelingstandard13第13頁(yè)TheSignalIntegrityModelSImodelsrepresentonlythebehaviorofthedeviceoutputandinputbuffers

InternalcomponentfunctionsandassociatedtimingarenotmodeledDrivingReceivingt=0Internal

LogicnotmodeledInternal

Logicnotmodeled14第14頁(yè)MeasuringInterconnectDelayAccountsforelectricaldelaycausedbyinterconnect(PCBetch)betweenthedrivingdeviceandeachreceiveronthenetUsuallydifferentforeachdriver–receivercombinationCanbedeterminedusingsignalintegrityanalysis15第15頁(yè)MinimumandMaximumDelaysThereceiver’sinputthresholdsareusedtodeterminetheearliestandlatesttimesthattheinputchangemaybedetectedThisinformationisthenusedtodetermineminimum&maximumflighttimedataforeachdriver/receivercombinationEarliestSwitchLatestSwitchInputThresholds16第16頁(yè)ACloserLookAtTcoDinClockOutput

BufferInternal

LogicRL=50WClocktriggersatt=0VmeasTcoLoadforTcomeasurement(fromdatabook)Tco=timefromclockrisetoVmeasintotestload17第17頁(yè)ComponentsofTcoDinClockOutput

BufferInternal

LogicRL=50WClocktriggersatt=0VmeasTcoInternaldelay=fromclock

triggertothetimewhentheoutputbufferistriggeredExternal(buffer)delay=how

longthebuffertakestodrivethe

referenceloadtoVmeas18第18頁(yè)TheDouble-CountingProblemWewanttoknowatwhatpointintheclockperiodsignalsarriveandstabilizeatthereceiverinputThisiscomparedtosetup/holdconstraintsThisisfoundbycombiningcomponenttimingdata(TCO)withflighttimedatafromsignalintegrityanalysis19第19頁(yè)But,IfWeSimplyAdd…TCO(fromDatabook)

+SimulatedDelay

+TheexternalbufferdelayportionofTcogetsdouble-counted!!

20第20頁(yè)Because,WhatWeReallyWantedWas…InternalDelay

+SimulatedDelay

+21第21頁(yè)MakingThePiecesFitTogetherTherearetwowaystosolvethisdiscrepancy:AdjustthevalueofTCOusedfortiminganalysisbysubtractingoutthetimeattributedtoTCObufferdelaySubtractthetimeattributedtotheTCObufferdelayfromtheinputreceiverswitchingtimespredictedbysimulationByconvention,thelattermethodisused.22第22頁(yè)DeterminingTheBufferDelay...TheoutputbuffermodelusedforsignalintegrityanalysisisconnectedtotheTCO“testload”andsimulatedThedelayismeasuredatthepointwheretheoutputpincrossesVmeasThecorrespondingdelayissavedandusedinflighttimecomputations23第23頁(yè)MeasuringFlightTimeFlighttimeisthereforealwaysmeasuredwithrespecttothedelayintothestandardloadThisisaccomplishedbydeterminingtheTCObufferdelay,andsubtractingthatvaluefromsimulationresultsBufferdelayintoStandardLoad

880.55ps,2.5V3.0V=VIH2.0V=VIL2.5V=VmeasMaxFlight

608.71psMinFlight

476.32ps24第24頁(yè)ImplicationsTheoutput-to-inputdelay,asapparentfromwaveformdatacannotbedirectlymeasuredtodetermineflighttimeTheloadingconditionusedtocomputebufferdelayandtheconditionsunderwhichTcoismeasuredmustbeidentical25第25頁(yè)FundamentalAssumptionsTimingequationsarevalidforbustimingAssumescommonclock,synchronousdesignInter-symbolinterference(ISI)caninvalidateequationsSImodelsprovidegoodpredictionofsystembehaviorLoadingconditionforTcois“representative”ofactualsystemloadingconditionsTheTcoloadisusertocalculatebufferdelaySimulationresultsarecorrectlyadjustedtomeetthedefinitionforflighttime(eitherbythetoolormanually)26第26頁(yè)AFewWordsonDeviceModeling…QualityproblemsarenotunusualinSImodels(unfortunately)Checkmodelquality!CheckbufferdelayinformationDifferentmodelssupportdifferentpurposesPre-layoutmodels(min/maxpackageparasiticsonly)Post-layoutmodels(detailedper-pinparasiticdata)DatafromIBISmodelwithper-pinlumpedparasitics27第27頁(yè)VerifyingStandardLoadingConditions...Model_typeI/O_open_drainPolarity Non-InvertingEnableActive-LowVinl=0.8Vinh=1.2Vmeas=1.00Cref=0.00pRref=25.00Vref=1.50...IBISprovidesspecifickeywordstodefinetheconditionsunderwhichbufferdelaysshouldbesimulatedandmeasuredThemeasurement/loadingconditionsintheIBISfileshouldbethesameastheconditionsunderwhichTCOisspecifiedinthedevice’sdatasheetIBISModelFileVmeas=1.00Cref=0.00pRref=25.00Vref=1.5028第28頁(yè)ClosingTheLoopDifferentwaystointegratetiminganalysisandsignalintegrityresults:Manualapproach:determineallowablemin/maxflighttimesusingcomponenttimingdataandaspreadsheet.Usesignalintegrityanalysistoverifythatthedesignmeetsthecomputedflighttimerequirements.Generalapproach:usestatictiminganalysistoevaluatesystemtiming,andsignalintegrityanalysistocomputeflighttimes.Feedflighttimedatabackintothestatictimingtool.Bus-leveltimingapproach:usestandardtimingequationsandcomponenttimingdatatoperformspreadsheet-basedtiminganalysis.Feedflighttimesfromsignalintegrityanalysisbackintothespreadsheettocomputedesignmargins.29第29頁(yè)ManualApproachForcommon-clockbuses,allowablemin/maxflighttimescanbecomputedfrombusspeeds,systembudgetsandcomponenttimingdataTimingequationsareprogrammedintoaspreadsheetandallowableflighttimescomputedWhilenotelegant,thismethodisfast,flexibleandreliablewhenthetimingforasmallnumberofbusesneedstobedetermined30第30頁(yè)GeneralApproachTiminganalysis,layoutandSIanalysisarerunasseparateprocessesFlighttimedatafromsignalintegrityanalysisisfedbackintotiminganalysistocompletetheloopandintegratethetwosetsofdataChangingthedesignrequiresre-runningthecompleteloopSchematicCapturePCBLayoutStaticTimingAnalysisSignalIntegrityAnalysisNetlistRoutedDatabaseFlight

TimesConstraints31第31頁(yè)Bus-LevelApproachComponenttiming,busspeedsandclockjitter/skewbudgetsarecapturedaspartofthePCBdatabaseSignalintegrityanalysisisrunfromthePCBdatabaseAspreadsheetcontainingbus-leveltimingequationsisusedtocomputethedesignmarginsbasedonsimulationresultsSchematicCapturePCBLayoutTimingSpreadsheetSignalIntegrityAnalysisNetlistFlight

TimesComponentTimingDataComponent

TimingDataRouted

Database32第32頁(yè)SPECCTRAQuestTimingModelLoadedfromcomponenttimingdataSpecifiedintimingspreadsheetandsavedindatabaseDefinedaspropertyinAllegrodatabaseComputedusingSIanalysisDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)33第33頁(yè)SPECCTRAQuestTimingFlowComponent

timingdataClockNetdeclarations,operatingspeeds,clockjitterClockjitterandskewbudgetsSimulated

flighttimesSP