數(shù)集全套課件

1數(shù)字積體電路

-電路、系統(tǒng)與設(shè)計(jì)引論

2本書(shū)的內(nèi)容數(shù)字積體電路簡(jiǎn)介.CMOSdevicesandmanufacturingtechnology.CMOSinvertersandgates.Propagationdelay(傳播延時(shí)),noisemargins,andpowerdissipation.Sequentialcircuits.Arithmetic,interconnect,andmemories.Programmablelogicarrays.Designmethodologies.你要學(xué)習(xí)什麼知識(shí)？Understanding,designing,andoptimizingdigitalcircuitswithrespecttodifferentqualitymetrics:cost,speed,powerdissipation,andreliability3數(shù)字積體電路引論:數(shù)字積體電路中的設(shè)計(jì)問(wèn)題CMOS反相器組合邏輯門的設(shè)計(jì)時(shí)序邏輯門設(shè)計(jì)方法R,L,C的互聯(lián)問(wèn)題時(shí)序問(wèn)題設(shè)計(jì)運(yùn)算功能塊記憶體和陣列結(jié)構(gòu)設(shè)計(jì)4簡(jiǎn)介數(shù)字IC設(shè)計(jì)和以前相比有什麼不同?未來(lái)有什麼變化?5第一臺(tái)電腦圖1.1世界上已知的第一個(gè)自動(dòng)計(jì)算器Babbage的DifferenceEngineI（1832年）的工作部件（摘自［Swade93］，由倫敦科學(xué)博物館提供）6ENIAC–第一臺(tái)電子電腦(1946)7電晶體革命FirsttransistorBellLabs,19488第一個(gè)積體電路Bipolarlogic1960’sECL3-inputGateMotorola19669

Intel4004微處理器19711000transistors1MHzoperation10IntelPentium(IV)微處理器11摩爾定律1965年,戈登.摩爾指出每個(gè)新晶片大體上包含其前任兩倍的容量，每個(gè)晶片的產(chǎn)生都是在前一個(gè)晶片產(chǎn)生後的18~24個(gè)月內(nèi)。他預(yù)測(cè)半導(dǎo)體工藝的效率將會(huì)每18個(gè)月翻一番。12摩爾定律Electronics,April19,1965.13複雜性革命14電晶體數(shù)量Courtesy,Intel15摩爾法則在微處理器上的應(yīng)用40048008808080858086286386486Pentium?procP60.0010.010.1110100100019701980199020002010YearTransistors(MT)2Xgrowthin1.96years!TransistorsonLeadMicroprocessorsdoubleevery2yearsCourtesy,Intel16尺寸增長(zhǎng)40048008808080858086286386486Pentium?procP611010019701980199020002010YearDiesize(mm)~7%growthperyear~2Xgrowthin10yearsDiesizegrowsby14%tosatisfyMoore’sLawCourtesy,Intel17頻率Courtesy,Intel18功耗P6Pentium?proc486386286808680858080800840040.1110100197119741978198519922000YearPower(Watts)LeadMicroprocessorspowercontinuestoincreaseCourtesy,Intel19功耗將會(huì)成為首要問(wèn)題5KW18KW1.5KW500W40048008808080858086286386486Pentium?proc0.111010010001000010000019711974197819851992200020042008YearPower(Watts)PowerdeliveryanddissipationwillbeprohibitiveCourtesy,Intel20功耗密度40048008808080858086286386486Pentium?procP611010010001000019701980199020002010YearPowerDensity(W/cm2)HotPlateNuclearReactorRocketNozzlePowerdensitytoohightokeepjunctionsatlowtempCourtesy,Intel21生產(chǎn)趨勢(shì)1101001,00010,000100,0001,000,00010,000,000200319811983198519871989199119931995199719992001200520072009101001,00010,000100,0001,000,00010,000,000100,000,000LogicTr./ChipTr./StaffMonth.xxxxxxx21%/Yr.compoundProductivitygrowthratex58%/Yr.compoundedComplexitygrowthrate10,0001,0001001010.10.010.001LogicTransistorperChip(M)0.010.11101001,00010,000100,000Productivity(K)Trans./Staff-Mo.Source:SematechComplexityoutpacesdesignproductivityComplexityCourtesy,ITRSRoadmap22為什麼要縮小尺寸?Technologyshrinksby0.7/generationWitheverygenerationcanintegrate2xmorefunctionsperchip;chipcostdoesnotincreasesignificantlyCostofafunctiondecreasesby2xBut…Howtodesignchipswithmoreandmorefunctions?Designengineeringpopulationdoesnotdoubleeverytwoyears…Hence,aneedformoreefficientdesignmethodsExploitdifferentlevelsofabstraction23設(shè)計(jì)中的抽象層次24設(shè)計(jì)要求數(shù)字設(shè)計(jì)的品質(zhì)評(píng)價(jià)成本可靠性可測(cè)量性速度(延遲,工作頻率)功耗、能耗性能25積體電路的成本固定成本設(shè)計(jì)時(shí)間、人力間接成本

可變成本矽處理,封裝,測(cè)試按體積按片面積26固定成本在增加27固定成本SingledieWaferFromGoingupto12”(30cm)28單個(gè)電晶體成本0.00000010.0000010.000010.00010.0010.010.1119821985198819911994199720002003200620092012cost:￠-per-transistorFabricationcapitalcostpertransistor(Moore’slaw)29成品率30缺陷aisapproximately331一些例子(1994)ChipMetallayersLinewidthWafercostDef./cm2Areamm2Dies/waferYieldDiecost386DX20.90$9001.04336071%$4486DX230.80$12001.08118154%$12PowerPC60140.80$17001.312111528%$53HPPA710030.80$13001.01966627%$73DECAlpha30.70$15001.22345319%$149SuperSparc30.70$17001.62564813%$272Pentium30.80$15001.5296409%$417321.3.2功能性和穩(wěn)定性為什麼一個(gè)製造出來(lái)的電路所測(cè)得的行為特性通常都會(huì)與預(yù)期的回應(yīng)有差別？原因1：製造過(guò)程導(dǎo)致的差異每個(gè)生產(chǎn)批次之間、甚至同一圓片或晶片上器件的尺寸和參數(shù)都會(huì)有所不同。原因2：晶片上或晶片外存在的干擾雜訊。如電源雜訊、並排放置導(dǎo)線間的串?dāng)_雜訊33數(shù)字積體電路中的雜訊i(t)電感耦合電容耦合電源線和地線雜訊v(t)VDD34串?dāng)_雜訊Crosstalkvs.Technology0.16mCMOS0.12mCMOS0.35mCMOS0.25mCMOSPulsedSignalBlacklinequietRedlinespulsedGlitchesstrengthvstechnology35

電壓傳輸特性V(x)V(y)VOHVOLVM

VOHVOLfV(y)=V(x)SwitchingThresholdNominalVoltageLevelsVOH=f(VOL)VOL=f(VOH)VM=f(VM)36邏輯電平映射至電壓範(fàn)圍VILVIHVin斜率=-1斜率=-1VOLVOHVout“0”VOLVILVIHVOH不確定區(qū)“1”37雜訊容限NoisemarginhighNoisemarginlowVIH

VIL不確定區(qū)"1""0"VOH

VOLNMHNML門輸出門輸入38再生性條件39再生性條件40扇入與扇出

41理想傳輸門Ri=￥Ro=0Fanout=￥NMH=NML=VDD/2

g

=

VinVout42老式反相器43傳播延時(shí)44環(huán)振45一階RC網(wǎng)路voutvinCRtp=ln(2)t=0.69RCImportantmodel–matchesdelayofinverter

46功耗Instantaneouspower: p(t)=v(t)i(t)=Vsupplyi(t)Peakpower: Ppeak=VsupplyipeakAveragepower:47能量and能量延時(shí)Power-DelayProduct(PDP)=

E=Energyperoperation=Pav

tp

Energy-DelayProduct(EDP)=

qualitymetricofgate=Etp

482.2製造工藝概述

CMOS工藝過(guò)程49現(xiàn)代CMOS工藝過(guò)程現(xiàn)代雙阱CMOS工藝的截面圖

50設(shè)計(jì)電路51版圖52氧化光照掩模工藝步驟塗光刻膠

去除光刻膠（沙洗）旋轉(zhuǎn)、清洗、乾燥酸刻蝕

光刻機(jī)曝光光刻膠顯影一個(gè)光刻過(guò)程的典型操作步驟（摘自［Fullman99］）

光刻過(guò)程53形成SiO2圖形的工藝步驟Si襯底Si襯底Si襯底(a)矽基礎(chǔ)材料(b)氧化及澱積負(fù)光刻膠後

(c)光刻機(jī)曝光

光刻膠SiO2紫外光圖形的光照掩膜曝光的光刻膠SiO2Si襯底Si襯底Si襯底SiO2SiO2(d)顯影和刻蝕光刻膠後化學(xué)或等離子刻蝕SiO2(e)刻蝕後、(f)去除光刻膠後的最終結(jié)果

變硬的光刻膠變硬的化學(xué)或等離子刻蝕54雙阱CMOS工藝中製造NMOS管和PMOS管的工藝流程

p+P外延(a)基礎(chǔ)材料：p+襯底及p外延層

p+(c)採(cǎi)用有源區(qū)掩?；パa(bǔ)區(qū)進(jìn)行等離子刻蝕絕緣溝槽後p+P外延SiO23SiN4(b)澱積柵氧和氮化矽犧牲層（作為緩衝層）後55雙阱CMOS工藝中製造NMOS管和PMOS管的工藝流程SiO2(d)溝槽填充氧化物、CMP平整化及移去氮化矽犧牲層後

(e)n阱和VTP調(diào)整的離子注入

n(f)p阱和VTn調(diào)整的離子注入

p56雙阱CMOS工藝中製造NMOS管和PMOS管的工藝流程(g)多晶矽澱積與刻蝕後

poly(silicon)(h)n+源/漏及p+源/漏注入後。這些步驟也摻雜多晶矽n

p+n+(i)SiO2絕緣層澱積及接觸孔刻蝕後

SiO257雙阱CMOS工藝中製造NMOS管和PMOS管的工藝流程(j)第一層Al澱積及圖形形成後

Al(k)SiO2絕緣層澱積、通孔刻蝕及第二層Al澱積和圖形形成後AlSiO258高級(jí)鍍金屬法59高級(jí)鍍金屬法602.3設(shè)計(jì)規(guī)則613D透視圖PolysiliconAluminum62設(shè)計(jì)規(guī)則設(shè)計(jì)規(guī)則是電路設(shè)計(jì)者和工藝工程師之間的介面設(shè)計(jì)規(guī)則是製造各種掩膜的指南單元尺寸:最小線寬scalabledesignrules:lambdaparameterabsolutedimensions(micronrules)63CMOSProcessLayersLayerPolysiliconMetal1Metal2ContactToPolyContactToDiffusionViaWell(p,n)ActiveArea(n+,p+)ColorRepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect(p+,n+)Green64Layersin0.25mmCMOSprocess65Intra-Layer設(shè)計(jì)規(guī)則Metal24366電晶體版圖67通孔和接觸孔68選擇層69CMOS反相器版圖70版圖編輯器圖A.1max版圖工具的顯示窗口。窗口中畫(huà)出了兩個(gè)堆疊NMOS電晶體的版圖。窗口左邊的菜單可用來(lái)選擇一個(gè)工藝層，使一個(gè)具體的多邊形可以放在這個(gè)工藝層上71設(shè)計(jì)規(guī)則檢查poly_not_fettoall_diffminimumspacing=0.14um.72棍棒圖13InOutVDDGNDCMOS反相器的棍棒圖。數(shù)字代表電晶體的寬長(zhǎng)比

DimensionlesslayoutentitiesOnlytopologyisimportantFinallayoutgeneratedby

“compaction”program732.4封裝74封裝要求電氣要求:低參數(shù)機(jī)械特性:可靠性和牢固性熱特性:散熱率越高越好低成本:價(jià)格低75壓焊技術(shù)76載帶自動(dòng)壓焊（TAB）

77倒裝焊

78印刷版安裝方法79封裝類型1裸晶片2雙列直插（DIP）3針柵陣列（PGA）4小外廓IC（SOIC）5方形扁平封裝（QFP）6引線塑封晶片載體（PLCC）7無(wú)引線載體（LCC）80封裝參數(shù)二極體耗盡層二極體電流特性正向偏置TypicallyavoidedinDigitalICs反向偏置TheDominantOperationMode手工分析模型結(jié)電容擴(kuò)散電容二次效應(yīng)二極體SPICE模型SPICE參數(shù)什麼是電晶體？ASwitch!|VGS|AnMOSTransistorMOS電晶體PolysiliconAluminumMOS電晶體-

類型和特征閾值電壓:概念閾值電壓體偏置影響I-V特性QuadraticRelationship00.511.522.50123456x10-4VDS(V)ID(A)VGS=2.5VVGS=2.0VVGS=1.5VVGS=1.0VResistiveSaturationVDS=VGS-VT線性區(qū)下的電晶體飽和區(qū)下電晶體電流-電壓關(guān)係

長(zhǎng)溝道器件手工分析模型電流-電壓關(guān)係

深亞微米級(jí)線性關(guān)係-4VDS(V)00.511.522.500.511.522.5x10ID(A)VGS=2.5VVGS=2.0VVGS=1.5VVGS=1.0V早期飽和速度飽和結(jié)論ID、

VGS關(guān)係ID、

VGS關(guān)係手工分析的標(biāo)準(zhǔn)模型SDGBMOS管簡(jiǎn)單SPICE模型PMOS電晶體用於手工分析的電晶體模型開(kāi)關(guān)模型電晶體開(kāi)關(guān)模型電晶體開(kāi)關(guān)模型電晶體MOS動(dòng)態(tài)電容特性MOS電晶體動(dòng)態(tài)特性溝道電容溝道電容Cut-offResistiveSaturationMostimportantregionsindigitaldesign:saturationandcut-off溝道電容測(cè)量溝道尺寸擴(kuò)散電容結(jié)電容線性化結(jié)電容Replacenon-linearcapacitancebylarge-signalequivalentlinearcapacitancewhichdisplacesequalchargeovervoltageswingofinterest0.25mmCMOS電容參數(shù)深亞微米級(jí)MOS電晶體ThresholdVariationsSubthresholdConductionParasiticResistances閾值變化Sub-ThresholdConduction00.511.522.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypicalvaluesforS:60..100mV/decadeTheSlopeFactorSisDVGSforID2/ID1=10Sub-ThresholdIDvsVGSVDSfrom0to0.5VSub-ThresholdIDvsVDSVGSfrom0to0.3VMOSFET工作區(qū)域小結(jié)StrongInversionVGS>

VTLinear(Resistive)VDS<

VDSATSaturated(ConstantCurrent)VDS

VDSATWeakInversion(Sub-Threshold)VGS

VTExponentialinVGSwithlinearVDSdependence寄生電阻閂鎖效應(yīng)133導(dǎo)線134片上互連影響135導(dǎo)線模型136互連寄生效應(yīng)的影響InterconnectparasiticsreducereliabilityaffectperformanceandpowerconsumptionClassesofparasiticsCapacitiveResistiveInductive137互連特性GlobalInterconnectSLocal=STechnologySGlobal=SDieSource:Intel138互連Capacitance139互連電容140電容:平行板模型141介電常數(shù)142邊緣場(chǎng)電容143平行板的邊緣效應(yīng)144電容耦合145電容耦合的影響146導(dǎo)線電容(0.25mmCMOS)147互連Resistance148互連電阻149互連電阻150DealingwithResistanceSelectiveTechnologyScalingUseBetterInterconnectMaterialsreduceaveragewire-lengthe.g.copper,silicidesMoreInterconnectLayersreduceaveragewire-length151矽化物多晶柵MOSFETn+n+SiO2多晶矽矽化物p矽化物多晶柵MOSFET152薄層電阻153現(xiàn)代互連154例:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric155互連Inductance156互連模型157集總模型158分佈RC模型

Elmore延時(shí)159Ellmore延時(shí)

RC鏈160導(dǎo)線模型Assume:WiremodeledbyNequal-lengthsegmentsForlargevaluesofN:161分佈rc線Thediffusionequation162RC導(dǎo)線的階躍回應(yīng)與時(shí)間及位置的關(guān)係163RC模型計(jì)算VIHandVIL反相器增益VDD產(chǎn)生的增益VTC模擬器件參數(shù)變化的影響00.511.522.500.511.522.5Vin(V)Vout(V)GoodPMOSBadNMOSGoodNMOSBadPMOSNominal傳播延時(shí)CMOS反相器傳播延時(shí)

1階分析CMOS反相器傳播延時(shí)

2階分析CMOS反相器多晶矽InOut金屬1VDDGNDPMOSNMOS1.2mm=2l瞬態(tài)回應(yīng)tp=0.69CL(Reqn+Reqp)/2?tpLHtpHL功能設(shè)計(jì)保持小電容增加電晶體尺寸注意self-loading!增加VDD(????)VDD對(duì)延時(shí)的影響注意：這一公式只在器件速度飽和時(shí)成立，因此在低電源電壓會(huì)有偏差。器件尺寸NMOS/PMOS尺寸係數(shù)b=Wp/Wn上升時(shí)間對(duì)延時(shí)的影響反相器尺寸反相器鏈CLIfCLisgiven:Howmanystagesareneededtominimizethedelay?Howtosizetheinverters?Mayneedsomeadditionalconstraints.InOut反響器延時(shí)

Minimumlengthdevices,L=0.25mmAssumethatforWP=2WN=2Wsamepull-upandpull-downcurrentsapprox.equalresistancesRN=RPapprox.equalrisetpLHandfalltpHLdelaysAnalyzeasanRCnetworktpHL=(ln2)RNCLtpLH=(ln2)RPCLDelay(D):2WWLoadforthenextstage:帶負(fù)載的反相器Load(CL)DelayAssumptions:noload->zerodelayCLtp=k

RWCLRWRWWunit=1kisaconstant,equalto0.69帶負(fù)載的反相器LoadDelayCintCLDelay=kRW(Cint+CL)=kRWCint+kRWCL=kRWCint(1+CL/Cint)=Delay(Internal)+Delay(Load)CN=CunitCP=2Cunit2WW延時(shí)公式Cint=gCginwith

g

1f=CL/Cgin

-effectivefanoutR=Runit/W;Cint=WCunittp0=0.69RunitCunit反相器鏈的應(yīng)用CLInOut12Ntp=tp1+tp2+…+tpN最佳給定尖端N值DelayequationhasN-1unknowns,Cgin,2–Cgin,NMinimizethedelay,findN-1partialderivativesResult:Cgin,j+1/Cgin,j=Cgin,j/Cgin,j-1Sizeofeachstageisthegeometricmeanoftwoneighborseachstagehasthesameeffectivefanout(Cout/Cin)eachstagehasthesamedelay最佳延時(shí)Wheneachstageissizedbyfandhassameeff.fanoutf:MinimumpathdelayEffectivefanoutofeachstage:例CL=8C1InOutC11ff2CL/C1hastobeevenlydistributedacrossN=3stages:最佳階段數(shù)量Foragivenload,CLandgiveninputcapacitanceCinFindoptimalsizingfForg=0,f=e,N=lnF最佳有效扇出fOptimumfforgivenprocessdefinedbygfopt=3.6for

g=1自載對(duì)tp的影響NoSelf-Loading,g=0WithSelf-Loadingg=1不同驅(qū)動(dòng)器結(jié)構(gòu)與F的關(guān)係緩衝器設(shè)計(jì)111186464646442.881622.6N f tp1 64 652 8 183 4 154 2.8 15.3功耗CMOS的功耗產(chǎn)生來(lái)源?動(dòng)態(tài)功耗Energy/transition=CL*Vdd2Power=Energy/transition*f=CL*Vdd2

*f減小CL,Vdd,和f來(lái)降低能量.VinVoutCLVdd與電晶體尺寸無(wú)關(guān)為減小擺幅而進(jìn)行的電路修正絕熱裝置222AdiabaticCharging節(jié)點(diǎn)轉(zhuǎn)換和功耗最小能量的電晶體尺寸Goal:MinimizeEnergyofwholecircuitDesignparameters:fandVDDtp

tprefofcircuitwithf=1andVDD=Vref電晶體尺寸(2)PerformanceConstraint(g=1)EnergyforsingleTransition電晶體尺寸(3)短路電流怎麼保持較低短路電流？Shortcircuitcurrentgoestozeroiftfall>>trise,butcan’tdothisforcascadelogic,so...最小化短路電流功耗Vdd=1.5Vdd=2.5Vdd=3.3洩漏電流反偏漏二極體JS=10-100pA/mm2at25degCfor0.25mmCMOSJSdoublesforevery9degC!SubthresholdLeakageComponent靜態(tài)功耗Wastedenergy…Shouldbeavoidedinalmostallcases,butcouldhelpreducingenergyinothers(e.g.senseamps)減小功耗的方法首要選擇:減小電壓!RecentyearshaveseenanaccelerationinsupplyvoltagereductionDesignatverylowvoltagesstillopenquestion(0.6…0.9Vby2010!)減小開(kāi)關(guān)電流減小物理電容DeviceSizing:forF=20fopt(energy)=3.53,fopt(performance)=4.47工藝尺寸

縮小的影響工藝尺寸縮小的目的更為廉價(jià):用同樣一個(gè)片所需的錢賣出更多的電晶體把同樣的產(chǎn)品做得更便宜電晶體的價(jià)格降低更快、更小、低功耗工藝尺寸縮小Goalsofscalingthedimensionsby30%:Reducegatedelayby30%(increaseoperatingfrequencyby43%)DoubletransistordensityReduceenergypertransitionby65%(50%powersavings@43%increaseinfrequencyDiesizeusedtoincreaseby14%pergenerationTechnologygenerationspans2-3yearsTechnologyGenerations技術(shù)革命(2000data)InternationalTechnologyRoadmapforSemiconductors18617717116013010690MaxmPpower[W]1.41.26-71.5-1.818019991.71.6-1.46-71.5-1.8200014.9-3.611-37.1-2.53.5-22.1-1.6Maxfrequency[GHz],Local-Global2.52.32.12.42.0Bat.power[W]109-10987Wiringlevels0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply[V]30406090130Technologynode[nm]20142011200820042001YearofIntroductionNodeyears:2007/65nm,2010/45nm,2013/33nm,2016/23nm技術(shù)革命(1999)ITRS工藝尺寸路標(biāo)

繼續(xù)加速工藝尺寸縮小(1)MinimumFeatureSize

工藝尺寸縮小(2)Numberofcomponentsperchip

工藝尺寸縮小(3)PropagationDelay

tp

decreasesby13%/year50%every5years!工藝尺寸縮小(4)FromKuroda工藝尺寸縮小模型

長(zhǎng)溝器件的尺寸縮小情況

電晶體縮小比例mProcessorScalingP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC2001mProcessorPowerP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC2001mProcessorPerformanceP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC20012010展望Performance2X/16months1TIP(terrainstructions/s)30GHzclockSizeNooftransistors:2BillionDie:40*40mmPower10kW!!Leakage:1/3activePowerP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC2001230組合邏輯和時(shí)序邏輯Output=f(In)Output=f(In,PreviousIn)231靜態(tài)CMOS電路Ateverypointintime(exceptduringtheswitchingtransients)eachgateoutputisconnectedtoeither

VDD

or

Vss

viaalow-resistivepath.Theoutputsofthegatesassume

atalltimes

the

valueoftheBooleanfunction,implementedbythecircuit(ignoring,onceagain,thetransienteffectsduringswitchingperiods).Thisisincontrasttothe

dynamic

circuitclass,whichreliesontemporarystorageofsignalvaluesonthecapacitanceofhighimpedancecircuitnodes.232互補(bǔ)CMOSPUNandPDNareduallogicnetworks233NMOS電晶體

串/並聯(lián)TransistorscanbethoughtasaswitchcontrolledbyitsgatesignalNMOSswitchcloseswhenswitchcontrolinputishigh234PMOS電晶體

串/並聯(lián)235ThresholdDropsVDDVDD

0PDN0

VDDCLCLPUNVDD0

VDD-VTnCLVDDVDDVDD

|VTp|CLSDSDVGSSSDDVGS236互補(bǔ)CMOS邏輯類型237ExampleGate:NAND238ExampleGate:NOR239複合門OUT=D+A?(B+C)DABCDABC240構(gòu)建複合門241單元設(shè)計(jì)StandardCellsGeneralpurposelogicCanbesynthesizedSameheight,varyingwidthDatapathCellsForregular,structureddesigns(arithmetic)IncludessomewiringinthecellFixedheightandwidth242標(biāo)準(zhǔn)單元方法–1980ssignalsRoutingchannelVDDGND243標(biāo)準(zhǔn)單元方法–1990sM2NoRoutingchannelsVDDGNDM3VDDGNDMirroredCellMirroredCell244標(biāo)準(zhǔn)單元CellboundaryNWellCellheight12metaltracksMetaltrackisapprox.3

+3

Pitch=

repetitivedistancebetweenobjectsCellheightis“12pitch”2

Rails~10

InOutVDDGND245標(biāo)準(zhǔn)單元InOutVDDGNDInOutVDDGNDWithsilicided

diffusionWithminimal

diffusion

routing246標(biāo)準(zhǔn)單元AOutVDDGNDB2-inputNANDgate247棍棒圖ContainsnodimensionsRepresentsrelativepositionsoftransistorsInOutVDDGNDInverterAOutVDDGNDBNAND2248棍棒圖CABX=C?(A+B)BACijjVDDXXiGNDABCPUNPDNABCLogicGraph249C?(A+B)的二種方法XCABABCXVDDGNDVDDGND250歐拉路徑j(luò)VDDXXiGNDABCABC251OAI22邏輯圖CABX=(A+B)?(C+D)BADVDDXXGNDABCPUNPDNCDDABCD252例:x=ab+cd253多接觸點(diǎn)電晶體OnefingerTwofingers(folded)Lessdiffusioncapacitance254PropertiesofComplementaryCMOSGatesSnapshotHighnoisemargins:VOHandVOL

areatVDD

andGND,respectively.Nostaticpowerconsumption:ThereneverexistsadirectpathbetweenVDD

andVSS(GND)insteady-statemode.Comparableriseandfalltimes:(underappropriatesizingconditions)255CMOS特性Fullrail-to-railswing;highnoisemarginsLogiclevelsnotdependentupontherelativedevicesizes;ratiolessAlwaysapathtoVddorGndinsteadystate;lowoutputimpedanceExtremelyhighinputresistance;nearlyzerosteady-stateinputcurrentNodirectpathsteadystatebetweenpowerandground;nostaticpowerdissipationPropagationdelayfunctionofloadcapacitanceandresistanceoftransistors256開(kāi)關(guān)延時(shí)模型AReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR2257輸入數(shù)據(jù)對(duì)延時(shí)的影響DelayisdependentonthepatternofinputsLowtohightransitionbothinputsgolowdelayis0.69Rp/2CLoneinputgoeslowdelayis0.69RpCLHightolowtransitionbothinputsgohighdelayis0.692RnCLCLBRnARpBRpARnCint258顯示延時(shí)與輸入有關(guān)的例子A=B=10A=1,B=10A=10,B=1時(shí)間[ps]電壓輸入數(shù)據(jù)模式延時(shí)(psec)A=B=0167A=1,B=0164A=01,B=161A=B=1045A=1,B=1080A=10,B=181NMOS=0.5m/0.25mPMOS=0.75m/0.25mCL=100fF259電晶體尺寸

CLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144260複雜CMOS電晶體尺寸確定OUT=D+A?(B+C)DABCDABC122244886366261扇入情況DCBADCBACLC3C2C1

DistributedRCmodel(Elmoredelay)tpHL=0.69Reqn(C1+2C2+3C3+4CL)Propagationdelaydeterioratesrapidlyasafunctionoffan-in–quadraticallyintheworstcase.262傳播延時(shí)和扇入的關(guān)係tpLHtp(psec)fan-inGateswithafan-ingreaterthan4shouldbeavoided.tpHLquadraticlineartp263傳播延時(shí)和扇出的關(guān)係tpNOR2tp(psec)eff.fan-outAllgateshavethesamedrivecurrent.tpNAND2tpINVSlopeisafunctionof“drivingstrength”264傳播延時(shí)和扇入/扇出的關(guān)係扇入:quadraticduetoincreasingresistanceandcapacitance扇出:eachadditionalfan-outgateaddstwogatecapacitancestoCLtp=a1FI+a2FI2+a3FO265高速複雜門:

設(shè)計(jì)技術(shù)1266高速複雜門:

設(shè)計(jì)技術(shù)2電晶體順序調(diào)整267高速複雜門:

設(shè)計(jì)技術(shù)3重組邏輯結(jié)構(gòu)F=ABCDEFGH268高速複雜門:

設(shè)計(jì)技術(shù)4重新安排輸入CLCL269高速複雜門:

設(shè)計(jì)技術(shù)5減小電壓浮動(dòng)linearreductionindelayalsoreducespowerconsumptionButthefollowinggateismuchslower!Orrequiresuseof“senseamplifiers”onthereceivingendtorestorethesignallevel(memorydesign)tpHL=0.69(3/4(CLVDD)/IDSATn)=0.69(3/4(CLVswing)/IDSATn)270SizingLogicPathsforSpeedFrequently,inputcapacitanceofalogicpathisconstrainedLogicalsohastodrivesomecapacitanceExample:ALUloadinanIntel’smicroprocessoris0.5pFHowdowesizetheALUdatapathtoachievemaximumspeed?Wehavealreadysolvedthisfortheinverterchain–canwegeneralizeitforanytypeoflogic?271緩衝器例ForgivenN:Ci+1/Ci=Ci/Ci-1TofindN:Ci+1/Ci~4Howtogeneralizethistoanylogicpath?CLInOut12N(inunitsoftinv)272邏輯努力p–intrinsicdelay(3kRunitCunitg)-gateparameterf(W)g–logicaleffort(kRunitCunit)–gateparameterf(W)f–effectivefanoutNormalizeeverythingtoaninverter:ginv=1,pinv=1Divideeverythingbytinv(everythingismeasuredinunitdelaystinv)Assumeg=1.273邏輯門的延時(shí)Gatedelay:d=h+peffortdelayintrinsicdelayEffortdelay:h=gflogicalefforteffectivefanout=Cout/CinLogicaleffortisafunctionoftopology,independentofsizingEffectivefanout(electricaleffort)isafunctionofload/gatesize274邏輯努力InverterhasthesmallestlogicaleffortandintrinsicdelayofallstaticCMOSgatesLogicaleffortofagatepresentstheratioofitsinputcapacitancetotheinvertercapacitancewhensizedtodeliverthesamecurrentLogicaleffortincreaseswiththegatecomplexity275邏輯努力Logicaleffortistheratioofinputcapacitanceofagatetotheinputcapacitanceofaninverterwiththesameoutputcurrentg=1g=4/3g=5/3276門的邏輯努力Fan-out(h)

Normalizeddelay(d)t1234567pINVtpNANDF(Fan-in)g=p=d=g=p=d=277門的邏輯努力Fan-out(h)

Normalizeddelay(d)t1234567pINVtpNANDF(Fan-in)g=1p=1d=h+1g=4/3p=2d=(4/3)h+2278門的邏輯努力279累加分支努力分支努力:280多級(jí)網(wǎng)路Stageeffort:hi=gifiPathelectricaleffort:F=Cout/CinPathlogicaleffort:G=g1g2…gNBranchingeffort:B=b1b2…bNPatheffort:H=GFBPathdelayD=Sdi=Spi+Shi281每階段最佳努力Wheneachstagebearsthesameeffort:MinimumpathdelayEffectivefanoutofeachstage:Stageefforts:g1f1=g2f2=…=gNfN282階段最佳數(shù)量Foragivenload,andgiveninputcapacitanceofthefirstgateFindoptimalnumberofstagesandoptimalsizingSubstitute‘beststageeffort’283邏輯努力FromSutherland,Sproull284例:最佳路徑Effectivefanout,F=G=H=h=a=b=g=1

f=ag=5/3

f=b/ag=5/3

f=c/bg=1

f=5/c285例:最佳路徑g=1

f=ag=5/3

f=b/ag=5/3

f=c/bg=1

f=5/cEffectivefanout,F=5G=25/9H=125/9=13.9h=1.93a=1.93b=ha/g2=2.23c=hb/g3=5g4/f=2.59286例:最佳路徑Effectivefanout,H=5G=25/9F=125/9=13.9f=1.93a=1.93b=fa/g2=2.23c=fb/g3=5g4/f=2.59g1=1g2=5/3g3=5/3g4=1287例–8輸入AND288邏輯努力的方法Computethepatheffort:F=GBHFindthebestnumberofstagesN~log4FComputethestageeffortf=F1/NSketchthepathwiththisnumberofstagesWorkeitherfromeitherend,findsizes:

Cin=Cout*g/fReference:Sutherland,Sproull,Harris,“LogicalEffort,Morgan-Kaufmann1999.289小結(jié)Sutherland,SproullHarris290有比邏輯291有比邏輯292有比邏輯293有效負(fù)載294偽NMOS295偽NMOSVTC0.00.51.01.52.02.50.00.51.01.52.02.53.0Vin[V]Vout

[V]W/Lp=4W/Lp=2W/Lp=1W/Lp=0.25W/Lp=0.5296改良的負(fù)載297改良的負(fù)載(2)VDDVSSPDN1OutVDDVSSPDN2OutAABBM1M2差分串聯(lián)電壓開(kāi)關(guān)邏輯(DCVSL)298DCVSLExample299DCVSL瞬態(tài)回應(yīng)00.20.40.60.81.0-0.50.51.52.5時(shí)間[ns]Voltage[V]ABABA,BA,B300傳輸管邏輯301傳輸管邏輯302例:AND門303單一NMOS邏輯00.511.520.01.02.03.0時(shí)間[ns]Voltage

[V]xOutIn304單一NMOS開(kāi)關(guān)A=2.5VBC=2.5

VCLA=2.5VC=2.5VBM2M1MnThresholdvoltagelosscausesstaticpowerconsumptionVB

doesnotpullupto2.5V,but2.5V-VTNNMOShashigherthresholdthanPMOS(bodyeffect)305單一NMOS邏輯:

電平恢復(fù)器M2M1MnMrOutABVDDVDD電平恢復(fù)器X?Advantage:FullSwing?Restoreraddscapacitance,takesawaypulldowncurrentatX?Ratioproblem306恢復(fù)尺寸01002003004005000.01.02.0W/Lr=1.0/0.25W/Lr=1.25/0.25W/Lr=1.50/0.25W/Lr=1.75/0.25Voltage[V]時(shí)間[ps]3.0UpperlimitonrestorersizePass-transistorpull-down

canhaveseveraltransistorsin

stack307方法2:零閾值輸出管308互補(bǔ)傳輸電晶體邏輯309Solution3:傳輸門ABCCABCCBCLC

=0VA=2.5VC=2.5V310傳輸門電阻311多路傳輸電晶體GNDVDDIn1In2SSSS312傳輸門XORABFBABBM1M2M3/M4313傳輸門網(wǎng)路延時(shí)V1Vi-1C2.52.500ViVi+1CC2.50Vn-1VnCC2.50InV1ViVi+1CVn-1VnCCInReqReqReqReqCC(a)(b)CReqReqCCReqCCReqReqCCReqCInm(c)314最佳延時(shí)315全加器傳輸門Similardelaysforsumandcarry316動(dòng)態(tài)邏輯317動(dòng)態(tài)邏輯Instaticcircuitsateverypointintime(exceptwhenswitching)theoutputisconnectedtoeitherGNDorVDDviaalowresistancepath.fan-inofnrequires2n(nN-type+nP-type)devicesDynamiccircuitsrelyonthetemporarystorageofsignalvaluesonthecapacitanceofhighimpedancenodes.requiresonn+2(n+1N-type+1P-type)transistors318動(dòng)態(tài)門Twophaseoperation

Precharge(CLK=0)

Evaluate(CLK=1)319動(dòng)態(tài)門In1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwophaseoperation

Precharge(Clk=0)

Evaluate(Clk=1)onoff1offon((AB)+C)320輸出條件Oncetheoutputofadynamicgateisdischarged,itcannotbechargedagainuntilthenextprechargeoperation.Inputstothegatecanmakeatmostonetransitionduringevaluation.Outputcanbeinthehighimpedancestateduringandafterevaluation(PDNoff),stateisstoredonCL321動(dòng)態(tài)傳輸門特性Logi邏輯功能由下拉網(wǎng)絡(luò)實(shí)現(xiàn)。構(gòu)成PDN的過(guò)程與靜態(tài)CMOS完全一樣。Full電晶體的數(shù)目（對(duì)於複雜門）明顯少於靜態(tài)情況：為N+2而不是2N。是無(wú)比邏輯門。動(dòng)態(tài)邏輯門只有動(dòng)態(tài)功耗。理想情況下在VDD和GND之間從不存在任何靜態(tài)電流路徑。但它的總功耗還是可以明顯高於靜態(tài)邏輯門322動(dòng)態(tài)傳輸門特性動(dòng)態(tài)邏輯門具有較快的開(kāi)關(guān)速度，主要有二個(gè)原因。第一個(gè)（明顯的）原因是由於減少了每個(gè)門電晶體的數(shù)目，並且每個(gè)扇入對(duì)首碼只表現(xiàn)一個(gè)負(fù)載電晶體，因而降低了負(fù)載電容，這相當(dāng)與降低了邏輯努力。第二個(gè)原因是動(dòng)態(tài)門沒(méi)有短路電流，並且由下拉器件提供的所有電流都用來(lái)對(duì)負(fù)載電流放電。323動(dòng)態(tài)設(shè)計(jì)問(wèn)題1:

電荷洩漏CLClkClkOutAMpMe漏電來(lái)源CLKVOut預(yù)充電求值動(dòng)態(tài)電路的漏電問(wèn)題324解決辦法CLClkClkMeMpABOutMkp靜態(tài)洩露器補(bǔ)償電荷洩露Keeper325動(dòng)態(tài)設(shè)計(jì)問(wèn)題2:

電荷分享CLClkClkCACBB=0AOutMpMe326電荷分享例CL=50fFClkClkAABBB!BCCOutCa=15fFCc=15fFCb=15fFCd=10fF327電荷分享B=0ClkXCLCaCbAOutMpMaVDDMbClkMe328解決電荷分享的方法ClkClkMeMpABOutMkpClk329動(dòng)態(tài)設(shè)計(jì)問(wèn)題3:

回柵耦合CL1ClkClkB=0A=0Out1MpMeOut2CL2In動(dòng)態(tài)NAND靜態(tài)NAND=1=0