數(shù)字集成電路：時序問題

1數(shù)字集成電路

-電路、系統(tǒng)與設(shè)計時序問題2同步互連3時序

定義4鎖存器參數(shù)DClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT5寄存器參數(shù)DClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions6時鐘不確定性7時鐘非理想化時鐘偏差集成電路中一個時鐘翻轉(zhuǎn)的到達(dá)時間在空間上的差別通常稱為時鐘偏差時鐘抖動指在芯片的某一個定點(diǎn)上的周期發(fā)生暫時的變化周期至周期抖動(短期)tJS長期tJL脈寬的差異性對各種靈敏時鐘很重要8時鐘偏差和抖動偏差和抖動都影響有效時鐘周期只有偏差影響邊緣路徑ClkClktSKtJS9時鐘偏差#ofregistersClkdelayInsertiondelayMaxClkskewEarliestoccurrence

ofClkedgeNominal–

/2Latestoccurrence

ofClkedgeNominal+

/2

10正時鐘偏差和負(fù)時鐘偏差11正時鐘偏差12負(fù)時鐘偏差13時序約束最小周期:T-=tc-q+tsu+tlogic接受沿到達(dá)早就有不好情況發(fā)生(positive)14時序約束維持時間約束:t(c-q,cd)+t(logic,cd)>thold+Worstcaseiswhenreceivingedgearriveslate

Racebetweendataandclock15抖動的影響16最長邏輯路徑

邊緣觸發(fā)系統(tǒng)ClkTTSUTClk-QTLMLatestpoint

oflaunchingEarliestarrival

ofnextcycleTJI+d17時鐘約束

邊緣觸發(fā)系統(tǒng)Iflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:最小周期由通過邏輯的最大延時決定Tc-q+TLM+TSU<T–TJI,1–TJI,2-dTc-q+TLM+TSU+d+2TJI<T偏差是正向或是反向18最短路徑ClkTClk-QTLmEarliestpoint

oflaunchingDatamustnotarrive

beforethistimeClkTHNominal

clockedge19時鐘約束

邊緣觸發(fā)系統(tǒng)最小邏輯延時下降沿早來接受沿晚到:Tc-q+TLM–TJI,1<TH+TJI,2+dTc-q+TLM<TH+2TJI+d20怎樣計算時鐘偏差?21基于觸發(fā)器的時序觸發(fā)器邏輯ff=1f=0觸發(fā)器延時偏差邏輯延時TSUTClk-QRepresentationafter

M.Horowitz,VLSICircuits1996.22觸發(fā)器和動態(tài)邏輯f=1f=0LogicdelayTSUTClk-Qf=1f=0LogicdelayTSUTClk-QPrechargeEvaluateEvaluatePrechargeFlip-flopsareusedonlywithstaticlogic23鎖存器時序DClkQtD-QtClk-QWhendataarrivestotransparentlatchWhendataarrivestoclosedlatchDatahastobe‘re-launched’Latchisa‘soft’barrier24鎖存器的單相時序鎖存器邏輯fClkPPWTsklTsklTsktTskt25基于鎖存器的設(shè)計L1鎖存器邏輯邏輯L2鎖存器f

L1latchistransparent

whenf=0

L2latchistransparent

whenf=126鎖存式時鐘控制27基于鎖存器的時序L1LatchLogicLogicL2Latchff=1f=0L1latchL2latchSkewCantolerateskew!LongpathShortpathStaticlogic28時鐘分配Clockisdistributedinatree-likefashionH-tree29H數(shù)時鐘[Restle98]30網(wǎng)格結(jié)構(gòu)系統(tǒng)31例:DECAlpha211643221164時鐘2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35ns

tskew=150pstcycle=3.3nsClockwaveformLocationofclockdriverondiepre-driverfinaldrivers3334Alpha處理器的時鐘偏差352Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)時鐘600MHz–0.35micronCMOSGlobalclockwaveform3621264時鐘37EV6時鐘分布情況GCLKSkew(atVdd/2Crossings)ps5101520253035404550ps300305310315320325330335340345GCLKRiseTimes(20%to80%Extrapolatedto0%to100%)38EV7時鐘層次+widelydisperseddrivers+DLLscompensatestaticandlow-frequencyvariation+dividesdesignandverificationeffort-DLLdesignandverificationisaddedwork+tailoredclocksActiveSkewManagementandMultipleClockDomains

39自定時電路設(shè)計Functionsofclockinsynchronousdesign1)Actsascompletionsignal2)EnsuresthecorrectorderingofeventsTrulyasynchronousdesign2)Orderingofeventsisimplicitinlogic1)CompletionisensuredbycarefultiminganalysisSelf-timeddesign1)Completionensuredbycompletionsignal2)Orderingimposedbyhandshakingprotocol40流水線的同步數(shù)據(jù)通路41自定時的流水線數(shù)據(jù)通路42延時仿真43完成信號的電路44DCVSL的完成信號PDNB0PDNIn1In1In2In2B1StartStartVDDVDDDoneB0B145自定時加法器46利用電流檢測產(chǎn)生完成信號47兩相位握手協(xié)議48單元邏輯–Muller-C單元492相位握手協(xié)議Advantage:FAST-minimal#ofsignalingevents(importantforglobalinterconnect)Disadvantage:edge-sensitive,hasstate50例:自定時FIFO512相位協(xié)議52例From[Horowitz]53例54例55例564相位握手協(xié)議574相位握手協(xié)議58自復(fù)位邏輯59時鐘延時多米諾60同步器-異步接口61同步器和判斷器判斷器:Circuittodecidewhichof2eventsoccurredfirst同步器:Arbiterwithclockfasoneoftheinputs問題:CircuitHAStomakeadecisioninlimitedtime-whichdecisionisnotimportant注意:ItisimpossibletoensurecorrectoperationBut,wecandecreasetheerrorprobabilityattheexpenseofdelay62一個簡單的同步器?在時鐘上升沿進(jìn)行時鐘采樣?鎖存器最終會解決信號估值,但是…會用很多時間!63同步器:輸出變化軌跡64信號斜率的線性近似65例66噪聲的影響Lowamplitudenoisedoesnotinfluencesynchronizationbehavior67典型的同步器用延遲線2相位時鐘電路68串連