第七章-狀態(tài)機(jī)設(shè)計(jì)1

EDA技術(shù)實(shí)用教程第7章有限狀態(tài)機(jī)設(shè)計(jì)7.1一般有限狀態(tài)機(jī)的設(shè)計(jì)7.1.1用戶自定義數(shù)據(jù)類型定義語句TYPE語句用法如下：TYPE數(shù)據(jù)類型名IS數(shù)據(jù)類型定義OF基本數(shù)據(jù)類型;或TYPE數(shù)據(jù)類型名IS數(shù)據(jù)類型定義;以下列出了兩種不同的定義方式：TYPEst1ISARRAY(0TO10

)OFSTD_LOGIC;TYPEweekIS(sun，mon，tue，wed，thu，fri，sat);TYPEPCIbusstate

is(idle,busbusy,write,read);7.1一般有限狀態(tài)機(jī)的設(shè)計(jì)枚舉類型TYPEm_stateIS(st0，st1，st2，st3，st4，st5);SIGNALpresent_state，next_state:m_state;布爾數(shù)據(jù)類型的定義語句是：TYPEBOOLEANIS（FALSE，TRUE）；TYPEmy_logicIS('1'，'Z'，'U'，'0');SIGNALs1:my_logic;s1<='Z';7.1一般有限狀態(tài)機(jī)的設(shè)計(jì)7.1.1用戶自定義數(shù)據(jù)類型定義語句子類型SUBTYPE的語句格式如下：SUBTYPE子類型名IS基本數(shù)據(jù)類型RANGE約束范圍;

SUBTYPEdigitsISINTEGERRANGE0to9;7.1.2為什么要使用狀態(tài)機(jī)7.1一般有限狀態(tài)機(jī)的設(shè)計(jì)

有限狀態(tài)機(jī)克服了純硬件數(shù)字系統(tǒng)順序方式控制不靈活的缺點(diǎn)。

狀態(tài)機(jī)的結(jié)構(gòu)模式相對(duì)簡單。

狀態(tài)機(jī)容易構(gòu)成性能良好的同步時(shí)序邏輯模塊。

狀態(tài)機(jī)的VHDL表述豐富多樣。

在高速運(yùn)算和控制方面，狀態(tài)機(jī)更有其巨大的優(yōu)勢。

就可靠性而言，狀態(tài)機(jī)的優(yōu)勢也是十分明顯的。7.1.3一般有限狀態(tài)機(jī)的設(shè)計(jì)7.1一般有限狀態(tài)機(jī)的設(shè)計(jì)1.說明部分2.主控時(shí)序進(jìn)程ARCHITECTURE...IS

TYPEFSM_STIS(s0，s1，s2，s3);

SIGNAL

current_state,next_state:FSM_ST;...負(fù)責(zé)狀態(tài)機(jī)運(yùn)轉(zhuǎn)和在時(shí)鐘驅(qū)動(dòng)下負(fù)責(zé)狀態(tài)轉(zhuǎn)換的進(jìn)程3.主控組合進(jìn)程7.1.3一般有限狀態(tài)機(jī)的設(shè)計(jì)

主控組合進(jìn)程的任務(wù)是根據(jù)外部輸入的控制信號(hào)（包括來自狀態(tài)機(jī)外部的信號(hào)和來自狀態(tài)機(jī)內(nèi)部其它非主控的組合或時(shí)序進(jìn)程的信號(hào)），或（和）當(dāng)前狀態(tài)的狀態(tài)值確定下一狀態(tài)（next_state）的取向，即next_state的取值內(nèi)容，以及確定對(duì)外輸出或?qū)?nèi)部其它組合或時(shí)序進(jìn)程輸出控制信號(hào)的內(nèi)容。4.輔助進(jìn)程7.1.3一般有限狀態(tài)機(jī)的設(shè)計(jì)圖7-1

一般狀態(tài)機(jī)結(jié)構(gòu)框圖工作示意圖用于配合狀態(tài)機(jī)工作的組合進(jìn)程或時(shí)序進(jìn)程【例7-1】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYs_machineISPORT(clk,reset:INSTD_LOGIC;state_inputs:INSTD_LOGIC_VECTOR(0TO1);comb_outputs:OUTINTEGERRANGE0TO15);ENDs_machine;ARCHITECTUREbehvOFs_machineISTYPEFSM_STIS(s0,s1,s2,s3);SIGNALcurrent_state,next_state:FSM_ST;BEGINREG:PROCESS(reset,clk)BEGINIFreset='1'THENcurrent_state<=s0;ELSIFclk='1'ANDclk'EVENTTHENcurrent_state<=next_state;ENDIF;ENDPROCESS;COM:PROCESS(current_state,state_Inputs)BEGINCASEcurrent_stateISWHENs0=>comb_outputs<=5;IFstate_inputs="00"THENnext_state<=s0;ELSEnext_state<=s1;ENDIF;WHENs1=>comb_outputs<=8;IFstate_inputs="00"THENnext_state<=s1;ELSEnext_state<=s2;ENDIF;WHENs2=>comb_outputs<=12;IFstate_inputs="11"THENnext_state<=s0;ELSEnext_state<=s3;ENDIF;WHENs3=>comb_outputs<=14;IFstate_inputs="11"THENnext_state<=s3;ELSEnext_state<=s0;ENDIF;ENDcase;ENDPROCESS;ENDbehv;圖7-2例7-1狀態(tài)機(jī)的工作時(shí)序圖7.1.3一般有限狀態(tài)機(jī)的設(shè)計(jì)有限狀態(tài)機(jī)finitestatemachine（FSM）狀態(tài)圖statediagram狀態(tài)表statetable7.2Moore型有限狀態(tài)機(jī)的設(shè)計(jì)7.2.1三進(jìn)程有限狀態(tài)機(jī)CE CSRCK12/8A0 工作狀態(tài)

0 X X X X 禁止

X 1 X X X 禁止

1 0 0 X 0 啟動(dòng)12位轉(zhuǎn)換

1 0 0 X 1 啟動(dòng)8位轉(zhuǎn)換

1 0 1 1 X 12位并行輸出有效

1 0 1 0 0 高8位并行輸出有效

1 0 1 0 1 低4位加上尾隨4個(gè)0有效表7-1AD574邏輯控制真值表（X表示任意）7.2.1三進(jìn)程有限狀態(tài)機(jī)圖7-3AD574工作時(shí)序7.2.1三進(jìn)程有限狀態(tài)機(jī)圖7-4AD574工作時(shí)序PROCESSREG時(shí)序進(jìn)程PROCESSCOM組合進(jìn)程PROCESSLATCH鎖存器current_statenext_stateLOCK狀態(tài)機(jī)FSMFPGA/CPLDCLK

CSA0RCK12/8STATUSD[11..0]AD574Q[11..0]模擬信號(hào)輸入采樣數(shù)據(jù)輸出【例7-2】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYAD574ISPORT(D:INSTD_LOGIC_VECTOR(11DOWNTO0);CLK,STATUS:INSTD_LOGIC;--狀態(tài)機(jī)時(shí)鐘CLK，AD574狀態(tài)信號(hào)STATUSLOCK0:OUTSTD_LOGIC;--內(nèi)部鎖存信號(hào)LOCK的測試信號(hào)

CS,A0,RC,K12X8:OUTSTD_LOGIC;--AD574控制信號(hào)

Q:OUTSTD_LOGIC_VECTOR(11DOWNTO0));--鎖存數(shù)據(jù)輸出ENDAD574;ARCHITECTUREbehavOFAD574ISTYPEstatesIS(st0,st1,st2,st3,st4);SIGNALcurrent_state,next_state:states:=st0;SIGNALREGL:STD_LOGIC_VECTOR(11DOWNTO0);SIGNALLOCK:STD_LOGIC;BEGINK12X8<='1';LOCK0<=LOCK;COM1:PROCESS(current_state,STATUS)--決定轉(zhuǎn)換狀態(tài)的進(jìn)程

接下頁7.2.1三進(jìn)程有限狀態(tài)機(jī)BEGINCASEcurrent_stateISWHENst0=>next_state<=st1;WHENst1=>next_state<=st2;WHENst2=>IF(STATUS='1')THENnext_state<=st2;ELSEnext_state<=st3;ENDIF;WHENst3=>next_state<=st4;WHENst4=>next_state<=st0;WHENOTHERS=>next_state<=st0;ENDCASE;ENDPROCESSCOM1;COM2:PROCESS(current_state)--輸出控制信號(hào)的進(jìn)程

BEGINCASEcurrent_stateISWHENst0=>CS<='1';A0<='1';RC<='1';LOCK<='0';--初始化WHENst1=>CS<='0';A0<='0';RC<='0';LOCK<='0';--啟動(dòng)12位轉(zhuǎn)換WHENst2=>CS<='0';A0<='0';RC<='0';LOCK<='0';--等待轉(zhuǎn)換WHENst3=>CS<='0';A0<='0';RC<='1';LOCK<='0';--12位并行輸出有效WHENst4=>CS<='0';A0<='0';RC<='1';LOCK<='1';--鎖存數(shù)據(jù)WHENOTHERS=>CS<='1';A0<='1';RC<='1';LOCK<='0';--其它情況返回初始態(tài)

接下頁接上頁ENDCASE;ENDPROCESSCOM2;REG:PROCESS(CLK)--時(shí)序進(jìn)程

BEGINIF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;ENDIF;ENDPROCESSREG;LATCH1:PROCESS(LOCK)--數(shù)據(jù)鎖存器進(jìn)程

BEGINIFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF;ENDPROCESS;Q<=REGL;ENDbehav;接上頁7.2.1三進(jìn)程有限狀態(tài)機(jī)圖7-6AD574采樣狀態(tài)機(jī)工作時(shí)序單進(jìn)程有限狀態(tài)機(jī)【例7-3】

COM:PROCESS(current_state,STATUS)BEGINCASEcurrent_stateISWHENst0=>next_state<=st1;CS<='1';A0<='1';RC<='1';LOCK<='0';WHENst1=>next_state<=st2;CS<='0';A0<='0';RC<='0';LOCK<='0';WHENst2=>IF(STATUS='1')THENnext_state<=st2;ELSEnext_state<=st3;ENDIF;CS<='0';A0<='0';RC<='0';LOCK<='0';WHENst3=>next_state<=st4;CS<='0';A0<='0';RC<='1';LOCK<='0';WHENst4=>next_state<=st0;CS<='0';A0<='0';RC<='1';LOCK<='1';WHENOTHERS=>next_state<=st0;ENDCASE;ENDPROCESSCOM;7.2.2單進(jìn)程Moore型有限狀態(tài)機(jī)【例7-4】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMOORE1ISPORT(DATAIN:INSTD_LOGIC_VECTOR(1DOWNTO0);CLK,RST:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDMOORE1;ARCHITECTUREbehavOFMOORE1ISTYPEST_TYPEIS(ST0,ST1,ST2,ST3,ST4);SIGNALC_ST:ST_TYPE;BEGINPROCESS(CLK,RST)BEGINIFRST='1'THENC_ST<=ST0;Q<="0000";ELSIFCLK'EVENTANDCLK='1'THEN

接下頁CASEC_STISWHENST0=>IFDATAIN="10"THENC_ST<=ST1;ELSEC_ST<=ST0;ENDIF;Q<="1001";WHENST1=>IFDATAIN="11"THENC_ST<=ST2;ELSEC_ST<=ST1;ENDIF;Q<="0101";WHENST2=>IFDATAIN="01"THENC_ST<=ST3;ELSEC_ST<=ST0;ENDIF;Q<="1100";WHENST3=>IFDATAIN="00"THENC_ST<=ST4;ELSEC_ST<=ST2;ENDIF;Q<="0010";WHENST4=>IFDATAIN="11"THENC_ST<=ST0;ELSEC_ST<=ST3;ENDIF;Q<="1001";WHENOTHERS=>C_ST<=ST0;ENDCASE;ENDIF;ENDPROCESS;ENDbehav;接上頁圖7-7例7-4狀態(tài)機(jī)綜合后的RTL電路模塊圖7.2.2單進(jìn)程Moore型有限狀態(tài)機(jī)7.2.2單進(jìn)程Moore型有限狀態(tài)機(jī)圖7-8例7-4單進(jìn)程狀態(tài)機(jī)工作時(shí)序ARCHITECTUREbehavOFMOORE1ISTYPEST_TYPEIS(ST0,ST1,ST2,ST3,ST4);SIGNALC_ST，N_ST:ST_TYPE;BEGINREG:PROCESS(reset,clk)BEGINIFreset='1'THENC_ST<=sT0;ELSIFclk='1'ANDclk'EVENTTHENC_ST<=N_ST;ENDIF;ENDPROCESS;

PROCESS(CLK,RST)BEGINCASEC_STISWHENST0=>IFDATAIN="10"THENN_ST<=ST1;ELSEN_ST<=ST0;ENDIF;Q<="1001";WHENST1=>IFDATAIN="11"THENN_ST<=ST2;ELSEN_ST<=ST1;ENDIF;Q<="0101";WHENST2=>IFDATAIN="01"THENN_ST<=ST3;ELSEN_ST<=ST0;ENDIF;Q<="1100";WHENST3=>IFDATAIN="00"THENN_ST<=ST4;ELSEN_ST<=ST2;ENDIF;Q<="0010";WHENST4=>IFDATAIN=“11”THENＮ_ST<=ST0;ELSEN_ST<=ST3;ENDIF;Q<="1001";WHENOTHERS=>Ｎ_ST<=ST0;ENDCASE;ENDIF;ENDPROCESS;ENDbehav;7.2.2單進(jìn)程Moore型有限狀態(tài)機(jī)圖7-9對(duì)應(yīng)于例7-4的2進(jìn)程狀態(tài)機(jī)工作時(shí)序圖7.3Mealy型有限狀態(tài)機(jī)的設(shè)計(jì)【例7-5】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMEALY1ISPORT(CLK,DATAIN,RESET:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(4DOWNTO0));ENDMEALY1;ARCHITECTUREbehavOFMEALY1ISTYPEstatesIS(st0,st1,st2,st3,st4);SIGNALSTX:states;BEGINCOMREG:PROCESS(CLK,RESET)BEGIN--決定轉(zhuǎn)換狀態(tài)的進(jìn)程

IFRESET='1'THENSTX<=ST0;ELSIFCLK'EVENTANDCLK='1'THEN

接下頁CASESTXISWHENst0=>IFDATAIN='1'THENSTX<=st1;ENDIF;WHENst1=>IFDATAIN='0'THENSTX<=st2;ENDIF;WHENst2=>IFDATAIN='1'THENSTX<=st3;ENDIF;WHENst3=>IFDATAIN='0'THENSTX<=st4;ENDIF;WHENst4=>IFDATAIN='1'THENSTX<=st0;ENDIF;WHENOTHERS=>STX<=st0;ENDCASE;ENDIF;ENDPROCESSCOMREG;COM1:PROCESS(STX,DATAIN)BEGIN--輸出控制信號(hào)的進(jìn)程

CASESTXISWHENst0=>IFDATAIN='1'THENQ<="10000";ELSEQ<="01010";ENDIF;WHENst1=>IFDATAIN='0'THENQ<="10111";ELSEQ<="10100";ENDIF;WHENst2=>IFDATAIN='1'THENQ<="10101";ELSEQ<="10011";ENDIF;WHENst3=>IFDATAIN='0'THENQ<="11011";ELSEQ<="01001";ENDIF;

WHENst4=>IFDATAIN='1'THENQ<="11101";ELSEQ<="01101";ENDIF;WHENOTHERS=>Q<="00000";ENDCASE;ENDPROCESSCOM1;ENDbehav;接上頁圖7-10例7-5狀態(tài)機(jī)工作時(shí)序圖【例7-6】MEALY2LIBRARYIEEE;--MEALYFSMUSEIEEE.STD_LOGIC_1164.ALL;ENTITYMEALY2ISPORT(CLK,DATAIN,RESET:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(4DOWNTO0));ENDMEALY2;ARCHITECTUREbehavOFMEALY2ISTYPEstatesIS(st0,st1,st2,st3,st4);SIGNALSTX:states;SIGNALQ1:STD_LOGIC_VECTOR(4DOWNTO0);BEGINCOMREG:PROCESS(CLK,RESET)--決定轉(zhuǎn)換狀態(tài)的進(jìn)程

BEGINIFRESET='1'THENSTX<=ST0;ELSIFCLK'EVENTANDCLK='1'THENCASESTXISWHENst0=>IFDATAIN='1'THENSTX<=st1;ENDIF;WHENst1=>IFDATAIN='0'THENSTX<=st2;ENDIF;WHENst2=>IFDATAIN='1'THENSTX<=st3;ENDIF;WHENst3=>IFDATAIN='0'THENSTX<=st4;ENDIF;WHENst4=>IFDATAIN='1'THENSTX<=st0;ENDIF;WHENOTHERS=>STX<=st0;ENDCASE;接下頁ENDIF;ENDPROCESSCOMREG;COM1:PROCESS(STX,DATAIN,CLK)--輸出控制信號(hào)的進(jìn)程

VARIABLEQ2:STD_LOGIC_VECTOR(4DOWNTO0);BEGINCASESTXISWHENst0=>IFDATAIN='1'THENQ2:="10000";ELSEQ2:="01010";ENDIF;WHENst1=>IFDATAIN='0'THENQ2:="10111";ELSEQ2:="10100";ENDIF;WHENst2=>IFDATAIN='1'THENQ2:="10101";ELSEQ2:="10011";ENDIF;WHENst3=>IFDATAIN='0'THENQ2:="11011";ELSEQ2:="01001";ENDIF;WHENst4=>IFDATAIN='1'THENQ2:="11101";ELSEQ2:="01101";ENDIF;WHENOTHERS=>Q2:="00000";ENDCASE;接下頁IFCLK'EVENTANDCLK='1'THENQ1<=Q2;ENDIF;ENDPROCESSCOM1;Q<=Q1;ENDbehav;接上頁圖7-11例7-6狀態(tài)機(jī)工作時(shí)序圖7.4狀態(tài)編碼7.4.1狀態(tài)位直接輸出型編碼

典型應(yīng)用為計(jì)數(shù)器實(shí)現(xiàn)，將狀態(tài)編碼直接輸出作為控制信號(hào)，但要求對(duì)狀態(tài)機(jī)各狀態(tài)的編碼作特殊的選擇，以適應(yīng)控制時(shí)序的要求。又稱為直接輸出型狀態(tài)機(jī)PROCESSREG時(shí)序進(jìn)程PROCESSCOM組合進(jìn)程PROCESSLATCH鎖存器current_statenext_stateLOCK狀態(tài)機(jī)FSMFPGA/CPLDCLK

CSA0RCK12/8STATUSD[11..0]AD574Q[11..0]模擬信號(hào)輸入采樣數(shù)據(jù)輸出每一位的編碼值都賦予了實(shí)際的控制功能，即：CS=current_state（4）；A0=current_state（3）；RC=current_state（2）；LOCK=current_state（1）。表7-2控制信號(hào)狀態(tài)編碼表【例7-7】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYAD574AISPORT(D:INSTD_LOGIC_VECTOR(11DOWNTO0);CLK,STATUS:INSTD_LOGIC;OUT4:OUTSTD_LOGIC_VECTOR(3DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(11DOWNTO0));ENDAD574A;ARCHITECTUREbehavOFAD574AISSIGNALcurrent_state,next_state:STD_LOGIC_VECTOR(4DOWNTO0);CONSTANTst0:STD_LOGIC_VECTOR(4DOWNTO0):="11100";CONSTANTst1:STD_LOGIC_VECTOR(4DOWNTO0):="00001";CONSTANTst2:STD_LOGIC_VECTOR(4DOWNTO0):="00000";CONSTANTst3:STD_LOGIC_VECTOR(4DOWNTO0):="00100";CONSTANTst4:STD_LOGIC_VECTOR(4DOWNTO0):="00110";SIGNALREGL:STD_LOGIC_VECTOR(11DOWNTO0);SIGNALLK:STD_LOGIC;BEGINCOM1:PROCESS(current_state,STATUS)--決定轉(zhuǎn)換狀態(tài)的進(jìn)程

接下頁BEGINCASEcurrent_stateISWHENst0=>next_state<=st1;WHENst1=>next_state<=st2;WHENst2=>IF(STATUS='1')THENnext_state<=st2;ELSEnext_state<=st3;ENDIF;WHENst3=>next_state<=st4;WHENst4=>next_state<=st0;WHENOTHERS=>next_state<=st0;ENDCASE;OUT4<=current_state(4DOWNTO1);ENDPROCESSCOM1;REG:PROCESS(CLK)--時(shí)序進(jìn)程

BEGINIF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;ENDIF;ENDPROCESSREG;LK<=current_state(1);LATCH1:PROCESS(LK)--數(shù)據(jù)鎖存器進(jìn)程

BEGINIFLK='1'ANDLK'EVENTTHENREGL<=D;接下頁ENDIF;ENDPROCESS;Q<=REGL;ENDbehav;接上頁圖7-12例7-7狀態(tài)機(jī)工作時(shí)序圖7.4.2順序編碼表7-3編碼方式【例7-8】...SIGNALCRURRENT_STATE,NEXT_STATE:STD_LOGIC_VECTOR(2DOWNTO0);CONSTANTST0:STD_LOGIC_VECTOR(2DOWNTO0):="000";CONSTANTST1:STD_LOGIC_VECTOR(2DOWNTO0):="001";CONSTANTST2:STD_LOGIC_VECTOR(2DOWNTO0):="010";CONSTANTST3:STD_LOGIC_VECTOR(2DOWNTO0):="011";CONSTANTST4:STD_LOGIC_VECTOR(2DOWNTO0):="100";BEGINCASEcurrent_stateISWHENst0=>next_state<=st1;WHENst1=>next_state<=st2;WHENst2=>IF(STATUS='1')THENnext_state<=st2;ELSEnext_state<=st3;ENDIF;WHENst3=>next_state<=st4;WHENst4=>next_state<=st0;WHENOTHERS=>next_state<=st0;ENDCASE;ENDPROCESSCOM1;COM2:PROCESS(current_state)--輸出控制信號(hào)的進(jìn)程

BEGINCASEcurrent_stateISWHENst0=>CS<='1';A0<='1';RC<='1';LOCK<='0';--初始化WHENst1=>CS<='0';A0<='0';RC<='0';LOCK<='0';--啟動(dòng)12位轉(zhuǎn)換WHENst2=>CS<='0';A0<='0';RC<='0';LOCK<='0';--等待轉(zhuǎn)換WHENst3=>CS<='0';A0<='0';RC<='1';LOCK<='0';--12位并行輸出有效WHENst4=>CS<='0';A0<='0';RC<='1';LOCK<='1';--鎖存數(shù)據(jù)WHENOTHERS=>CS<='1';A0<='1';RC<='1';LOCK<='0';--其它情況返回初始態(tài)

接下頁ENDCASE;ENDPROCESSCOM2;REG:PROCESS(CLK)--時(shí)序進(jìn)程

BEGINIF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;ENDIF;ENDPROCESSREG;LATCH1:PROCESS(LOCK)--數(shù)據(jù)鎖存器進(jìn)程

BEGINIFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF;ENDPROCESS;Q<=REGL;ENDbehav;7.4.3一位熱碼編碼（One-hotencoding）一位熱碼編碼方式就是用n個(gè)觸發(fā)器來實(shí)現(xiàn)具有n個(gè)狀態(tài)的狀態(tài)機(jī)，狀態(tài)機(jī)中的每一個(gè)狀態(tài)都由其中一個(gè)觸發(fā)器的狀態(tài)表示。圖7-13一位熱碼編碼方式選擇窗狀態(tài)機(jī)編碼方式設(shè)置7.5狀態(tài)機(jī)剩余狀態(tài)處理未被定義的編碼組合，稱為非法狀態(tài)。采用容錯(cuò)技術(shù)對(duì)非法狀態(tài)進(jìn)行處理，基本步驟為：1）首先確定非法狀態(tài)的數(shù)目2）在枚舉類型中定義這個(gè)非法狀態(tài)3）定義轉(zhuǎn)移出非法狀態(tài)的代碼采用狀態(tài)設(shè)置Whenst_ilg1=>next_state<=st0;Whenst_ilg2=>nect_state<=st1;……【例7-9】采用Others語句...TYPEstatesIS(st0,st1,st2,st3，st4，st_ilg1，st_ilg2，st_ilg3);SIGNALcurrent_state,next_state:states;...COM：PROCESS(current_state,state_Inputs)--組合邏輯進(jìn)程BEGINCASEcurrent_stateIS--確定當(dāng)前狀態(tài)的狀態(tài)值...

WHENOTHERS=>next_state<=st0;ENDcase;【例7-10】采用一位熱碼編碼時(shí)...alarm<=(st0AND(st1ORst2ORst3ORst4ORst5))OR(st1AND(st0ORst2ORst3ORst4ORst5))OR(st2AND(st0ORst1ORst3ORst4ORst5))OR(st3AND(st0ORst1ORst2ORst4ORst5))OR(st4AND(st0ORst1ORst2ORst3ORst5))OR(st5AND(st0ORst1ORst2ORst3ORst4));7.6.1AD采樣系統(tǒng)頂層電路設(shè)計(jì)圖ADC0809采樣電路系統(tǒng)7.6LPM模塊的VHDL文本方式調(diào)用7.6.2編輯定制LPM_RAM模塊利用LPM模塊LPM_RAM生成元件的方法1選菜單file—Megawizardpluginmanager,選擇“createanew….”2選擇模塊，鍵入文件名3選擇數(shù)據(jù)寬度，地址線寬度4選擇初始配置5完成定制【例】

LIBRARYieee;USEieee.std_logic_1164.all;ENTITYRAM9ISPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);--8位地址輸入

inclock:INSTD_LOGIC;--數(shù)據(jù)寫入時(shí)鐘

we:INSTD_LOGIC;--寫允許信號(hào)

data:INSTD_LOGIC_VECTOR(7DOWNTO0);--8位寫入數(shù)據(jù)q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位RAM數(shù)據(jù)輸出ENDRAM1;ARCHITECTURESYNOFRAM1ISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTlpm_ram_dqGENERIC(lpm_width:NATURAL;--類屬RAM數(shù)據(jù)寬度自然數(shù)數(shù)據(jù)類型

lpm_widthad:NATURAL;--類屬RAM地址線位寬自然數(shù)數(shù)據(jù)類型

lpm_indata,lpm_address_control,lpm_outdata,lpm_hint:STRING);PORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);

we,inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0);data:INSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;接下頁BEGINq<=sub_wire0(7DOWNTO0);

lpm_ram_dq_component:lpm_ram_dqGENERICMAP--類屬映射語句(LPM_WIDTH=>8,--8位數(shù)據(jù)寬度自然數(shù)數(shù)據(jù)類型

LPM_WIDTHAD=>8,--8位地址線寬度自然數(shù)數(shù)據(jù)類型

LPM_INDATA=>"REGISTERED",--寄存器鎖存方式寫入數(shù)據(jù)，字符串?dāng)?shù)據(jù)類型

LPM_ADDRESS_CONTROL=>"REGISTERED",--寄存器鎖存方式寫入地址，字符串?dāng)?shù)據(jù)類型

LPM_OUTDATA=>"UNREGISTERED",--非寄存器鎖存方式輸出數(shù)據(jù)

LPM_HINT=>"USE_EAB=ON")-–允許使用FPGA中的EABPORTMAP(address=>address,inclock=>inclock,data=>data,we=>we,q=>sub_wire0);ENDSYN;接上頁生成的元件圖7.6.3雙口RAM定制讀寫控制RAM7.6.4正弦信號(hào)發(fā)生器設(shè)計(jì)與LPMROM定制1正弦信號(hào)發(fā)生器結(jié)構(gòu)計(jì)數(shù)器正弦波數(shù)據(jù)存儲(chǔ)ROMD/A芯片VHDL頂層設(shè)計(jì)1）計(jì)數(shù)器實(shí)現(xiàn)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount64isport(clk:instd_logic;q:outstd_logic_vector(5downto0));endcount64;architecturearchofcount64issignalm:std_logic_vector(5downto0);begin

process(clk)begin

if(clk'eventandclk='1')thenm<=m+1;endif;q<=m;endprocess;endarch;2）正弦信號(hào)數(shù)據(jù)文件建立sindata.mifwidth=8;depth=64;address_radix=hex;data_radix=dec;contentbegin00:255;01:254;02:252;03:249;04:245;05:239;06:233;07:225;08:217;09:207;0A:197;0B:186;0C:174;0D:162;0E:150;0F:137;10:124;11:112;12:99;13:87;14:75;15:64;16:53;17:43;18:34;19:26;1A:19;1B:13;1C:8;1D:4;1E:1;1F:0;20:0;21:1;22:4;23:8;24:13;25:19;26:26;27:34;28:43;29:53;2A:64;2B:75;2C:87;2D:99;2E:112;2F:124;30:137;31:150;32:162;33:174;34:186;35:197;36:207;37:217;38:225;39:233;3A:239;3B:245;3C:249;3D:252;3E:254;2F:255;end;正弦波發(fā)生器模塊3)頂層設(shè)計(jì)原理圖輸入文本輸入libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitysingtisport(clk:instd_logic;q:outstd_logic_vector(7downto0));end;architecturearchofsingtiscomponentsinwaveport(address:instd_logic_vector(5downto0);

inclock:instd_logic;q:outstd_logic_vector(7downto0));endcomponent;signalq1:std_logic_vector(5downto0);begin

process(clk)begin

if(clk'eventandclk='1')thenq1<=q1+1;endif;endprocess;u1:sinwaveportmap(address=>q1,q=>q,inclock=>clk);end;7.6.5編輯定制LPM_FIFO模塊圖生成或修改一定制的巨功能塊選擇LPM巨功能塊編輯器選擇建立一個(gè)巨功能塊最后按鍵NEXT圖用VHDL定制LPM_FIFO，文件名：fifo2.vhd選擇功能塊類型選擇建立FIFO功能塊選擇巨功能表達(dá)語言為VHDL在選定的目錄中確定生成的功能塊的文件名：fifo2.vhd圖選擇FIFO數(shù)據(jù)位寬為8，深度為512圖fifo端口設(shè)置選擇含溢出標(biāo)志輸出含異步清零圖選擇在讀請(qǐng)求信號(hào)有效后數(shù)據(jù)輸出選擇同步工作模式圖選擇Area優(yōu)化方式選擇優(yōu)化方式選擇使用EAB設(shè)計(jì)fifo圖單擊“Finish”后完成fifo2.vhd的定制

LPM_FIFO定制文件仿真測試將編制好的輸出文件設(shè)置成工程打開文件原文件選目標(biāo)器件LPM_FIFO定制文件仿真測試【例】

LIBRARYieee;USEieee.std_logic_1164.all;ENTITYfifo2ISPORT(data:INSTD_LOGIC_VECTOR(7DOWNTO0);--輸入數(shù)據(jù)

wrreq:INSTD_LOGIC;--寫入請(qǐng)求

rdreq:INSTD_LOGIC;--讀出請(qǐng)求

clock:INSTD_LOGIC;--工作時(shí)鐘

aclr:INSTD_LOGIC;--異步清0

q:OUTSTD_LOGIC_VECTOR(7DOWNTO0);--數(shù)據(jù)輸出

full:OUTSTD_LOGIC);--溢出標(biāo)志ENDfifo2;ARCHITECTURESYNOFfifo2ISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALsub_wire1:STD_LOGIC;COMPONENTlpm_fifo--調(diào)用LPM_FIFO聲明

GENERIC(lpm_width:NATURAL;--類屬數(shù)據(jù)寬度自然數(shù)數(shù)據(jù)類型

lpm_numwords:NATURAL;--類屬數(shù)據(jù)深度自然數(shù)數(shù)據(jù)類型

接下頁lpm_w