數(shù)字系統(tǒng)設(shè)計(jì) - 驗(yàn)證與測試

1講義第九章驗(yàn)證與測試29.1引言系統(tǒng)可測性設(shè)計(jì)（designfortestability，DFT）DFT是整個(gè)設(shè)計(jì)過程一個(gè)非常重要的組成部分在設(shè)計(jì)流程中需要盡早考慮如果你不測試它，系統(tǒng)很可能不工作DFT策略提供必要的電路以使測試過程快速且全面提供測試激勵(lì)矢量測試過程需要的降低成本希望測試序列盡可能短但仍能覆蓋大部分可能存在的缺陷。39.2生產(chǎn)測試過程診斷測試

芯片和板級調(diào)試期間識別和指出失效的部位對于給定的失效部件

功能測試確定一個(gè)制造出的元件是否能工作。每一個(gè)制造出來的芯片都要經(jīng)過這一測試直接的影響芯片成本測試盡可能簡單快速參數(shù)測試在各種工作條件（如溫度和電源電壓）下檢查許多非離散參數(shù)，如噪聲容限、傳播延時(shí)和最大時(shí)鐘頻率參數(shù)測試一般分為靜態(tài)和動(dòng)態(tài)測試。 49.2.生產(chǎn)測試過程IntroductionThefabricationprocessisoneofthemostprecisemanufacturingmethodsweknowof,butitisstillnotperfect.Eachtimeachipismade,thereisafinitechancethatatleastoneofthemillionsoftransistorsorwireswillhaveanerrorinit.ProductiontestSinceusersofthechipsassumethatthechipisfunction,weneedtohavesomemethodtosortoutthefunctionchipsfromthebadones.acriticalpartofmanufacturinDesignfortest.

Giventhecomplexityoftoday’schips,designersneedtoaddfeaturestothechiptomakeproductiontestingpossible.56DesignMethodologyinDetailDesignSpecificationDesignPartitionDesignEntryBehavioralModelingSimulation/FunctionalVerificationPre-SynthesisSign-OffSynthesizeandMapGate-levelNetListPostsynthesisDesignValidationPostsynthesisTimingVerificationTestGenerationandFaultSimulationCellPlacement/ScanInsertation/RoutingVerifyPhysicalandElectricalRulesSynthesizeandMapGate-levelNetListDesignIntegrationAndVerificationDesignSign-Off7一個(gè)典型的生產(chǎn)測試8自動(dòng)測試儀9109.3.可測性設(shè)計(jì)TestingofLogicCircuitsFaultModels故障模型

TestGenerationandCoverageFaultDetectionDesignforTest在設(shè)計(jì)過程的早期考慮測試可能簡化整個(gè)驗(yàn)證過程所有可能的輸入矢量并觀察相應(yīng)的響應(yīng)實(shí)現(xiàn)驗(yàn)證該電路的正確性11FaultModel故障模型Stuck-At固定故障ModelAssumeselectedwires(gateinputoroutput)are“stuckat”固定logicvalue0or1故障Modelscurtainkindsoffabricationflawsthatshortcircuitwirestogroundorpower,orbrokenwiresthatarefloatingWirewstuck-at-0:w/0Wirewstuck-at-1:w/1Oftenassumethereisonlyonefaultatatime—eventhoughinrealcircuitsmultiplesimultaneousfaultsarepossibleandcanmaskeachotherObviouslyaverysimplisticmodel!12FaultModelSimpleexample:Generateatestcasetodetermineifaisstuckat1Try000Ifastuckat1,expecttoseef=0,butsee1insteadw1w2w3a/1bcdf0000see1butshouldbe013FaultModelSimpleexamplew1w2w3abcdfTestw1w2w3000001010011100101110111a/0X

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XFaultDetectedTestSet14ProblemswithFaultModel故障模型Ingeneral,n-inputcircuitsrequiremuchlessthan2ntestinputstocoverallpossiblestuck-at-faultsinthecircuitHowever,thisnumberisusuallystilltoolargeinrealcircuitsforpracticalpurposesFindingminimumtestcoverisanNP-hardproblemtoo（NP難題，non-deterministicpolynomial縮寫）15PathSensitizationWire-at-timetestingtoolaboriousBettertofocusonwiringpaths,enablingmulti-wiretestingatthesametime“Activate”apathsothatchangesinsignalpropagatingalongthepathaffectstheoutput16PathSensitizationSimpleExample:Toactivatethepath,setinputssothatw1caninfluencefE.g.,w2=1,w3=0,w4=1ANDgates:oneinputat1passestheotherinputNORgates:oneinputat0invertstheotherinputTotest:w1setto1shouldgeneratef=0ifpathokfaultsa/0,b/0,c/1causef=1

w1setto0shouldgeneratef=1ifpathokfaultsa/1,b/1,c/0causef=0Onetestcancaptureseveralfaultsatonce!w1w2bfcaw3w410117PathSensitizationGoodnews:onetestchecksforseveralfaultsNumberofpathsmuchsmallerthannumberofwiresStillanimpracticallylargenumberofpathsforlarge-scalecircuitsPathideacanbeusedto“propagate”afaulttotheoutputtoobservethefaultSetinputsandintermediatevaluessoastopassaninternalwiretotheoutputwhilesettinginputstodrivethatinternalwiretoaknownvalueIfpropagatedvalueisn’tasexpected,thenwehavefoundafaultontheisolatedwire18FaultPropagationw1w2bfcgw3w4hkw1w2fw3w4b/001111DD00D19FaultPropagationw1w2bfcgw3w4hkw1w2fDw3w4g/1110000DDD20TreeStructuredCircuitsTotestinputs

stuck-at-0atgivenANDgateSetinputsatothergatestogenerateANDoutputofzeroForceinputsatselectedgatetogenerateaoneIffis1thencircuitok,elsefaultTotestinputs

stuck-at-1atgivenANDgateDriveinputtotestto0,restofinputsdrivento1Othergatesdrivenwithinputsthatforcegatesto0Iffis0thenOK,elsefaultw1w3w4w2w3w4w1w2w3f21TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest111010000000Stuck-at-0022TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest010111110000Stuck-at-0023TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest000101111000Stuck-at-0024TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110100Stuck-at-1125TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110010Stuck-at-1126TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110001Stuck-at-1127TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest101100011100Stuck-at-1128TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest101100011001Stuck-at-1129TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest110011000010Stuck-at-11Anyotherstuck-at-1casescovered?30TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest100101011010Stuck-at-11Anyotherstuck-at-1casescovered?Wasthatcasealreadycovered?31TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest000001101001Stuck-at-11Allinputsstuck-at-1’scoverednow32RandomTestingSofar:deterministictesting(確定性)電路中的同一個(gè)缺陷為許多輸入圖形所覆蓋，檢測出這樣一個(gè)缺陷只需要這些矢量中的一個(gè)，而其他矢量是冗余的。Alternative:randomtestingGeneraterandominputpatternstodistinguishbetweenthecorrectfunctionandthefaultyfunction放寬必須檢測出所有缺陷這一要求可以大大減少矢量的數(shù)目。為此一般的測試過程只要求95-99%的故障覆蓋率。NumberofTestsProbabilityFaultDetectedSmallnumberoftests

hasreasonable

probabilityoffinding

thefault33SequentialTestingDuetoembeddedstateinsideflip-flops,itisdifficulttoemploythesamemethodsaswithcombinationallogic為了測試一個(gè)狀態(tài)機(jī)中一定的故障僅僅應(yīng)用正確的輸入激勵(lì)是不夠的。因?yàn)槭紫缺仨毷惯@個(gè)被測部件處于所希望的狀態(tài)。這需要應(yīng)用一系列的輸入。同時(shí)把電路響應(yīng)傳送到其中的輸出上。測試一個(gè)FSM中的單個(gè)缺陷需要一系列的測試向量。Alternativeapproach:designfortestScanPathtechnique:FFinputspassthroughmultiplexerstagestoallowthemtobeusedinnormalmodeaswellasaspecialtestshiftregistermode在測試過程中把反饋回路斷開，從而把時(shí)序電路變成組合電路。自測試（self-test）34設(shè)計(jì)可測試性的重要特性設(shè)計(jì)可測試性的重要特性高的可控性。只利用輸入引線就可以使一個(gè)電路節(jié)點(diǎn)進(jìn)入某一指定狀態(tài)如果只用一個(gè)輸入向量就可以把一個(gè)節(jié)點(diǎn)帶到任何狀態(tài)，那么容易控制一個(gè)具有低可控性的節(jié)點(diǎn)或電路需要一個(gè)很長的向量序列才能到預(yù)期的狀態(tài)。高可觀察性在輸出引線上觀察一個(gè)節(jié)點(diǎn)的值對于一個(gè)具有高可觀察性的節(jié)點(diǎn)，可以在輸出引線上直接監(jiān)測到它的值一個(gè)低可觀察性的節(jié)點(diǎn)則需要多個(gè)周期才能使的狀態(tài)出現(xiàn)在輸出口上。當(dāng)電路的復(fù)雜性和引線數(shù)目一定時(shí)，一個(gè)可測電路應(yīng)當(dāng)具有較高的可觀察性。專門測試（adhoctest）同應(yīng)用類型相關(guān)集合了一些可用來提高設(shè)計(jì)的可觀察性和可控性的技術(shù)額外的I/O引線為了減少可能需要的額外壓焊塊的數(shù)目，可以采用在同一個(gè)壓焊塊上分路選擇測試信號和功能信號的方法。I/O總線在正常工作期間作為數(shù)據(jù)總線，而在測試期間則用來提供測試圖形和收集響應(yīng)。35DesignforTestabilityBasicideaConvertasequentialcircuitintoacombinationalcircuitControleveryflip-flopcontentObserveeveryflip-flopoutputHow?Connectflip-flopsintooneormoreshiftregistersSCANDesignforTestability(ScanDFT)OtherbenefitsDiagnosis&debugLowcosttestequipment36ScanPathTechnique掃描測試ConfigureFFsintoshiftregistermode(redpath)Scanintestpatternof0sand1sNon-stateinputscanalsobeonthescanpath(thinksynchronousMealyMachine)激勵(lì)向量通過引線ScanIn輸入邏輯模塊Runsystemforoneclockcyclein“normal”mode(blackpath)—nextstatecapturedinscanpath結(jié)果鎖存到寄存器中Returntoshiftregistermodeandshiftoutthecapturedstateandoutputs寄存器中的結(jié)果通過引線ScanOut送出電路并與期望的數(shù)據(jù)進(jìn)行比較。CombinationalLogic串聯(lián)掃描方式激勵(lì)向量37ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFszY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S10000042ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFsNormalw=0Outputz=0,Y1=0,Y2=0ObservezdirectlyzY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S000044ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFsNormalw=0Outputz=0,Y1=0,Y2=0ObservezdirectlyScanoutY1,Y2zY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S00045ScanOperationsScan-in:testpatternshiftedinApplyTestMode=1Numberofclockcyclesappliedinthismode=numberofflip-flopsinscanchain(shiftregister)?Applyprimaryinputs?Capture:combinationallogicresponsetothetestpatterncapturedinflip-flopsApplyTestMode=0,and1ormoreclockcycles?Observeprimaryoutputs?Scan-out:capturedresponseshiftedoutApplyTestMode=1Numberofclockcyclesappliedinthismode=numberofflip-flopsIn·scanchain(shiftregister)46部分掃描并不是設(shè)計(jì)中所有的寄存器都需要掃描

流水線寄存器只是為了提高性能，并不增加電路的新狀態(tài)只需使輸入和輸出寄存器可掃描就可以了47邊界掃描設(shè)計(jì)（boundaryscan）邊界掃描

把一個(gè)板上部件的輸入-輸出引線連接成一條串聯(lián)的掃描鏈在正常工作時(shí)，邊界掃描壓焊塊pads作為正常的輸入-輸出器件在測試模式，向量可以從這些壓焊塊處掃入掃出，從而在部件的邊界上提供可控性和可觀察性?？梢岳酶鞣N控制模塊來測試各個(gè)部件以及板上的互連線。這方法的開銷是要求稍微復(fù)雜一些的輸入-輸出壓焊塊以及一個(gè)附加的片上測試控制器。目前大多數(shù)產(chǎn)品部件都提供邊界掃描。板級測試的邊界掃描方法48邊界掃描鏈邊界掃描鏈由邊界掃描單元串行組成邊界掃描單元能夠完成對電路節(jié)點(diǎn)的控制和觀察功能邊界掃描單元的結(jié)構(gòu)49為了實(shí)現(xiàn)PCB測試，芯片的邊界掃描鏈要求必須在所有的管腳添加邊界掃描單元。對于輸入管腳、兩態(tài)輸出管腳、三態(tài)輸出管腳和雙向管腳，邊界掃描單元添加方式有所不同當(dāng)不實(shí)現(xiàn)INTEST指令時(shí)，輸入管腳的邊界掃描單元只用一個(gè)觀察級的掃描單元即可，當(dāng)需要實(shí)現(xiàn)INTEST指令時(shí)，還必須添加一個(gè)帶控制級的掃描單元。50兩態(tài)的輸出管腳必須添加帶輸出鎖存的邊界掃描單元51三態(tài)輸出管腳除了添加帶輸出鎖存的邊界掃描單元外，還必須在三態(tài)控制信號上也添加一個(gè)帶輸出鎖存的邊界掃描單元雙向邊界掃描單元由一個(gè)三態(tài)輸出掃描單元和一個(gè)只帶觀察級的輸入掃描單元組成52邊界掃描除了在管腳上添加邊界掃描單元外，為了實(shí)現(xiàn)芯片內(nèi)部的電路級可測試性，還必須在內(nèi)部的電路節(jié)點(diǎn)添加掃描單元。掃描單元一般添加在寄存器的位置，用帶掃描功能的寄存器替換設(shè)計(jì)中的所有寄存器，即可實(shí)現(xiàn)全掃描設(shè)計(jì)。全掃描資源消耗很大，同時(shí)掃描鏈過長也使得串行數(shù)據(jù)掃描的速度急劇下降，使得測試速度變慢。需要根據(jù)電路邏輯結(jié)構(gòu)采用部分掃描設(shè)計(jì)。53Built-inSelf-Test(BIST)內(nèi)建測試內(nèi)建自測試讓電路自己生成測試圖形電路自己能夠決定它所得到的測試結(jié)果是否正確TestVectorGeneratorPseudorandom

testswithafeedbackshiftregister窮盡測試，所有可以得到的輸入信號空間，所有可測的故障都會(huì)被檢測到。對于N值較大的電路，通過整個(gè)輸入空間的操作所需要的時(shí)間是無法接受的。

SeedgeneratesasequenceoftestpatternsOutputscombinedusingthesametechniqueGeneratesauniquesignature簽名

thatcanbecheckedtodetermineifthecircuitiscorrectTestVectorGeneratorCircuitUnderTestTestResponseCompressorx0...xn-1P0...Pm-1Signature原則是應(yīng)當(dāng)能得到合理的故障覆蓋率54LinearFeedbackShiftRegisterDQQDQQDQQDQQDQQDQQDQQDQQPSignatureRandomTestPatternInputfrom

circuitundertest由多個(gè)一位的寄存器串聯(lián)構(gòu)成有些輸出被異或（XOR）并反饋回移位寄存器的輸入

把這個(gè)寄存器初始化為一定的種子值就會(huì)產(chǎn)生不同的偽隨機(jī)序列。55LinearFeedbackShiftRegisterStartingwiththepattern1000種子,generates15differentpatternsinsequenceandthenrepeatsPattern0000isano-noDQQDQQDQQDQQx3x2x1x0x3x2x1x0ff10001110011110111110011111011001011101011101001100001111001001000001000001110001……InitialConfiguration56LinearFeedbackShiftRegister響應(yīng)分析器將所生成的響應(yīng)與存放在片上存儲(chǔ)器中的預(yù)期響應(yīng)進(jìn)行比較更經(jīng)濟(jì)的技術(shù)是在對它們進(jìn)行比較之前把這些響應(yīng)進(jìn)行壓縮

Multi-inputCompressor每一個(gè)進(jìn)來的數(shù)據(jù)字被一個(gè)接一個(gè)地與LFSR的內(nèi)容相比較(XOR)。在測試序列結(jié)束時(shí)，LFSR中含有了這個(gè)數(shù)據(jù)序列的簽名或特征字，可以用來與正確電路的特征字進(jìn)行比較。

DQQDQQP3P2DQQP1DQQP0SignatureCircuitUnderTestOutputs改進(jìn)的線性反饋移位寄存器用同一硬件來完成圖形生成和信號分析57TestCompression?BISTbenefitsretained,BISTissuesavoided?MAJORproliferationintheindustry?Exampleconfigurations:n=200,p=k=15;n=500,p=k=20;n=1,000,p=k=5058一位信號流的壓縮簽名分析器響應(yīng)分析器有一個(gè)動(dòng)態(tài)壓縮被測電路輸出的電路以及一個(gè)比較器構(gòu)成。被壓縮的輸出也常常稱為該電路的簽名，而整個(gè)方法稱為簽名分析。這一電路只是計(jì)數(shù)輸入流中0->1和1->0的翻轉(zhuǎn)數(shù)目。這一壓縮并不能保證接收到的序列是正確的，也就是說許多不同的序列可以有相同數(shù)目的翻轉(zhuǎn)。但是翻轉(zhuǎn)數(shù)目不對，電路肯定有錯(cuò)。59TestCompressionAdvantages?Exponentialreduction(50–80X,sometimesevenmore)Testdatavolume,time,pins,testerchannels?Hightestquality?XtoleranceNewX-Compactortechnique–anexampleofcombiningVLSIwithinformationtheory?CommercialATPGtoolcompatibility?Diagnosissupport?Faultmodel&testsetindependence?Verylittleareaoverhead,noextradelay?Easyautomation60CompleteSelf-TestSystemCombinationalCircuitFFsandMuxesMICSICScanoutPRBSGScaninMUXPRBSGNormalInputsRandomTest

SequencesMulti-inputCompressorRandomTest

SequencesSingle-inputCompressor61Built-inLogicBlockObserver(Bilbo)內(nèi)建邏輯塊監(jiān)測器Testgenerationandcompressioninasinglecircuit!M1,M2=11:RegularmodeM1