交通燈控制器課程設(shè)計報告

1、湖南大學(xué)電氣與信息工程學(xué)院本科生課程設(shè)計題目： 交通燈控制器課程： 數(shù)電課程設(shè)計專業(yè)：自動化專業(yè)班級：學(xué)號：姓名：設(shè)計時間： 目錄一、 設(shè)計目的二、 設(shè)計要求三、 設(shè)計原理四、 設(shè)計程序五、設(shè)計心得一、 設(shè)計目的1、用紅、綠、黃三色發(fā)光二極管做信號燈，主干道a為東西向，設(shè)紅、綠、黃三色燈為ar、ag、ay；支干道b喂南北向。三色燈為br、bg、by。2、主干道車輛較多，所以亮綠燈的時間設(shè)為50s；支干道亮綠燈的時間設(shè)為30s。當(dāng)主干道允許通行亮綠燈時則支干道亮紅燈；相反，支干道允許通行亮綠燈時則主干道亮紅燈。每次由綠燈轉(zhuǎn)變?yōu)榧t燈時，其間要亮5s的黃燈作為過渡，以便行駛中的車輛有時間停到禁止線以

2、內(nèi)。3、交通燈正常運行時，用4位數(shù)碼管m1、m2、m3、m4顯示主干道和支干道的倒計時時間，m1、m2顯示主干道在當(dāng)前狀態(tài)剩余時間；m3、m4顯示支干道在當(dāng)前狀態(tài)的剩余時間。4、能實現(xiàn)系統(tǒng)總清0，清0后計數(shù)器由出事狀態(tài)開始計數(shù)。指示燈指示主干道亮綠燈。5、具有一定的擴(kuò)展功能： 它能實現(xiàn)特殊狀態(tài)的功能先死，用開關(guān)s作為特殊信號傳感器，s為1時進(jìn)入特殊狀態(tài)并實現(xiàn)下列特殊狀態(tài)功能： 1）顯示器m1、m2、m3、m4閃爍，即在全0和當(dāng)前計時時間中交替顯示。 2）計數(shù)器停止計數(shù)并保持原來的時間數(shù)據(jù)。 3）東西、南北方向的三色燈全顯示為紅色狀態(tài)。 4）特殊狀態(tài)解除后能繼續(xù)返回正常工作狀態(tài)。 5）進(jìn)入特殊狀

3、態(tài)時，音響電路發(fā)出急促的“嘀嘟”聲，以示警告。二、設(shè)計要求 1、分析設(shè)計任務(wù)，擬定多種設(shè)計方案，根據(jù)當(dāng)時的制作條件，選定其中的一種方案繪制系統(tǒng)框圖和設(shè)計流程。 2、設(shè)計各部分單元電路或編寫vhdl描述程序。計算元器件參數(shù)、確定元器件幸好和數(shù)量，提出元器件清單。 3、安裝調(diào)試硬件電路，或制作以cpld/fpga為基礎(chǔ)的專用集成電路芯片asic。 4、對制作的電路進(jìn)行功能測試，分析各項技術(shù)指標(biāo)；或?qū)υO(shè)計的電路進(jìn)行功能仿真，分析仿真波形。對asic電路做硬件測試或脫機運行。 5、總結(jié)設(shè)計資料，打印包括原理電路（或vhdl描述）、仿真波形的設(shè)計報告，交驗并演示電路裝置三、設(shè)計原理 1、系統(tǒng)設(shè)計原理框圖

4、 交通燈控制器原理框圖如下，包括置數(shù)模塊、主控制器模塊、譯碼器模塊和數(shù)據(jù)選擇器模塊幾個部分。置數(shù)模塊將交通燈的點亮?xí)r間初值預(yù)置到置數(shù)電路中，預(yù)置的具體數(shù)據(jù)則由控制器當(dāng)前的狀態(tài)決定，即點亮不同顏色的燈則置入不同的值。計數(shù)器電路則根據(jù)預(yù)置的初值做減1操作，當(dāng)減到零時則預(yù)置時間到；又使主控制器的狀態(tài)發(fā)生變化，啟動計時電路進(jìn)入下一個狀態(tài)的倒計時。譯碼器模塊將主控制電路的當(dāng)前狀態(tài)譯碼為紅、綠、黃三色信號燈的點亮信號。整個電路的核心是主控制器。南北方向顯示器東西方向顯示器時鐘信號1hz清0（cr）特殊狀態(tài)sbrbybgagayar主控制器十位個位譯碼器譯碼器mux接地計數(shù)器a置數(shù)器a十位個位譯碼器譯碼器m

5、ux接地計數(shù)器b置數(shù)器b分頻器綠 黃 紅 紅 黃 綠交通燈控制器原理框圖2、主控制器 主控制器決定控制電路狀態(tài)變化的順序。主控制器的輸入信號有：控制器目前狀態(tài)s1s0，特殊情況輸入信號s、50s計時時間到信號t50,30s計時時間到信號t30，輸出信號是控制器的次態(tài)z1z0?？芍苯釉O(shè)計為時序電路，也可以先設(shè)計為組合電路后加接觸發(fā)器，下圖是主控電路的框圖。主控制器原理框圖ffc1ffc0s0 z0s1 z1 st30t50 s0s1 st30t50cpclrd qc clrd qc clrz0z1四、設(shè)計程序 library ieee;use ieee.std_logic_1164.all;us

6、e ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity tr_m is port ( rst : in std_logic; clk : in std_logic; s : in std_logic; speak:out std_logic; bcd_out : out std_logic_vector (7 downto 0); bcdout : out std_logic_vector (7 downto 0); led: out std_logic_vector (7 downto 0);end tr_m;arc

7、hitecture behavioral of tr_m istype numstate is (s1gr,s2yr,s3rg,s4ry,s5rr,s6rr);signal state : numstate;signal sbcd_out : std_logic_vector (7 downto 0);constant c1: std_logic_vector (7 downto 0) :=x55;constant c3: std_logic_vector (7 downto 0) :=x35;signal state_tem: numstate;signal sled : std_logic

8、_vector (7 downto 0) ;signal n:std_logic;beginled=sled;process(clk,rst)begin if(rst=1) then n=1; elsif(rising_edge(clk) then if(sbcd_out=x55) then bcd_out=x50; bcdout=x55; elsif sbcd_out=x35 then bcd_out=x35; bcdout=x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_ou

9、t-5; end if; bcdout = sbcd_out; elsif(sled=x21) then bcd_out = sbcd_out; bcdout =x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out = sbcd_out; elsif(sled=x12) then bcd_out = sbcd_out; bcdout = sbcd_out; elsif(sled=x11 and n=1 and s=1) then n=0; bc

10、d_out = x00; bcdout = x00; elsif(sled=x11 and n=0 and s=1) then n=x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out =x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_out-5; end if; bcdout = sbcd_out; else bcd_out =

11、 sbcd_out; bcdout =x0 and sbcd_out(3 downto 0)=x4) then bcdout = sbcd_out-x6-5; else bcdout = sbcd_out-5; end if; bcd_out =x0 and sbcd_out(3 downto 0)=x4) then bcd_out = sbcd_out-x6-5; else bcd_out = sbcd_out-5; end if; bcdout = sbcd_out; else bcd_out = sbcd_out; bcdout = sbcd_out; end if; end if; e

12、nd if;end process;cntproc: process(rst,clk,state_tem)beginif rst=1 then sbcd_out=c1;elsif rising_edge(clk) then if s=1 then sbcd_out=sbcd_out; elsif sbcd_out=1 then if sled=x12 then sbcd_out=c1; elsif sled=x21 then sbcd_out=c3; end if; elsif sbcd_out(3 downto 0)=0 then sbcd_out = sbcd_out-7; else sb

13、cd_out = sbcd_out-1; end if;end if;end process;stateproc: process(rst,clk)begin if rst=1 then state=s1gr; state_tem=s1gr; elsif rising_edge(clk) then if s=1 and n=1 then state=s5rr; elsif s=1 and n=0 then state=s6rr; elsif sled=x11 then state=state_tem; elsif sbcd_out=x06 then if sled=x41 then state

14、=s2yr; state_tem=s2yr; elsif sled=x14 then state=s4ry; state_tem=s4ry; end if; elsif sbcd_out=x01 then if sled=x21 then state=s3rg; state_tem=s3rg; elsif sled=x12 then state=s1gr; state_tem sled=x41; speak sled=x21; speak sled=x14; speak sled=x12; speak sled=x11; speak sled=x11; speak null;end case;

15、end if;end process;end behavioral; - company:- engineer:- create date: 14:56:21 05/13/2012- design name:- module name: jiaotongdeng - behavioral- project name:- target devices:- tool versions:- description:- dependencies:- revision:- revision 0.01 - file created- additional comments:-library ieee;us

16、e ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity jiaotongdeng is port ( clk : in std_logic; rst : in std_logic;

17、s : in std_logic; ar : out std_logic; ag : out std_logic; ay : out std_logic; br : out std_logic; bg : out std_logic; by : out std_logic; bcd_out : out std_logic_vector (7 downto 0); sound : out std_logic);end jiaotongdeng;architecture behavioral of jiaotongdeng istype numstate is (s1gr,s2yr,s3rg,s4

18、ry);signal state: numstate;signal sbcd_out: std_logic_vector (7 downto 0);signal sar : std_logic;signal sag : std_logic;signal say : std_logic;signal sbr : std_logic;signal sbg : std_logic;signal sby : std_logic;signal ssound:std_logic;beginbcd_out=sbcd_out;ar=sar;ag=sag;ay=say;br=sbr;bg=sbg;by=sby;

19、sound=ssound;out_process:process(state,clk,s)beginif s=1 then sar=1; sag=0; say=0; sbr=1; sbg=0; sby=0; ssound=1;elsif rising_edge(clk) then if state=s1gr then sar=0; sag=1; say=0; sbr=1; sbg=0; sby=0; ssound=0; elsif state=s2yr then sar=0; sag=0; say=1; sbr=1; sbg=0; sby=0; ssound=0; elsif state=s3

20、rg then sar=1; sag=0; say=0; sbr=0; sbg=1; sby=0; ssound=0; elsif state=s4ry then sar=1; sag=0; say=0; sbr=0; sbg=0; sby=1; ssound=0; end if;end if;end process;sbcd_process:process(clk,rst,s)beginif s=1 then sbcd_out=sbcd_out;elsif rst=1 then sbcd_out=x55;elsif rising_edge(clk) then if sbcd_out=1 th

21、en if state=s4ry then sbcd_out=x55; elsif state=s2yr then sbcd_out=x35; end if; elsif sbcd_out(3 downto 0)=0 then sbcd_out = sbcd_out-7; else sbcd_out = sbcd_out-1; end if;end if;end process;state_process:process(clk,rst)beginif rst=1 then state=s1gr;elsif rising_edge(clk) then if sbcd_out=x06 then

22、if state=s1gr then state=s2yr; elsif state=s3rg then state=s4ry; end if; elsif sbcd_out=x01 then if state=s2yr then state=s3rg; elsif state=s4ry then state=s1gr; end if; end if;end if;end process;end behavioral; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alarm is

23、port( clk,rst: in std_logic; alarm : in std_logic; div : out std_logic);end alarm;architecture arct of alarm issignal cnt : natural range 0 to 200000 ;signal div_r : std_logic;beginprocess(div_r)begindiv = div_r;end process;process(clk,rst)beginif(rst = 1) then cnt = 0; div_r = 0;elsif(rising_edge(c

24、lk) then if(alarm = 1) then if(cnt = 200000) then div_r = not div_r; cnt = 0; else cnt = cnt + 1; end if; else if(alarm=0) then div_r=0; end if; end if;end if;end process;end arct;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtdlcd is port (cpin,r,busy :in std_logi

25、c; ew,sn :in std_logic_vector(7 downto 0); ewryg,snryg : in std_logic_vector(2 downto 0); clk,rst,strobe,outline : out std_logic; data : out std_logic_vector(7 downto 0); addr : out std_logic_vector(3 downto 0) );end entity ;architecture jgt of jtdlcd is type states is (s0,s1,s2,s3,s4); signal s: st

26、ates; signal lcdpt : integer range 0 to 10; signal cpct : integer range 0 to 65535; signal cp: std_logic; signal ascew,ascsn : std_logic_vector(7 downto 0);beginprocess(cpin,r)beginclk=cpin;if r=1 then cpct=65535;elsif cpin=1 and cpin event then if cpct=0 then cpct=65535;cp=not cp; else cpct=cpct-1;

27、 end if;end if;end process; process(cp,r)beginif r=1 then s=s0;lcdpt=0;rst s=s1;lcdpt=0;rst rst=0;strobe=0; if busy=0 then lcdpt=lcdpt+1; if lcdpt=5 then s=s3; else s s=s1;strobe strobe=0; if busy=0 then if lcdpt=10 then lcdpt=5; else lcdpt=lcdpt+1; end if; s strobe=1;s null; end case;end if; end pr

28、ocess;process(lcdpt)begincase lcdpt iswhen 0 = null;when 1= data=01000101;addr=0101;outline data=01010111;addr=0110;outline data=01010011;addr=1001;outline data=01001110;addr=1010;outlinedata=0011&ew(7 downto 4);addr=0101;outlinedata=0011&ew(3 downto 0);addr=0110;outlinedata=ascew;addr=0100;outlined

29、ata=0011&sn(7 downto 4);addr=1001;outlinedata=0011&sn(3 downto 0);addr=1010;outlinedata=ascsn;addr=1000;outline null;end case;end process;process(ewryg)begincase ewryg iswhen 100 = ascew ascew ascew null;end case;end process;process(snryg)begincase snryg iswhen 100 = ascsn ascsn ascsn null;end case;

30、end process; end architecture jgt;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;- uncomment the following library declaration if using- arithmetic functions with signed or unsigned values-use ieee.numeric_std.all;- uncomment the following libra

31、ry declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity fengmingming_main is port ( clk_1 : in std_logic; clk_2 : in std_logic; s_main : in std_logic; out_cp : out std_logic; clk_main : in std_logic);end fengmingming_main;architecture be

32、havioral of fengmingming_main issignal sjudje_1: std_logic:=0;signal sjudje_2: std_logic:=0;signal scomplete: std_logic:=0;signal sout_cp:std_logic:=0;beginout_cp=sout_cp;process(s_main,clk_main,clk_1,clk_2)begin if s_main=1 and scomplete=0 then if rising_edge(clk_main) then if sjudje_1=0 then sjudj

33、e_1=1; elsif sjudje_2=0 and sjudje_1=1 then sjudje_2=1; elsif sjudje_1=1 and sjudje_2=1 then scomplete=1; sout_cp=0; end if; else sjudje_1=sjudje_1;sjudje_2=sjudje_2;scomplete=scomplete; end if; if sjudje_1=1 and sjudje_2=0 then sout_cp=clk_1; elsif sjudje_2=1 and sjudje_1=1 then sout_cp=clk_2; end

34、if; elsif s_main=0 then scomplete=0;sjudje_1=0;sjudje_2=0; sout_cp=0; end if;end process;end behavioral;- company:- engineer:- create date: 15:25:56 06/25/2012- design name:- module name: freq_div - behavioral- project name:- target devices:- tool versions:- description:- dependencies:- revision:- r

35、evision 0.01 - file created- additional comments:-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following library declaration if using- arithmetic functions with signed or unsigned values-use ieee.numeric_std.all;- uncomment the

36、 following library declaration if instantiating- any xilinx primitives in this code.-library unisim;-use unisim.vcomponents.all;entity freq_div is port ( clkin : in std_logic; rst : in std_logic; alarm : in std_logic; div : out std_logic);end freq_div;architecture behavioral of freq_div istype numst

37、ate is (s0,s1);signal state_curr,state_next:numstate;signal sdiv_1 : std_logic;signal sdiv_2 : std_logic;signal cnt_1 :integer range 0 to 30000;signal cnt_2 :integer range 0 to 30000;-signal t1:integer range 0 to 30000;constant rate_1 :integer :=5000; - 10m/5000 = 2000hzconstant rate_2 :integer :=25

38、000; - 10m/25000 = 400hzconstant freq :integer :=1500000; - 4beginwith state_curr select div = sdiv_1 when s0, sdiv_2 when s1, u when others;wave_1:process(clkin,rst,alarm)begin if rst = 1 then sdiv_1 = 0; else if ( rising_edge(clkin) ) then if ( cnt_1 = rate_1 ) then cnt_1 = 0; sdiv_1 = not sdiv_1; else cnt_1 = cnt_1 + 1; end if; end if; if alarm = 0 then sdiv_1 = 0; end