EDA數(shù)字鐘設(shè)計(jì)

1、數(shù)字鐘程序設(shè)計(jì)本設(shè)計(jì)在實(shí)驗(yàn)箱上驗(yàn)證，使用電路模式7，用動(dòng)態(tài)掃描方式顯示，“ds8使能”開關(guān)上推；動(dòng)態(tài)位掃描時(shí)，時(shí)、分、秒之間間隔點(diǎn)亮；tmode：12/24進(jìn)制模式切換，接鍵8；scan：動(dòng)態(tài)掃描時(shí)鐘信號(hào)，接clock0，跳線選16384hz；minute：分校時(shí)，接鍵1（單脈沖）；hour：小時(shí)時(shí)校時(shí)，接鍵4（單脈沖）；exchge：計(jì)時(shí)/校時(shí)切換，接鍵5；clk:：時(shí)鐘脈沖，接clock2,跳線選1hz；ret：清零，接鍵7（單脈沖）；en：計(jì)數(shù)使能，接鍵3；clk1024：蜂鳴輸入信號(hào)，接clock5,跳線選1024hz；sg6.0：段選信號(hào)，接pio49到pio43；bt7.0：位選信

2、號(hào)，接pio41到pio34；speaker：蜂鳴輸出信號(hào)，接speaker。程序模塊【1】60進(jìn)制模塊cnt60 library ieee; -clk時(shí)鐘輸入，ret清零，en計(jì)數(shù)使能，use ieee.std_logic_1164.all; - cql分或秒的個(gè)位輸出，use ieee.std_logic_unsigned.all; -cqh分或秒的十位輸出,entity cnt60 is - cout1進(jìn)位輸出port (clk,rst,en : in std_logic;cql: out std_logic_vector(3 downto 0);cqh: out std_logic_v

3、ector(3 downto 0);cout1 : out std_logic); -向外部的進(jìn)位end cnt60;architecture behav of cnt60 issignal cqi0: std_logic_vector (3 downto 0);signal cqi1: std_logic_vector (3 downto 0);signal cout0 : std_logic; -低位向高位的進(jìn)位begin process(clk,rst,en) -十進(jìn)制beginif rst=1 then cqi0 0);elsif clkevent and clk=1 thenif e

4、n =1 thenif cqi0 9 then cqi0 =cqi0+1;else cqi0 0);end if;end if;if cqi0 = 9 then cout0 = 1;else cout0=0;end if;end if;end process;cql=cqi0;process(cout0,rst) -六進(jìn)制beginif rst=1 then cqi1 0);elsif cout0event and cout0=1 thenif cqi15 then cqi1=cqi1+1;else cqi10);end if;if cqi1=5 and cqi0=9 then cout1=1

5、;else cout1=0;end if;end if;end process;cqh=cqi1;end behav;【2】24|12進(jìn)制模塊cnt24 library ieee; -clk輸入分的進(jìn)位信號(hào)，ret清零，en計(jì)數(shù)使能,use ieee.std_logic_1164.all; -mode為12和24進(jìn)制的切換，use ieee.std_logic_unsigned.all; - cql小時(shí)的個(gè)位輸出，cqh小時(shí)的十位輸出entity cnt24 isport (clk,rst,en,mode: in std_logic;cql: out std_logic_vector(3 do

6、wnto 0);cqh: out std_logic_vector(3 downto 0);end cnt24;architecture behav of cnt24 issignal cqi0: std_logic_vector (3 downto 0);signal cqi1: std_logic_vector (3 downto 0);signal cqi2: std_logic_vector (3 downto 0);signal cqi3: std_logic_vector (3 downto 0); beginp1: process(clk,rst,en) -24進(jìn)制模式 begi

7、n if rst=1 then cqi0 0);cqi1 0); elsif clkevent and clk=1 then if en =1 then if cqi12 then if cqi09 then cqi0=cqi0+1;else cqi00);cqi1=cqi1+1;end if;elsif cqi03 thencqi0=cqi0+1;else cqi00);cqi10); end if; end if; end if; end process p1; p2: process(clk,rst,en) -12進(jìn)制模式 begin if rst=1 then cqi2 0);cqi3

8、 0); elsif clkevent and clk=1 then if en =1 then if cqi31 then if cqi29 then cqi2=cqi2+1;else cqi20);cqi3=cqi3+1;end if;elsif cqi22 thencqi2=cqi2+1;else cqi2=0001;cqi30);end if; end if; end if; end process p2; p3: process(mode) -mode=1為24進(jìn)制，mode=0為12進(jìn)制 begin case mode is when 1= cql=cqi0;cqh cql=cqi

9、2;cqhnull; end case; end process p3;end behav;【3】控制邏輯模塊control library ieee; -exchge校時(shí)與計(jì)時(shí)模式控制，use ieee.std_logic_1164.all; -minute手動(dòng)分校時(shí)use ieee.std_logic_unsigned.all; -hour手動(dòng)時(shí)校時(shí)entity control is -cy0,cy1分別接受秒和分的進(jìn)位信號(hào)port (minute,hour,exchge,cy0,cy1: in std_logic; -clk0,clk1分別控制分和小時(shí)的時(shí)鐘脈沖clk0: out std

10、_logic;clk1: out std_logic);end control;architecture behav of control issignal a0: std_logic;signal a1: std_logic;beginp1: process(exchge,minute,hour) begin if exchge=1 then a0=minute; a1=hour; end if;end process p1;p2: process(exchge,cy0,cy1) -exchge=1校時(shí)模式，exchge=0為計(jì)時(shí)模式 begin if exchge=1 then clk0=

11、a0;clk1=a1; else clk0=cy0;clk1=cy1; end if;end process p2;end architecture behav;【4】動(dòng)態(tài)掃描模塊scan_led library ieee; -scan動(dòng)態(tài)掃描時(shí)鐘信號(hào)use ieee.std_logic_1164.all; -din接受時(shí)、分、秒數(shù)據(jù)use ieee.std_logic_unsigned.all; -sg輸出段選信號(hào)entity scan_led is -輸出位選信號(hào) port(scan : in std_logic;din:in std_logic_vector(23 downto 0);s

12、g:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0);end;architecture one of scan_led is signal cnt6:std_logic_vector(2 downto 0); signal d:std_logic_vector(3 downto 0); beginp1:process(scan) begin if scanevent and scan=1 then if cnt65 then cnt6=cnt6+1; else cnt6 bt bt bt bt bt bt

13、null; end case;end process p2;p4: process(cnt6) begin case cnt6 iswhen000= d d d d d d null; end case; end process p4;p3:process(d) -段選 begin case d is when 0000 =sgsgsgsgsgsgsgsgsgsgnull; end case;end process p3;end architecture one;【5】整點(diǎn)報(bào)時(shí)模塊alarmlibrary ieee;-ml輸入分個(gè)位，mh輸入分十位use ieee.std_logic_1164

14、.all; -sl輸入秒個(gè)位，sh輸入秒十位use ieee.std_logic_unsigned.all; -clk輸入1024hz時(shí)鐘脈沖entity alarm is -speaker輸出報(bào)時(shí)信號(hào) port (ml: in std_logic_vector(3 downto 0); mh: in std_logic_vector(3 downto 0); sl: in std_logic_vector(3 downto 0); sh: in std_logic_vector(3 downto 0);clk: in std_logic; speaker: out std_logic);en

15、d alarm;architecture behav of alarm issignal div2clk: std_logic;begin process(clk) begin -實(shí)驗(yàn)箱的可用時(shí)鐘有限，1024hz作高音信號(hào) if clkevent and clk=1 then -1024hz時(shí)鐘脈沖2分頻，產(chǎn)生蜂鳴低音信號(hào) div2clk=not div2clk; end if; end process; process(mh,ml,sh,sl) begin if mh=5 and ml=9 then if sh=5 then if (sl=1 or sl=3 or sl=5 or sl=7

16、) then -51、53、55、57秒輸出低音信號(hào) speaker=div2clk; elsif (sl=9) then -59秒輸出高音信號(hào) speaker=clk; else speaker=0; end if; else speaker=0; end if; else speakerclk,rst=rst,en=en,cout1=m0, cqh=d(7 downto 4),cql=d(3 downto 0); u2: cnt60 port map(clk=m2,rst=rst,en=en,cout1=m1, cqh=d(15 downto 12),cql=d(11 downto 8); u3: cnt24 port map(clk=m3,rst=rst,en=en,mode=tmode, cqh=d(23 downto 20),cql=d(19 downto 16); u4: control port map(exchge=exchge,hour=hour,minute=minute, clk0=m2,clk1=m3,cy0=m0,cy1=m1); u5: scan_led port map(scan=scan,sg=sg,bt=bt, din(3 downto 0)=d(