交通燈信號(hào)控制設(shè)計(jì)

1、eda技術(shù)實(shí)驗(yàn)報(bào)告冊(cè)班級(jí)： 姓名：學(xué)號(hào)：指導(dǎo)教師：開課時(shí)間: 2013 至 2014 學(xué)年第 1 學(xué)期實(shí)驗(yàn)名稱交通燈信號(hào)控制設(shè)計(jì)實(shí)驗(yàn)時(shí)間2013年12月05日姓 名實(shí)驗(yàn)成績(jī)一、實(shí)驗(yàn)?zāi)康?.掌握vhdl語(yǔ)言的基本結(jié)構(gòu)。2.掌握vhdl層次化的設(shè)計(jì)方法。3.掌握vhdl基本邏輯電路的綜合設(shè)計(jì)應(yīng)用。二、實(shí)驗(yàn)設(shè)備計(jì)算機(jī)軟件：quartus iieda實(shí)驗(yàn)箱。主芯片：epm7128slc84-15或ep1k100qc208-3。下載電纜，導(dǎo)線等。三、實(shí)驗(yàn)內(nèi)容設(shè)計(jì)并調(diào)試好一個(gè)由一條主干道和一條支干道的匯合點(diǎn)形成的十字交叉路口的交通燈控制器，具體要求如下：1.主、支干道各設(shè)一個(gè)綠、黃、紅指示燈，兩個(gè)顯示數(shù)碼

2、管。2.主干道處于常允許通行狀態(tài)，而支干道有車來(lái)時(shí)才允許通行。當(dāng)主干道允許通行亮綠燈時(shí)，支干道亮紅燈。而支干道允許通行亮綠燈時(shí)，主干道亮紅燈。3.當(dāng)主、支干道均有車時(shí)，兩者交替允許通行，主干道每次放行45s，支干道每次放行25s，在每次由亮綠燈變成亮紅燈的轉(zhuǎn)換過(guò)程中，要亮5s的黃燈作為過(guò)渡，并進(jìn)行減計(jì)時(shí)顯示。要求編寫交通燈控制器電路邏輯圖中的各個(gè)模塊的vhdl語(yǔ)言程序，并完成交通燈控制器的頂層設(shè)計(jì)，然后利用開發(fā)工具軟件對(duì)其進(jìn)行編譯和仿真，最后要通過(guò)實(shí)驗(yàn)開發(fā)系統(tǒng)對(duì)其進(jìn)行硬件驗(yàn)證。（一）編寫交通燈控制器jtdkz模塊的vhdl程序，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。library iee

3、e;use ieee.std_logic_1164.all;entity jtdkz isport(clk, sm, sb: in std_logic;mr, my, mg, br, by, bg: out std_logic);end entity jtdkz;architecture art of jtdkz istype state_type is(a, b, c, d);signal state: state_type;signal cnt:integer range 0 to 45;begin process(clk) isbeginif(clk'event and clk=

4、'1')thencase state is when a=> if(sb and sm)='1' thenif cnt=44 then cnt<=0; state<=b;else cnt<=cnt+1;state<=a; end if; elsif(sb and (not sm)='1' thenstate<=b; cnt<=0; else state<=a; cnt<=0; end if; when b=> if cnt=4 then cnt<=0;state<=c; el

5、se cnt<=cnt+1;state<=b; end if; when c=> if(sm and sb)='1' then if cnt=24 then cnt<=0; state<=d; else cnt<=cnt+1;state<=c; end if; elsif sb='0' then state<=d; cnt<=0; else state<=c; cnt<=0; end if;when d=> if cnt=4 then cnt<=0; state<=a; else

6、 cnt<=cnt+1;state<=d; end if;end case;end if;end process ; rgy:process(state) isbegincase state iswhen a=>mr<='0' my<='0' mg<='1'br<='1' by<='0' bg<='0'when b=>mr<='0' my<='1' mg<='0'br<

7、='1' by<='0' bg<='0'when c=>mr<='1' my<='0' mg<='0'br<='0' by<='0' bg<='1'when d=>mr<='1' my<='0' mg<='0'br<='0' by<='1' bg<='0'end

8、case; end process rgy;end architecture art;（二）編寫45s定時(shí)單元cnt45s模塊的vhdl程序，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。-45s定時(shí)模塊源程序cnt45s.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_45s is port(sb,sm, clk, en45: in std_logic; dout45m, dout45b: out std_logic_vector(7 downto 0); e

9、nd entity time_45s ; architecture art of time_45s is signal cnt6b: std_logic_vector(5 downto 0); begin process(sb, sm, clk, en45) is begin if(clk'event and clk= '1')then if sb='1' and sm='1' then if en45='1'then cnt6b<=cnt6b+1;else cnt6b<="000000"

10、end if; else cnt6b<="000000" end if; end if; end process; process(cnt6b) is begin case cnt6b is when "000000"=>dout45m<="01000101" dout45b<="01010000" -bcd數(shù)45, 50 when "000001"=>dout45m<="01000100" dout45b<="010010

11、01" -bcd數(shù)44, 49 when "000010"=>dout45m<="01000011" dout45b<="01001000" -bcd數(shù)43, 48 when "000011"=>dout45m<="01000010" dout45b<="01000111" -bcd數(shù)42, 48 when "000100"=>dout45m<="01000001" dout45

12、b<="01000110" -bcd數(shù)41, 50 when "000101"=>dout45m<="01000000" dout45b<="01000101" -bcd數(shù)40, 49 when "000110"=>dout45m<="00111001" dout45b<="01000100" -bcd數(shù)39, 48 when "000111"=>dout45m<="001

13、11000" dout45b<="01000011" -bcd數(shù)38, 48 when "001000"=>dout45m<="00110111" dout45b<="01000010" -bcd數(shù)37, 50 when "001001"=>dout45m<="00110110" dout45b<="01000001" -bcd數(shù)36, 49 when "001010"=>dou

14、t45m<="00110101" dout45b<="01000000" -bcd數(shù)35, 48 when "001011"=>dout45m<="00110100" dout45b<="00111001" -bcd數(shù)34, 48 when "001100"=>dout45m<="00110011" dout45b<="00111000" -bcd數(shù)33, 50 when "00

15、1101"=>dout45m<="00110010" dout45b<="00110111" -bcd數(shù)32, 49 when "001110"=>dout45m<="00110001" dout45b<="00110110" -bcd數(shù)31, 48 when "001111"=>dout45m<="00110000" dout45b<="00110101" -bcd數(shù)30

16、, 48 when "010000"=>dout45m<="00101001" dout45b<="00110100" -bcd數(shù)29, 50 when "010001"=>dout45m<="00101000" dout45b<="00110011" -bcd數(shù)28, 49 when "010010"=>dout45m<="00100111" dout45b<="0011

17、0010" -bcd數(shù)27, 48 when "010011"=>dout45m<="00100110" dout45b<="00110001" -bcd數(shù)26, 48 when "010100"=>dout45m<="00100101" dout45b<="00110000" -bcd數(shù)25, 50 when "010101"=>dout45m<="00100100" dout

18、45b<="00101001" -bcd數(shù)24, 49 when "010110"=>dout45m<="00100011" dout45b<="00101000" -bcd數(shù)23, 48 when "010111"=>dout45m<="00100010" dout45b<="00100111" -bcd數(shù)22, 48 when "011000"=>dout45m<="0

19、0100001" dout45b<="00100110" -bcd數(shù)21, 50 when "011001"=>dout45m<="00100000" dout45b<="00100101" -bcd數(shù)20, 49 when "011010"=>dout45m<="00011001" dout45b<="00100100" -bcd數(shù)19, 48 when "011011"=>d

20、out45m<="00011000" dout45b<="00100011" -bcd數(shù)18, 48 when "011100"=>dout45m<="00010111" dout45b<="00100010" -bcd數(shù)17, 50 when "011101"=>dout45m<="00010110" dout45b<="00100001" -bcd數(shù)16, 49 when "

21、011110"=>dout45m<="00010101" dout45b<="00100000" -bcd數(shù)15, 48 when "011111"=>dout45m<="00010100" dout45b<="00011001" -bcd數(shù)14, 48 when "100000"=>dout45m<="00010011" dout45b<="00011000" -bcd數(shù)

22、13, 50 when "100001"=>dout45m<="00010010" dout45b<="00010111" -bcd數(shù)12, 49 when "100010"=>dout45m<="00010001" dout45b<="00010110" -bcd數(shù)11, 48 when "100011"=>dout45m<="00010000" dout45b<="00

23、010101" -bcd數(shù)10, 48 when "100100"=>dout45m<="00001001" dout45b<="00010100" -bcd數(shù)9, 50 when "100101"=>dout45m<="00001000" dout45b<="00010011" -bcd數(shù)8, 49 when "100110"=>dout45m<="00000111" dout

24、45b<="00010010" -bcd數(shù)7, 48 when "100111"=>dout45m<="00000110" dout45b<="00010001" -bcd數(shù)6, 48 when "101000"=>dout45m<="00000101" dout45b<="00010000" -bcd數(shù)5, 50 when "101001"=>dout45m<="0000

25、0100" dout45b<="00001001" -bcd數(shù)4, 49 when "101010"=>dout45m<="00000011" dout45b<="00001000" -bcd數(shù)3, 48 when "101011"=>dout45m<="00000010" dout45b<="00000111" -bcd數(shù)2, 07 when "101100"=>dout45m

26、<="00000001" dout45b<="00000110" -bcd數(shù)1, 06 when others=>dout45m<="00000000" dout45b<="00000000" -bcd數(shù)00, 00 end case; end process; end architecture art;（三）編寫25s定時(shí)單元cnt25s模塊的vhdl程序，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。-25s定時(shí)模塊源程序cnt25s.vhd library ieee; use ie

27、ee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_25s is port(sb, sm, clk, en25: in std_logic; dout25m, dout25b: out std_logic_vector(7 downto 0); end entity time_25s; architecture art of time_25s is signal cnt_5bit: std_logic_vector(4 downto 0); begin process(sb, sm, clk, en25) is

28、 begin if sb='0' or sm='0' then cnt_5bit<="00000" elsif(clk'event and clk= '1')then if en25='1' then cnt_5bit<=cnt_5bit+1; elsif en25='0'then cnt_5bit<="00000" end if; end if; end process; process(cnt_5bit) is begin case cnt_5b

29、it is when "00000"=>dout25b<="00100101" dout25m<="00110000" -bcd數(shù)25, 50 when "00001"=>dout25b<="00100100" dout25m<="00101001" -bcd數(shù)24, 49 when "00010"=>dout25b<="00100011" dout25m<="001010

30、00" -bcd數(shù)23, 48 when "00011"=>dout25b<="00100010" dout25m<="00100111" -bcd數(shù)22, 48 when "00100"=>dout25b<="00100001" dout25m<="00100110" -bcd數(shù)21, 50 when "00101"=>dout25b<="00100000" dout25m&l

31、t;="00100101" -bcd數(shù)20, 49 when "00110"=>dout25b<="00011001" dout25m<="00100100" -bcd數(shù)19, 48 when "00111"=>dout25b<="00011000" dout25m<="00100011" -bcd數(shù)18, 48 when "01000"=>dout25b<="00010111&

32、quot; dout25m<="00100010" -bcd數(shù)17, 50 when "01001"=>dout25b<="00010110" dout25m<="00100001" -bcd數(shù)16, 49 when "01010"=>dout25b<="00010101" dout25m<="00100000" -bcd數(shù)15, 48 when "01011"=>dout25b<=

33、"00010100" dout25m<="00011001" -bcd數(shù)14, 48 when "01100"=>dout25b<="00010011" dout25m<="00011000" -bcd數(shù)13, 50 when "01101"=>dout25b<="00010010" dout25m<="00010111" -bcd數(shù)12, 49 when "01110"=&

34、gt;dout25b<="00010001" dout25m<="00010110" -bcd數(shù)11, 48 when "01111"=>dout25b<="00010000" dout25m<="00010101" -bcd數(shù)10, 48 when "10000"=>dout25b<="00001001" dout25m<="00010100" -bcd數(shù)9, 50 when "

35、;10001"=>dout25b<="00001000" dout25m<="00010011" -bcd數(shù)8, 49 when "10010"=>dout25b<="00000111" dout25m<="00010010" -bcd數(shù)7, 48 when "10011"=>dout25b<="00000110" dout25m<="00010001" -bcd數(shù)6, 4

36、8 when "10100"=>dout25b<="00000101" dout25m<="00010000" -bcd數(shù)5, 50 when "10101"=>dout25b<="00000100" dout25m<="00001001" -bcd數(shù)4, 49 when "10110"=>dout25b<="00000011" dout25m<="00001000&quo

37、t; -bcd數(shù)3, 48when "10111"=>dout25b<="00000010" dout25m<="00000111" -bcd數(shù)2, 07 when "11000"=>dout25b<="00000001" dout25m<="00000110" -bcd數(shù)1, 06 when others =>dout25b<="00000000" dout25m<="00000000&qu

38、ot; -bcd數(shù)00, 00 end case; end process; end architecture art;（四）編寫5s定時(shí)單元cnt05s模塊的vhdl程序，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。-5s定時(shí)模塊源程序cnt05s.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity time_5s is port(clk, en05m, en05b: in std_logic; dout5: out std_logic_vector(7 downto 0

39、); end entity time_5s; architecture art of time_5s is signal cnt_3bit: std_logic_vector(2 downto 0); begin process(clk, en05m, en05b) is begin if(clk'event and clk= '1')then if en05m='1' or en05b='1' then cnt_3bit<=cnt_3bit+1; else cnt_3bit<="000" end if;

40、end if; end process; process(cnt_3bit) is begin case cnt_3bit is when "000" =>dout5<="00000101" -bcd數(shù)05 when "001" =>dout5<="00000100" -bcd數(shù)04 when "010" =>dout5<="00000011" -bcd數(shù)03 when "011" =>dout5<=&quo

41、t;00000010" -bcd數(shù)02 when "100" =>dout5<="00000001" -bcd數(shù)01 when others=>dout5<="00000000" -bcd數(shù)00 end case; end process; end architecture art;（五）編寫顯示控制單元xskz模塊的vhdl程序，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。-顯示控制模塊源程序xskz.vhd library ieee; use ieee.std_logic_1164.all; us

42、e ieee.std_logic_unsigned.all; entity xskz is port(en45, en25, en05m, en05b:in std_logic; ain45m, ain45b: in std_logic_vector(7 downto 0); ain25m, ain25b, ain05: in std_logic_vector(7 downto 0); dec_m, dec_b: out std_logic_vector(7 downto 0); end entity xskz; architecture art of xskz is begin proces

43、s(en45,en25,en05m, en05b,ain45m,ain45b,ain05,ain25m,ain25b) is begin if en45='1' then dec_m<=ain45m(7 downto 0); dec_b<=ain45b(7 downto 0); elsif en05m='1' then dec_m<=ain05(7 downto 0); dec_b<=ain05(7 downto 0); elsif en25='1' then dec_m<=ain25m(7 downto 0); d

44、ec_b<=ain25b(7 downto 0); -elsif en05b='1' then else dec_m<=ain05(7 downto 0); dec_b<=ain05(7 downto 0); end if; end process; end architecture art; （六）數(shù)碼管動(dòng)態(tài)掃描顯示電路設(shè)計(jì)library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity disp_s

45、can is port(clk_scan: in std_logic; dec_m: in std_logic_vector(7 downto 0); dec_b: in std_logic_vector(7 downto 0); ledw: out std_logic_vector(2 downto 0); seg7: out std_logic_vector(7 downto 0); end entity disp_scan; architecture art of disp_scan issignal temp: std_logic_vector(3 downto 0);signal c

46、nt:std_logic_vector(2 downto 0); begin process(clk_scan) is begin if clk_scan'event and clk_scan='1' then if cnt="111" then cnt<="000" else cnt<=cnt+'1' end if; end if; end process; ledw<=cnt; process(cnt,temp,dec_b,dec_m) is begin case cnt is when &q

47、uot;000" => temp<=dec_m(7 downto 4); when "001" => temp<=dec_m(3 downto 0); when "110" => temp<=dec_b(7 downto 4); when "111" => temp<=dec_b(3 downto 0); when others=> temp<="1111" end case; case temp is when "0000"

48、=> seg7<="00111111" when "0001"=> seg7<="00000110" when "0010"=> seg7<="01011011" when "0011"=> seg7<="01001111" when "0100"=> seg7<="01100110" when "0101"=> seg7<=

49、"01101101" when "0110"=> seg7<="01111101" when "0111"=> seg7<="00000111" when "1000"=> seg7<="01111111" when "1001"=> seg7<="01101111" when others=> seg7<="00000000" end

50、case; end process; end architecture art;（七）利用前面所設(shè)計(jì)的模塊，完成交通燈信號(hào)控制器的頂層設(shè)計(jì)，并對(duì)其進(jìn)行編譯和仿真，初步驗(yàn)證設(shè)計(jì)的正確性。library ieee;use ieee.std_logic_1164.all;entity traffic isport(sb,sm, clk, clk_scan: in std_logic;mr1,my1,mg1,br1,by1,bg1:buffer std_logic;-mr2,my2,mg2,br2,by2,bg2:out std_logic;ledw:out std_logic_vector(2 do

51、wnto 0);seg7: out std_logic_vector(7 downto 0);end entity traffic ;architecture art of traffic iscomponent jtdkz isport(clk, sm, sb: in std_logic;mr, my, mg, br, by, bg: out std_logic);end component jtdkz; component time_45s is port(sb,sm, clk, en45: in std_logic; dout45m, dout45b: out std_logic_vec

52、tor(7 downto 0); end component time_45s ; component time_25s is port(sb, sm, clk, en25: in std_logic; dout25m, dout25b: out std_logic_vector(7 downto 0); end component time_25s;component time_5s is port(clk, en05m, en05b: in std_logic; dout5: out std_logic_vector(7 downto 0); end component time_5s;

53、component xskz is port(en45, en25, en05m, en05b:in std_logic; ain45m, ain45b: in std_logic_vector(7 downto 0); ain25m, ain25b, ain05: in std_logic_vector(7 downto 0); dec_m, dec_b: out std_logic_vector(7 downto 0); end component xskz; component disp_scan is port(clk_scan: in std_logic; dec_m: in std_logic_vector(7 downto 0); dec_b: in std_logic_vector(7 downto 0); ledw: out std_logic_vector(2 downto 0); seg7: out std_logic_vector(7 downto 0); end component disp_scan; signal data_45m: std_logic_vector(7 downto 0);signal data_45b: st