外文文獻及翻譯：基于STC89C52單片機的多路搶答器設(shè)計

1、2010 International Conference on Intelligent Computation Technology and AutomationDesign and Implement of Responder Based on Freescale HCS12 Single Chip MicrocomputerCheng Qiming, Cheng Yinman, Wang Mingmei, Chang LinCollege of Electric Power and Automation Shanghai University of Electric PowerChang

2、yang 2588 road, Yandpu district, Shanghai 200090, China E-mail :chengqimingAbstractAn 8-channel responder based on Freescale HCS12 single chip microcomputer is designed. The responder can display the number of the first player correctly. It also can count the scores and show the player with the high

3、est score. The system includes four modules: CPU12, the SCI serial communication, digital display tube and timer. When competition signal input, it is been caught and then cause interruption, the timer is used to time accurately, the serial port is used to send and receive the start answer signal, j

4、udgment signal and other signals, the digital display tube is used to show the scores of the current player . LCD display tube shows subjects and answers. So the basic functions of the responder are achieved.Keywords-responder; single chip microcomputer; timer; input capture; interruptionI. INTRODUC

5、TIONResponder is also known as the first signal discriminator, which is widely used in various competitions. It can judge the number of the first player accurately, fairly and intuitively. Currently, a variety of quiz responder has emerged on the market, in which a small responder is commonly design

6、ed with small-scale digital integrated circuit. Although the technology has been quite mature, but it is simple function, low intelligence, high fault, simple display, less flexibility, not convenience for upgrade, it has been unable to meet all kinds of requirements for intellectual competitions an

7、d variety shows. Therefore, it is necessary to develop some kinds of responder which are more suitable for applications.In recent years, with the rapid development of science and technology, the applications of single-chip microcomputer are becoming widely, which promotes the development of traditio

8、nal measurement and control technology. In this paper, Freescale HCS12 1-3 is designed as a core component to achieve an intelligent digital responder with 8-channel 4-8, it has some breakthroughs on technology, function and other aspects, comparing with the past responder. It is characterized by si

9、mple structure, powerful, good reliability, practicability, so that the competition can really carried out on just, fair and open rules.II. FUNCTION OF RESPONDERThe basic functions of responder designed in this paper are:(1) The system can limit the competition time and answer time of the alarm;1 Th

10、is work is supported by Leading Academic Discipline Project of Shanghai Municipal Education Commission (Project Number: J510301， J510303)978-0-7695-4077-1/10 $26.00 © 2010 IEEE DOI 10.1109/ICICTA.2010.1281127(2) The system can identify the answer signal and identify the players number;(3) The s

11、ystem can calculate score for each player and display the scores.Responder can accommodate 8 players numbered 1 to 8. In addition, LED digital tubes are designed to display the latched data. After race host clears the system, if participants press switch, and after answer is certificated whether it

12、is correct or not, the number of first player to answer in action is immediately shown by digital tubes. Responder should have a strong ability to distinguish players to answer in the action, its resolution reaches at least a few ms.III. IDEAS OF RESPONDER DESIGNAfter the requirements and functions

13、of responder are analyzed, the following circuits are required in general:A Responder circuitThe circuit has two functions: one is to identify the number of the player who press button, and to save the number; the other is to prohibit the other players from buttoning or to make other buttons not ava

14、ilable.B Timing circuitsHost can set competition time and answer time by the time pre-set-circuit. If nobody can answer question within the set time, all players will not get score, then the host will announce the answer. Besides, if someone gets the chance to answer the question, but does not give

15、the right result before the allowable time, he or she wont get the score, the overtime signal will be also send, the host will declare the right answer. Freescale HCS12 contains timer module, the timer module can be directly used.C Overtime circuitHCS12 will send overtime signal when time goes beyon

16、d the set time, this signal will be transferred to the PC computer by the serial port. The next question will be proceeded to answer.D Scores count and display circuit.When host presses the answer key, it is time to start to answer, if one player presses the answer key, his or her number will be rec

17、orded, his or her score will be counted and displayed on the LED digital tubes.Bedside the circuits designed above, some necessary logic designs are also necessary. The logic designs are as following:First, the host will read the question which will show in the LCD; next, the PC computer will send l

18、etter “k”, which means that play is beginning to competition. At the same time, timing circuit starts to work, if nobody gets the chance to answer the question within permitted time, microcontroller will send the word “chao shi” to PC computer; If someone presses the competition key within the speci

19、fied time, microcontroller will send his or her number. If the time goes beyond the permitted time, PC computer will send “next” which means turning to the next question, the next question will be automatically showed to answer. If some player gets the chance to answer the question, his or her numbe

20、r and scores will decrease 1 automatically and show in the digital tubes, then microcontroller sends “next” to go on the next question. If the score is few than 0 after decreasing, player is eliminated. The right answer will show on the LCD. Finally, if all the questions are done, microcontroller wi

21、ll send “e” to end the game, then the scores of all players will be computed, the highest one will be shown on the digital tubes.IV. DESIGN OF RESPONDER HARDWAREResponder hardware is firstly designed; Responder hardware is taken directly from the hardware resources of Freescale HCS12 development boa

22、rd developed by Suzhou University. The development board takes MC9S12DG128 as the core, using modular design approach, it extracts part of I/O resources, and it also provides each module with a corresponding interface circuit. It also provides A/D input channels, PWM low-pass filter circuits, 16-key

23、 keyboard input channels, 8-bit digital I/O circuits, SPI I/O circuits, SCIcommunication circuits, I2C bus I/O expansion circuits and so on.In this paper, the hardware modules, the pin connections and the corresponding interfaces of the development board are listed and unified to redesign by actual

24、needs of the system. Figure 1 shows the hardware structure diagram of the selected part of development board.Figure 1. Diagram of hardware structureA Selection of hardware modulesThe responder designed in this paper is relatively simple, the I/O ports and the modules involved are not many.(1) The sy

25、stem uses push-button switch as the competition key, which is generally used as a switch input, there are 0 and1. Here, the system need know whether the button is switched by somebody, the system need not care about the switch on or off.(2) Timer module is indispensable in timing circuit. Here, the

26、timer module's functions are to limit time, and to captureinput signals. This will be followed some of the circuit design described in detail.(3) LED digital tubes are used to show the participants number and scores in the display circuit. The system records the player's number and the corre

27、sponding score, and then transmits to the LED digital tubes through I/O ports. LCD is achieved by external connection module; it is used to display questions and answers.(4) LED small light is used to show whether somebody presses the competition button. If player answer, the small light will be bri

28、ght, otherwise, it will not light.(5) SCI module is necessary in serial communication port. Since the signal that starts to answer needs to be send by PC computer, if there is no serial communication port, the whole system will be paralyzed. The function of SCI module is thatreceives the signal to H

29、CS12, and then sends the players number to PC.B Design of hardware circuits1)Competition circuit designCompetition circuit captures competition signals by means of input capturing; there will be a interruption once the push- button switch jumps. 8 push-button switches are connected with 8 channels,

30、so the system can know which player competes to answer the question by reading corresponding channel. In this paper, the 8 channels connect with input capture channels PT0 PT7 of HCS12.2) Timing circuitAs the HCS12 has its own timing module, timing circuit dont need to be designed, and internal timi

31、ng module of HCS12 can be directly used.3) Overtime reminding circuitSmall light or buzzer could connect with any I/O port, but the system should ensure the selected I/O ports have not conflict with the I/O ports occupied by the module. Once the specified time is over, I / O port send a high level,

32、and the LED small light is on. In this paper, the first pin of PA port is chosen as the alarm signal port; this pin is connected to the testing of small light.4) Electronic counter and display circuitThe scoring scores can be resolved by programming, but the displaying scores needs hardware connecti

33、on, LED digital tubes and LCD are connected with corresponding I/O ports of HCS12, external LCD module should have the function of displaying Chinese characters.5) Communication connectThe development board has a 9-pin cable of RS232 serial port; it can be connected with PC computer by the cable.V.

34、DESIGN OF RESPONDER SOFTWAREA Design of software subprogram1) SCI subprogram(1) SCI initialization functionSCI initialization is to set corresponding register, mainly to set serial port baud rate, here baud rate is set to 9600 bps, the baud rate is:Bt = fBUS / (16 * BR)(1)where, BR is set by SCI bau

35、d rate register, and it is a 16-bit register, is assigned twice, first set the low 8 bits, and then setthe higher 5 bits, the first three of high 8 bits are meaningless;fBUS is the bus frequency.The next is to set control registers (SCICR1 and SCICR2),here SCI serial port be allowed to run, and the

36、normal code, 8- bit, no parity data is output. The D6 bit of the SCICR1 (SCISWAI) is a SCI allowing bit, SCI module is prohibited at SCISWAI=1, SCI module is allowed when SCISWAI=0; D4 bit (M bit) is a choice bit of pattern/character length, it is used to define the sending/receiving data format, 9-

37、bit data transfer is allowed at M=1, 8-bit data transfer is allowed at M= 0; D1 bit (PE) is the parity enabling bit, PE=1 allows parity, PE = 0 does not allow parity. SCICR2 needs also to be set in order to receive and send data, the D3 bit of SCICR2 (TE) is a transmitter allowing bit, TE=1 allows t

38、o send, TE=0 prohibits to send; D2 bit is receiver allowing bit, RE=1 allows to receive, RE=0 prohibits to receive.(2) SCI sending functionFirstly, 1 bit sending function of serial port should be programmed. At the beginning, SCI status register 1 (SCISR1) needs to be judged, its D7 bit (TDRE) sends

39、 the empty flag of data register at TDRE=1, which means that the data to send has already moved into the sending shift register, if the data register is empty, the new data that is written into the data register can be sent. More bits data sending function calls repeatedly 1 bit sending functions un

40、til the sending is over.(3) SCI receiving functionSimilarly, 1 bit receiving function of serial port is programmed. Here, SCI status register 1 (SCISR1) is judged, its D5 bit (RDRF) represents the full flag of the receiving data register. RDRF=1 means that the receiver is full, the received data can

41、 be read from the SCI data register, then, the data needs to be read out from data register (SCIDR). The receiving data is one more step than the sending data, which it is to determine whether any data has been received. If the receiving process is failed, FFH data will be returned. More bits data r

42、eceiving function call repeatedly 1 bit receiving function, and the system will report the receiving error as long as there is 1 bit receiving failure.2) Timer subprogram(1) Timer initializationWhen timer is initialized, timer is prohibited to work until timer is used. The D7 bit (TEN) of timer cont

43、rol register 1(TSCR1) is an enabling bit of timer, timer is enabled at TEN=1, and timer is disabled at TEN=0. The following step is to allow the timer interrupt and to prohibit the timer reset. The D7 bit (TOI) and the D3 bit (TCRE) of timer control register 2 (TSCR2) are respectively the enabling b

44、it of timer overflow interrupt and the reset enabling bit of timer counter, timer interrupt is allowed at TOI=1, otherwise, timer interrupt is not allowed at TOI=0. When OC7 is successfully compared, the counter can be reset at TCRE=1, it cant be reset at TCRE=0; D2 D0 bits (PR2 PR0) of TSCR2 are th

45、e selection bits of frequency factor, they are used to set the division factor of bus clock frequency, frequency division factor p can be 1,2,4,8,16, 32, 64 or 128. The overflow time of timer can be described as following:t=np/fBUS(2)where, n is the count value of counter; fBUS is the bus clock freq

46、uency; p is the frequency division factor. In this paper, n =216 = 65536, p is chosen to be 2, t0.03s, t is much closed to 1/38s, 38 interruptions is about 1s.(2) Input capturing initializationFirst, the option is to capture input or to compare output. The select register of input capturing/output c

47、omparing (TIOS) is used to do this work, the Dx bit (IOSx) of the register is the select bit of x channel, the x channel is set as the output comparing channel at IOSx = 1, and it is set as the input capturing channel at IOSx = 0. In our design, because 8 players take pert in the competition, 8 chan

48、nels should all be set as input capturing channels, namely TIOS = 0x00.After input capturing is set, the interruption also needs to be open, which it should be done after the competition is allowed.3) Subprogram of LED digital tubes(1) Initialization of LED digital tubesLED digital tubes are used to

49、 dynamic display, its initialization is the I/O port initialization, the direction registers of corresponding I/O ports (the pins of 8-bit data port are connected with 7-segment digits and decimal point of digital tubes; the pins of 4-bit bit choice are connected with 4 digital tubes) are set to be

50、output, that is, data port is 0xFF, bit choice port is 0xF0.(2) Display of LED digital tubesThe basic idea of LED digital tubes display is that the display codes of all the numbers and the chip select code of the displaying bits are stored into the corresponding registers, when display functions are

51、 called, the parameter numbers of functions can match with the numbers and the bits in the tables of number display code and chip select code4) LCD display(1) LCD initializationThe module is enabled and the lattice size is defined as 8*8 or 8*10, the display format is defined as 1 row or 2 rows, the

52、 display of Chinese characters is used.(2) Subprogram of LCD displayThe emphasis of the program is the display of Chinese characters. Chinese characters are identified by two ASCII codes. The ASCII codes of Chinese characters to be displayed are recorded into data registers.B Design of interrupt ser

53、vice subprogram1) Subprogram of overflow interruptionThe frequency division factor has been set in the program of timer initialization, 38 interruptions is about 1s, so the counter variable needs to be set, it adds 1 automatically after each interruption, it calls the second accumulating function af

54、ter 38 interruptions. It needs to be noted that the interruption flag register 2 (TFLG2) is set to 0 after each overflow interruption. Otherwise, the system is always identified as overflow interrupt. D7 bit of the register is TOF bit, when the 16-bit running counter changes from $FFFF to $0000, the

55、 overflow interrupt occurs, this bit is set to 1, this bit can be cleared by writing 0 to it, other 7 bits are invalid. The flow of overflow interrupt is shown in Figure 2.2) Subprogram of input capturing interruptionThe main task of input capturing interruption program is to judge whether player co

56、mpetes to answer and to record the players number. The interrupt flag bit needs to be set, it is set to 1 when an interrupt happens, which means that someonecompetes to answer, and then the person number will be read. Interrupt flag register 1 (TFLG1) of main timer is used to read the interrupt chan

57、nel. Its Dx bit (CxF) is the interrupt flag of input capturing / output comparing channel x, when an input capturing / output comparing event happen, the corresponding bit is set to 1, the channel number of corresponding interrupting can read from TFLG1 register and it is also the number of competit

58、ion player. To note that, the flag register needs to be cleared after the flag register is read. The flag register can be cleared when the appropriate channel is set to 1. The flow of input capturing interrupt is shown in Figure 3.VI. CONCLUSIONSResponder is one of the essential devices in various knowledge and intellectual contests, the development of better and more intelligent digital responder is very significant. Responder designed in this paper can ach