實(shí)驗(yàn)七數(shù)據(jù)選擇與譯碼顯示

1、7 722021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用實(shí)驗(yàn)?zāi)康?2021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用實(shí)驗(yàn)設(shè)備與材料42021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用掃描顯示掃描顯示增加增加按鍵去抖動(dòng)按鍵去抖動(dòng)實(shí)驗(yàn)任務(wù)52021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用實(shí)驗(yàn)原理與電路圖62021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用72021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用視覺殘留視覺殘留82021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用92021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用102021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module basic_4to1_mux(in, led0); input wire 7:0 in; ou

2、tput wire led0; always (in3:0, in7:6) begin case (in7:6) 2b00 : led0 = in0; 2b01 : led0 = in1; 2b10 : led0 = in2; 2b11 : led0 = in3; endcase endendmodule112021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module displayswitch(clk, digit_anode, segment);/ port declaration, and define variable: disp_numassign disp_num = 16b1010_10

3、11_1100_1101; / display AbCd“display DISPLAY_0(clk, disp_num, digit_anode, segment);endmodulemodule display(clk, disp_num, digit_anode, segment);/ port declaration, and define variable: cnt, numalways (posedge clk) begin/ increment countercase (cnt11:10)/ display each digit according to cnt11:10endc

4、asecase (num)/ display 0F accroding to numendcaseendendmodule122021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module displayswitch(clk, btn_in, digit_anode, segment);/ port declaration, and define variable: disp_numinitial disp_num = 16b1010_1011_1100_1101; / display AbCdalways(posedge btn_in0) disp_num 3: 0= disp_num 3: 0 +

5、4d1;always(posedge btn_in1) disp_num 7: 4= disp_num 7: 4 + 4d1;always(posedge btn_in2) disp_num11: 8= disp_num11: 8 + 4d1;always(posedge btn_in3) disp_num15:12= disp_num15:12 + 4d1; display DISPLAY_0(clk, disp_num, digit_anode, segment);endmodulemodule display(clk, disp_num, digit_anode, segment);/

6、port declaration, and define variable: cnt, numalways (posedge clk) begin/ increment countercase (cnt11:10)/ display each digit according to cnt11:10endcasecase (num)/ display 0F accroding to numendcaseendendmodule132021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module displayswitch(clk, btn_in, digit_anode, segment);/ port d

7、eclaration, and define variable: disp_num, clk_1ms, btn_outdisplay DISPLAY_0 (clk, disp_num, digit_anode, segment);timer_1ms TIMER_1MS (clk, clk_1ms);anti_jitter ANTI_JETTER(clk, clk_1ms, btn_in, btn_out);initial disp_num = 16b1010_1011_1100_1101; / display AbCdalways(posedge btn_out0) disp_num 3: 0

8、=disp_num 3: 0 + 4d1;always(posedge btn_out1) disp_num 7: 4=disp_num 7: 4 + 4d1;always(posedge btn_out2) disp_num11: 8=disp_num11: 8 + 4d1;always(posedge btn_out3) disp_num15:12=disp_num15:12 + 4d1;endmodule142021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用實(shí)驗(yàn)內(nèi)容與測試步驟152021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module display(input wire clk,input wire

9、 15:0 digit,/顯示的數(shù)據(jù)output reg 3:0 node, /4個(gè)數(shù)碼管的位選output reg 7:0 segment);/七段+小數(shù)點(diǎn)reg 3:0 code = 4b0;reg 15:0 count = 15b0;always (posedge clk) begin case (count15:14) /與(count1:0)的不同?起到分頻的作用 2b00 : begin node = 4b1110; code = digit3:0; end 2b01 : begin node = 4b1101; code = digit7:4; end 2b10 : begin

10、node = 4b1011; code = digit11:8; end 2b11 : begin node = 4b0111; code = digit15:12; end endcase case (code) 4b0000: segment = 8b11000000; 4b0001: segment = 8b11111001; 4b0010: segment = 8b10100100; 4b0011: segment = 8b10110000; 4b0100: segment = 8b10011001; 4b0101: segment = 8b10010010; 4b0110: segm

11、ent = 8b10000010; 4b0111: segment = 8b11111000; 4b1000: segment = 8b10000000; 4b1001: segment = 8b10010000; 4b1010: segment = 8b10001000; 4b1011: segment = 8b10000011; 4b1100: segment = 8b11000110; 4b1101: segment = 8b10100001; 4b1110: segment = 8b10000110; 4b1111: segment = 8b10001110; default: seg

12、ment = 8b00000000; endcase count = count + 1;endendmodule162021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用172021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用這里注意這里注意display參數(shù)對應(yīng)關(guān)系！參數(shù)對應(yīng)關(guān)系！182021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用module timer_1ms(input wire clk,output reg clk_1ms);reg 15:0 cnt;initial begincnt 15:0 =0;clk_1ms =25000) begincnt=0;clk_1ms = clk_1ms;endelse begin

13、cnt=cnt+1;endendmodule192021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用202021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用212021-11-25數(shù)據(jù)選擇器設(shè)計(jì)及應(yīng)用HexD3D2D1D0BI/LEabcdefgp0 0 0 0 010000001p1 0 0 0 111001111p2 0 0 1 010010010p30 0 1 110000110p40 1 0 011001100p50 1 0 110100100p60 1 1 010100000p70 1 1 110001111p8 1 0 0 010000000P9 1 0 0 110000100PA 1 0 1 010001000PB1 0 1 111100000PC 1 1 0 010110001P