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1、renesas rx63n 32位rx mcu開發(fā)方案renesas公司的rx63n是100mhz 32位rx ,165d性能,集成了多達(dá)2mb閃存,以太網(wǎng)mac,全速 2.0主/功能/otg接口,包括can的各種通信接口,10位和12位和rtc.和現(xiàn)有產(chǎn)品相比,待機(jī)功耗降低大約90%,工作2.7- 3.6v,主要用在音頻設(shè)備,馬達(dá)控制,嬉戲機(jī)和通信設(shè)備.本文介紹了rx63n主要特性,方框圖,rx63n開發(fā)套件應(yīng)用和特性,方框圖,和材料清單.the rx63n/rx631 group incorporates communication functions suitable for netwo
2、rking equipment, such as ethernet controller, usb 2.0 full-speed (function, host, or otg selectable), and can. in addition, with a rtc (real-time clock) that can operate on a dedicated power supply as a low power feature, standby power consumption can be reduced by approximately 90% compared to exis
3、ting products. the selection of on-chip memory has been expanded from romless to 2 mb, and even smaller-sized packages are available. this makes possible mounting in anything from large-scale systems to small-scale/small-space devices.rx63n主要特性:32-bit rx cpu coremax. operating frequency: 100 mhzcapa
4、ble of 165 dmips in operation at 100 mhzsingle precision 32-bit ieee-754 floating pointtwo types of multiply-and-accumulation unit (between memories and between registers)32-bit multiplier (fastest instruction execution takes one cpu clock cycle)divider (fastest instruction execution takes two cpu c
5、lock cycles)fast interruptcisc harvard architecture with 5-stage pipelinevariable-length instructions: ultra-compact codesupports the memory protection unit (mpu)jtag and fine (two-line) debugging interfaceslow-power design and architectureoperation from a single 2.7- to 3.6-v supplylow power consum
6、ption: a product that supports all peripheral functions draws only 500ua/mhz.rtc is capable of operation from a dedicated power supply (min. operating voltage: 2 v).four low-power modeson-chip main flash memory, no wait statessupports rom-less versions and versions with up to 2 mbytes of rom (rom-le
7、ss version: rx631 group only)100-mhz operation, 10-ns read cycle (no wait states)384-kbyte to 2-mbyte capacitiesuser code programmable via the usb, sci, or jtagon-chip data flash memoryrom-less or 32 kbytes of rom (reprogrammable up to 100,000 times)programming/erasing as background operations (bgos
8、)on-chip sram, no wait states32- to 128-kbyte capacitiesfor instructions and operandscan provide backup on deep software standbydmadmac: four channelsdtcexdmac: two channelsdedicated dmac for the ethernet controller: single channelreset and supply managementpower-on reset (por)low voltage detection
9、(lvd) with voltage settingsclock functionsexternal crystal oscillator or internal pll for operation at 4 to 16 mhzinternal 125-khz loco and 50-mhz hocodedicated 125-khz loco for the iwdtreal-time clockadjustment functions (30 seconds, leap year, and error)time capture function (for capturing times i
10、n response to event-signal input on external pins)independent watchdog timer125-khz loco clock operationuseful functions for iec60730 complianceoscillation-stoppage detection, frequency measurement, crc, iwdt, selfdiagnostic function for the a/d converter, etc.various communications interfacesethern
11、et mac (1) (not in rx631 group products)host/function or otg controller (1) and function controller (1) with fullspeed usb 2.0 transfercan (compliant with iso11898-1), incorporating 32 mailboxes (up to 3 modules)sci with multiple functionalities (up to 13)choose from among asynchronous mode, clock-s
12、ynchronous mode, smartcard interface mode, simplified spi, simplified i2c, and extended serial mode.i2c bus interface for transfer at up to 1 mbps (up to 4)rspi for high-speed transfer (up to 3)external address spacebuses for high-speed data transfer (max. operating frequency of 50 mhz)8 cs areas (8
13、 16 mbytes)multiplexed address data or separate address lines are selectable per area.8-, 16-, or 32-bit bus space is selectable per areaindependent sdram area (128 mbytes)up to 20 extended-function timers16-bit mtu2: input capture, output compare, waveform output, phase-counting mode (6 channels)16
14、-bit tpu: input capture, output compare, phase-counting mode (12 channels)8-bit tmr (4 channels)16-bit compare-match timers (4 channels)a/d converter for 1-mhz operationup to 21 12-bit channels, and incorporating 1 sample-and-hold circuitup to 8 10-bit channels, and incorporating 1 sample-and-hold circuitaddition of results of a/d conversion (in the 12-bit converter)self diagnosis (for the 10-bit converter)10-bit d/a converter: 2 channelstemperature sensor for measuring temperature within the chipregister
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