數(shù)字系統(tǒng)設(shè)計(jì)與PLD應(yīng)用答案

1、1.7、 (1)算法模型(2)數(shù)據(jù)處理單元(框圖)2.10、2.17、流水線操作結(jié)構(gòu)：TS1=18*100+(256-1)*100=2.73*104(ns)順序算法結(jié)構(gòu)：TS2=256*18*100=4.608*105(ns)顯然流水線操作時(shí)間短。（若系統(tǒng)輸入數(shù)據(jù)流的待處理數(shù)據(jù)元素為m個，每一元素運(yùn)算共計(jì)L段，每段歷經(jīng)時(shí)間為，則流水線操作算法結(jié)構(gòu)共需運(yùn)算時(shí)間為：T=L·+(m-1) 而順序算法（或并行算法）結(jié)構(gòu)所需運(yùn)行時(shí)間為：m·L·）2.30、(1).DFF 狀態(tài)編碼A000 B001 C010 D011 E100輸出：（2）“一對一”狀態(tài)分配次態(tài)表：NSPS輸

2、入條件AAZCXEXBACBCDBZED-E激勵方程：輸出：3.2、試給出一位全減器的算法描述和數(shù)據(jù)流描述真值表：xybidbo0000000111010110110110010101001100011111x被減數(shù) y減數(shù) bi低位向本位的借位 d差 bo本位向高位的借位LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY full_sub IS PORT(x, y,bi : IN Std_Logic; d,bo : OUT Std_Logic);END full_sub;算法描述：ARICHITECTURE alg_fs OF full_sub I

3、SBIGIN PROCESS(x,y,bi) BEGIN IF (x=0 AND y=0 AND bi=0 OR x=1 AND y=0 AND bi=1 OR x=1 AND y=1 AND bi=0 ) THEN bo<=0' d<=0; ELSIF (x=1 AND y=0 AND bi=0 ) THEN bo<=0' d<=1; ELSIF (x=0 AND y=1 AND bi=1 ) THEN bo<=1' d<=0; ELSE bo<=1' d<=1; END IF; END PROCESS c1;E

4、ND alg_fs;數(shù)據(jù)流描述：（d=xybi bo=xy+xbi+ybi）ARICHITECTURE dataflow_fs OF full_sub ISBEGIN d<=x XOR y XOR bi; bo<=(NOT x AND y) OR (NOT x AND bi) OR (y AND bi);END dataflow_ha;3.4、(1).十進(jìn)制-BCD碼編碼器，輸入、輸出均為低電平有效。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOW

5、NTO 0) b : OUT Std_Logic_Vector(3 DOWNTO 0);END encoder;ARCHITECTURE beh_encoder OF encoder ISBEGIN WITH a SELECT b<= “0110” WHEN “0111111111”, “0111” WHEN “1011111111”, “1000” WHEN “1101111111”, “1001” WHEN “1110111111”, “1010” WHEN “1111011111”, “1011” WHEN “1111101111”, “1100” WHEN “1111110111

6、”, “1101” WHEN “1111111011”, “1110” WHEN “1111111101”, “1111” WHEN “1111111110”, “0000” WHEN OTHERS;END beh_encoder;補(bǔ)充：優(yōu)先編碼器LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0) b : OUT Std_Logic_Vector(3 DOWNTO 0);END encoder;ARCHITECTURE beh_encoder OF

7、encoder ISBEGIN WITH a SELECT b<= “0110” WHEN “0XXXXXXXXX”, “0111” WHEN “10XXXXXXXX”, “1000” WHEN “110XXXXXXX”, “1001” WHEN “1110XXXXXX”, “1010” WHEN “11110XXXXX”, “1011” WHEN “111110XXXX”, “1100” WHEN “1111110XXX”, “1101” WHEN “11111110XX”, “1110” WHEN “111111110X”, “1111” WHEN “1111111110”, “00

8、00” WHEN OTHERS;END beh_encoder;(2).時(shí)鐘RS觸發(fā)器。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY clk_rs_ff IS PORT(r,s,cp:IN Std_Logic; q,nq : BUFFER Std_Logic);END clk_rs_ff ;ARCHITECTURE beh_clkrsff OF clk_rs_ff ISBEGIN ASSERT NOT(r=1 AND s=1') REPORT"Control error" SEVERITY Error; PROCES

9、S(r,s,cp) BEGIN IF cp=1 THEN q<= s OR (NOT r AND q); nq<= NOT( s OR (NOT r AND q); END IF; END PROCESS;END beh_clkrsff;(3).帶復(fù)位端、置位端、延遲為15ns的響應(yīng)CP下降沿的JK觸發(fā)器。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY jk_ff IS GENERIC (tpd:Time:=15 ns); FORT (r,s,j,k,cp:IN Std_Logic; q,nq:BUFFEER Std_Logic);E

10、ND jk_ff;ARCHITECTURE beh_jkff OF jk_ff ISBEGIN ASSERT NOT(r='0 AND s='0') REPORT "Control error" SEVERITY Error; PROCESS(r,s,cp) BEGIN IF r=0 THEN q<=0 AFTER tpd; nq<=1 AFTER tpd; ELSIF s=0 THEN q<=1 AFTER tpd; nq<=0 AFTER tpd; ELSIF (cpEvent AND cp=0) THEN q<=j

11、 AND nq OR NOT k AND q AFTER tpd; nq<=NOT( j AND nq OR NOT k AND q) AFTER tpd; END IF; END PROCESS;END beh_jkff;(4).集成計(jì)數(shù)器74161。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;USE IEEE.Std_Logic_Unsigned.ALL; ENTITY counter16 IS PORT (cr, ld, cp, ctt, ctp : IN Std_Logic; d : IN Std_Logic_Vector(3 DOWNTO

12、0); q : BUFFER Std_Logic_Vector(3 DOWNTO 0); co :OUT Bit);END counter16;ARCHITECTURE behav_ctr16 OF counter16 ISBEGIN PROCESS (cr,cp) BEGIN IF cr=0 THEN q<=“0000”; ELSIF (cpEvent AND cp=1) THEN IF ld=0 THEN q<=d; ELSIF (ctt=1 AND ctp=1) THEN IF q=“1111” THEN q<=“0000”; ELSE q<=q+“0001”;

13、END IF; END IF; END IF; END PROCESS; co<=1 WHEN (q=“1111” AND ctt=1) ELSE 0;END beh_ctr16;(5).集成移位寄存器74194。 LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL; ENTITY srg IS PORT(cr, cp : IN Std_Logic; d : IN Std_Logic_Vector(3 DOWNTO 0); sl, sr: IN Std_Logic; m: IN Std_Logic_Vector(1 DOWNTO 0); q: BUFFER

14、 Std_Logic_Vector(3 DOWNTO 0); END srg; ARCHITECTURE behav_srg OF srg IS BEGIN PROCESS(cr, cp) BEGIN IF cr=0' THEN q<=“0000”; -異步復(fù)位 ELSIF(cpEvent AND cp=1) THEN CASE m IS WHEN "01"=> q<=sr & q(3 DOWNTO 1); -右移 WHEN "10"=> q<=q(2 DOWNTO 0) & sl; -左移 WHEN

15、 "11"=> q<=d; -并行輸入(同步預(yù)置) WHEN OTHERS=>NULL; -空操作，即保持 END CASE; END IF; END PROCESS; END behav_srg;3.6、(2).由D觸發(fā)器構(gòu)成的異步二進(jìn)制模8計(jì)數(shù)器異步2k進(jìn)制計(jì)數(shù)器的電路結(jié)構(gòu)計(jì)數(shù)規(guī)律觸發(fā)方式上升沿下降沿加法減法LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY asyn_ctr8 IS PORT(cp : IN Bit; q : BUFFER Std_Logic_Vector( 2DOWNTO 0);END ctr8;ARCHITECTURE struct_ctr8 OF asyn_ctr8 IS COMPONENT d_ff PORT (clk,d : IN Std_Logic; q,nq :OUT Std_Logic); END COMPONENT; SIGNAL nq0,