VHDL洗衣機(jī)設(shè)計(jì)

1、EDA課程實(shí)訓(xùn)報(bào)告一、實(shí)訓(xùn)課題：洗衣機(jī)控制器的設(shè)計(jì)二、設(shè)計(jì)的內(nèi)容及要求：1設(shè)計(jì)一個(gè)洗衣機(jī)控制器，要求為：1) 洗衣機(jī)控制器可以驅(qū)動(dòng)洗衣機(jī)進(jìn)行洗滌、漂洗或烘干；2) 洗衣機(jī)控制器可以設(shè)置洗衣機(jī)的工作時(shí)間，工作時(shí)間最短1分鐘，最長(zhǎng)30分鐘，在工作過程中，工作時(shí)間以倒計(jì)時(shí)顯示，若時(shí)間為0洗衣機(jī)停止工作；3) 洗衣機(jī)在待機(jī)狀態(tài)時(shí)，洗衣機(jī)控制器可以設(shè)置洗衣機(jī)的工作方式和工作時(shí)間；4) 可以暫?；蛲Ｖ瓜匆聶C(jī)工作；5) 利用四個(gè)數(shù)碼管顯示洗衣機(jī)待機(jī)時(shí)的設(shè)置時(shí)間和工作時(shí)的運(yùn)行時(shí)間，利用一位數(shù)碼管顯示洗衣機(jī)待機(jī)時(shí)所設(shè)置的工作方式運(yùn)行時(shí)的工作方式；6）利用三個(gè)LED分別表示驅(qū)動(dòng)洗衣機(jī)進(jìn)行洗滌、漂洗或烘干。2洗衣機(jī)

2、控制器可以劃分為狀態(tài)機(jī)模塊、計(jì)時(shí)器模塊、設(shè)置模塊和顯示選擇模塊。在QuartusII中輸入各個(gè)模塊的代碼，編譯綜合，仿真，完成各個(gè)模塊的軟件設(shè)計(jì)；4把各個(gè)模塊組合起來，綜合編譯，仿真，完成整個(gè)交通燈控制器系統(tǒng)的軟件設(shè)計(jì)；5. 選擇電路方案鎖定管腳，把程序下載到實(shí)驗(yàn)箱中，利用實(shí)驗(yàn)箱進(jìn)行硬件實(shí)現(xiàn)；6. 完成實(shí)訓(xùn)報(bào)告。實(shí)訓(xùn)報(bào)告包括：1) 設(shè)計(jì)的任務(wù)和要求；2) 模塊的劃分和系統(tǒng)總框圖；3) 各個(gè)模塊的實(shí)現(xiàn)，包括模塊的作用，模塊的輸入與輸出情況，模塊狀態(tài)圖，模塊的代碼以及注釋，模塊的波形圖；4) 系統(tǒng)的實(shí)現(xiàn)，包括系統(tǒng)總原理圖，系統(tǒng)的波形圖；5) 管腳的鎖定關(guān)系；三設(shè)計(jì)思路：u 狀態(tài)切換>>

3、>有限狀態(tài)機(jī)u 按定時(shí)時(shí)間及時(shí)>>> 定時(shí)計(jì)數(shù)器u 顯示時(shí)間>>> 數(shù)碼管譯碼驅(qū)動(dòng)器u 接收設(shè)置時(shí)間>>>時(shí)間設(shè)置鍵盤掃描器u 接收設(shè)置模式>>> 模式設(shè)置鍵盤掃描器u 切換顯示運(yùn)行時(shí)間和設(shè)置時(shí)間>>>二路選擇器u 切換顯示運(yùn)行模式和設(shè)置模式>>>二路選擇器整體設(shè)計(jì)示意圖：四系統(tǒng)組成以及系統(tǒng)各部分的設(shè)計(jì)： 1.狀態(tài)機(jī)的設(shè)計(jì)： 狀態(tài)機(jī)要完成的功能：l 能設(shè)置工作模式；l 控制洗滌、漂洗、干衣的驅(qū)動(dòng)輸出；l 能啟動(dòng)、暫停、停止洗衣機(jī)控制器；l 能重啟、暫停和停止定時(shí)器；l 能接收定時(shí)器

4、的到時(shí)標(biāo)志；l 能使能鍵盤掃描計(jì)數(shù)器；l 能控制二路選擇器。 狀態(tài)圖分析設(shè)計(jì)如下： 模塊設(shè)計(jì)圖如下：狀態(tài)機(jī)仿真圖如下：2. 定時(shí)器設(shè)計(jì)：定時(shí)器的功能：l 能通過使能端暫停和允許定時(shí)器工作；l 能停止并復(fù)位定時(shí)器；l 能進(jìn)行定時(shí)；l 能輸出定時(shí)標(biāo)志 模塊設(shè)計(jì)圖如下： 定時(shí)器波形圖如下： 3.時(shí)間設(shè)置： 時(shí)間設(shè)置鍵盤掃描器的功能：l 能響應(yīng)按鍵；l 能在使能端的控制下工作 模式設(shè)計(jì)圖如下： 波形圖如下： 4.模式設(shè)置: 模式設(shè)置鍵盤掃描器的功能：預(yù)設(shè)工作模式，”000”為待機(jī)，”001”為洗滌，”010”為漂洗，”022”為干衣，”100”為暫停模式設(shè)計(jì)圖如下：波形圖如下： 5. 二路選擇器 二路

5、選擇器的功能：設(shè)置顯示運(yùn)行時(shí)間還是設(shè)置時(shí)間，顯示運(yùn)行模式還是設(shè)置模式。模式設(shè)計(jì)圖如下：整體結(jié)構(gòu)圖：整體波形圖：五下載時(shí)選擇的開發(fā)系統(tǒng)模式以及管腳1.管教配置：2. 實(shí)驗(yàn)電路結(jié)構(gòu)圖：附錄代碼：1.狀態(tài)機(jī)LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY SHELL_WASHMACHINE ISPORT (CLK,modein0,modein1,modein2,pause,start,stop,tcin: IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2

6、 : OUT std_logic);END;ARCHITECTURE BEHAVIOR OF SHELL_WASHMACHINE ISTYPE type_sreg IS (dry,ready,rinse,waitup,wash);SIGNAL sreg, next_sreg : type_sreg;SIGNAL next_ken,next_modeout0,next_modeout1,next_modeout2,next_sel,next_ten,next_tstop,next_wout0,next_wout1,next_wout2 : std_logic;SIGNAL modeout : s

7、td_logic_vector (2 DOWNTO 0);SIGNAL wout : std_logic_vector (2 DOWNTO 0);BEGINPROCESS (CLK, stop, next_sreg, next_ken, next_sel, next_ten, next_tstop, next_modeout2, next_modeout1, next_modeout0, next_wout2, next_wout1, next_wout0)BEGINIF ( stop='1' ) THENsreg <= ready;sel <= '0

8、9;ken <= '1'ten <= '1'tstop <= '1'modeout2 <= '0'modeout1 <= '0'modeout0 <= '0'wout2 <= '0'wout1 <= '0'wout0 <= '0'ELSIF CLK='1' AND CLK'event THENsreg <= next_sreg;ken <= next_ken;se

9、l <= next_sel;ten <= next_ten;tstop <= next_tstop;modeout2 <= next_modeout2;modeout1 <= next_modeout1;modeout0 <= next_modeout0;wout2 <= next_wout2;wout1 <= next_wout1;wout0 <= next_wout0;END IF;END PROCESS;PROCESS (sreg,modein0,modein1,modein2,pause,start,tcin,modeout,wou

10、t)BEGINnext_ken <= '0' next_modeout0 <= '0' next_modeout1 <= '0' next_modeout2 <= '0' next_sel <= '0' next_ten <= '0' next_tstop <= '0' next_wout0 <= '0' next_wout1 <= '0' next_wout2 <= '0'

11、modeout<=std_logic_vector'("000"); wout<=std_logic_vector'("000"); next_sreg<=dry;CASE sreg ISWHEN dry =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<=

12、'1'modeout <= (std_logic_vector'("011");wout <= (std_logic_vector'("100");END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0'next_tstop<='0'next_ken<='0'next_sel<='1'modeout

13、<= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1'next_sel<='0'modeout <= (std_logic_vector'("000&quo

14、t;);wout <= (std_logic_vector'("000");END IF;WHEN ready =>IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( start='0' ) THENnext_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1'next_sel<='0&#

15、39;modeout <= (std_logic_vector'("000");wout <= (std_logic_vector'("000");END IF;IF ( modein0='1' AND modein1='1' AND modein2='0' AND start='1' ) THENnext_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken<=

16、9;0'next_sel<='1'modeout <= (std_logic_vector'("011");wout <= (std_logic_vector'("100");END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND start='1' ) THENnext_sreg<=rinse;next_ten<='1'next_tstop&

17、lt;='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("010");wout <= (std_logic_vector'("010");END IF;IF ( modein0='1' AND modein1='0' AND modein2='0' AND start='1' ) THENnext_sreg<=wash;next_

18、ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;WHEN rinse =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=rinse;next_ten&

19、lt;='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("010");wout <= (std_logic_vector'("010");END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0'next

20、_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1&

21、#39;next_sel<='0'modeout <= (std_logic_vector'("000");wout <= (std_logic_vector'("000");END IF;WHEN waitup =>IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( pause='1' ) THENnext_sreg<=waitup;next_ten<=&#

22、39;0'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( modein0='1' AND modein1='1' AND modein2='0' AND pause='0' ) THENnext

23、_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("011");wout <= (std_logic_vector'("100");END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND

24、 pause='0' ) THENnext_sreg<=rinse;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("010");wout <= (std_logic_vector'("010");END IF;IF ( modein0='1' AND modein1='0&#

25、39; AND modein2='0' AND pause='0' ) THENnext_sreg<=wash;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;WHEN wash =>

26、IF ( pause='0' AND tcin='0' ) THENnext_sreg<=wash;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;IF ( tcin='0'

27、 AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( tcin='1' ) THENnext_sreg<

28、;=ready;next_ten<='1'next_tstop<='1'next_ken<='1'next_sel<='0'modeout <= (std_logic_vector'("000");wout <= (std_logic_vector'("000");END IF;WHEN OTHERS =>END CASE;next_modeout2 <= modeout(2);next_modeout1 <= modeo

29、ut(1);next_modeout0 <= modeout(0);next_wout2 <= wout(2);next_wout1 <= wout(1);next_wout0 <= wout(0);END PROCESS;END BEHAVIOR;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY WASHMACHINE ISPORT (modein : IN std_logic_vector (2 DOWNTO 0);modeout : OUT std_logic_vector (2 DOWNTO 0);wout : OU

30、T std_logic_vector (2 DOWNTO 0);CLK,pause,start,stop,tcin: IN std_logic;ken,sel,ten,tstop : OUT std_logic);END;ARCHITECTURE BEHAVIOR OF WASHMACHINE ISCOMPONENT SHELL_WASHMACHINEPORT (CLK,modein0,modein1,modein2,pause,start,stop,tcin: IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wo

31、ut1,wout2 : OUT std_logic);END COMPONENT;BEGINSHELL1_WASHMACHINE : SHELL_WASHMACHINE PORT MAP (CLK=>CLK,modein0=>modein(0),modein1=>modein(1),modein2=>modein(2),pause=>pause,start=>start,stop=>stop,tcin=>tcin,ken=>ken,modeout0=>modeout(0),modeout1=>modeout(1),modeout

32、2=>modeout(2),sel=>sel,ten=>ten,tstop=>tstop,wout0=>wout(0),wout1=>wout(1),wout2=>wout(2);END BEHAVIOR; 2 定時(shí)器： library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dingshi is port(clk,ten,tstop:in std_logic; ims:in std_logic_vector(3 downto 0); iss:in

33、std_logic_vector(3 downto 0); img:in std_logic_vector(3 downto 0); isg:in std_logic_vector(3 downto 0); cin:out std_logic; omg, osg:buffer std_logic_vector(3 downto 0); oms:buffer std_logic_vector(3 downto 0); oss:buffer std_logic_vector(3 downto 0) ); end; architecture cml of dingshi isbegin PROCES

34、S(clk, ten, tstop) BEGIN IF ten='1' THEN IF tstop='1' THEN osg<=isg; ELSIF clk'EVENT AND clk='1' THEN IF osg="0000" THEN IF oss>"0000" OR omg>"0000" OR oms>"0000" THEN osg<="1001" ELSE osg<="0000&quo

35、t; END IF; ELSE osg<=osg-1; END IF; END IF; END IF; END PROCESS; PROCESS(clk, ten, tstop, osg) BEGIN IF ten='1' THEN IF tstop='1' THEN oss<=iss; ELSIF clk'EVENT AND clk='1' THEN IF osg="0000" THEN IF oss=0 THEN IF omg>"0000" OR oms>"00

36、00" THEN oss<="0101" ELSE oss<="0000" END IF; ELSE oss<=oss-1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(clk, ten, tstop, osg, oss) BEGIN IF ten='1' THEN IF tstop='1' THEN omg<=img; ELSIF clk'EVENT AND clk='1' THEN IF oss=0

37、and osg=0 THEN IF omg=0 THEN IF oms>0 THEN omg<="1001" ELSE omg<="0000" END IF; ELSE omg<=omg-1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(clk, ten, tstop, osg, oss, omg) BEGIN IF ten='1' THEN IF tstop='1' THEN oms<=ims; ELSIF clk'EVE

38、NT AND clk='1' THEN IF omg=0 and osg=0 and oss=0 THEN IF oms=0 THEN oms<="0000" ELSE oms<=oms-1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(clk, ten, tstop, osg, oss, omg, oms) BEGIN IF ten='1' THEN IF tstop='0' THEN IF clk'EVENT AND clk='1&#

39、39; THEN IF oms=0 AND omg=0 AND oss=0 AND osg=1 THEN cin<='1' ELSE cin<='0' END IF; END IF; END IF; END IF; END PROCESS; END cml; 3.時(shí)間設(shè)置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key ISport( kin: in std_logic; ken: in std_logic; ims,iss,img

40、,isg: buffer std_logic_vector(3 downto 0); end key;ARCHITECTURE cml OF key ISBEGIN PROCESS(kin, ken) BEGIN IF ken='1' THEN IF kin'EVENT AND kin='1' THEN IF isg="1001" THEN isg<="0000" ELSE isg<=isg+1; END IF; END IF; END IF; END PROCESS; PROCESS(kin, ken

41、, isg) BEGIN IF ken='1' THEN IF kin'EVENT AND kin='1' THEN IF isg=9 THEN IF iss="0101" THEN iss<="0000" ELSE iss<=iss+1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(kin, ken, isg, iss) BEGIN IF ken='1' THEN IF kin'EVENT AND kin='

42、1' THEN IF iss="0101" AND isg="1001" THEN IF img="1001" THEN img<="0000" ELSE img<=img+1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(kin, ken, isg, iss, img) BEGIN IF ken='1' THEN IF kin'EVENT AND kin='1' THEN IF img=&qu

43、ot;1001" AND iss="0101" AND isg="1001" THEN IF ims="0010" THEN ims<="0000" ELSE ims<=ims+1; END IF; END IF; END IF; END IF; END PROCESS; END cml;4.模式設(shè)置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mode isport(kin :in std_logic;ken :in std_logic;modeset:buffer std_logic_vector(2 downto 0);LED:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);end mode;architecture cml of mode issignal a: std_logic_vector(2