中科院研究生院課程VLSI測(cè)試與可測(cè)試性設(shè)計(jì)

1、EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論11中科院研究生院課程：VLSI測(cè)試與可測(cè)試性設(shè)計(jì) 預(yù)講 課程簡介李曉維中科院計(jì)算技術(shù)研究所Email: http:/EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論22基本目的1. 使學(xué)生掌握VLSI系統(tǒng)測(cè)試和可測(cè)性設(shè)計(jì)的基本原理和主要方法；2. 使學(xué)生把握VLSI系統(tǒng)測(cè)試和可測(cè)性設(shè)計(jì)的學(xué)科前沿方向；3. 使學(xué)生對(duì)EDA系統(tǒng)中有關(guān)測(cè)試和可測(cè)性設(shè)計(jì)工具有初步認(rèn)識(shí)和實(shí)踐體會(huì)；4. 使學(xué)生能夠在與VLSI測(cè)試相關(guān)的學(xué)術(shù)研究和應(yīng)用開發(fā)中直接發(fā)揮作用。EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論331.L.-T. Wang, C-W Wu, X-Q Wen, V

2、LSI TEST PRINCIPLES AND ARCHITECTURES Design for Testability Elsevier Morgan Kaufmann Publishers, 2006.2.M.L.Bushnell and V.D.Agrawal, ESSENTIAL OF ELECTRONIC TESTING for Digital Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000. 3.M.Abramovici, M.A.Breuer, A.D.Friedman,Digital

3、 Systems Testing and Testable Design, Computer Science Press, 1995.參考書EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論44國際學(xué)術(shù)刊物（/）1 IEEE Transactions on Computers2 IEEE Transactions of Computer Aided Design of Integrated Circuits and Systems4 IEEE Design and Test of Computers5 Journal of Electronic Testing:

4、Theory and Applications3 IEEE Transactions on VLSI Systems主要文獻(xiàn)出處EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論55國際學(xué)術(shù)會(huì)議（/tttc）1 IEEE International Test Conference (ITC)2 IEEE VLSI Test Symposium (VTS)3 IEEE Asian Test Symposium (ATS)4 IEEE Design Automation and Test in Europe (DATE)5 ACM/IEEE Design Automa

5、tion Conference (DAC)6 IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)主要文獻(xiàn)出處EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論66國內(nèi)學(xué)術(shù)刊物/會(huì)議1 中國科學(xué)3 計(jì)算機(jī)學(xué)報(bào)4 計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào)5 計(jì)算機(jī)研究與發(fā)展2 電子學(xué)報(bào)2+ Chinese Journal of Electronics3+ Journal of Computer Science and Technology6 全國測(cè)試學(xué)術(shù)會(huì)議（論文集）7 全國容錯(cuò)計(jì)算學(xué)術(shù)會(huì)議（論文集）主要文獻(xiàn)出處EE1

6、41VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論77教學(xué)安排課次內(nèi)容教材教師日期第1講VLSI測(cè)試技術(shù)導(dǎo)論第1章李曉維2007-09-10第2講可測(cè)試性設(shè)計(jì)(1)第2章李曉維2007-09-17第3講可測(cè)試性設(shè)計(jì)(2)第2章李曉維2007-09-24第4講邏輯與故障模擬第3章李曉維2007-10-08第5講測(cè)試生成(1)第4章李曉維2007-10-15第6講測(cè)試生成(2)第4章李曉維2007-10-29第7講邏輯自測(cè)試(1)第5章李曉維2007-11-05第8講邏輯自測(cè)試(2)第5章李曉維2007-11-12第9講測(cè)試壓縮第6章李曉維2007-11-19第10講邏輯診斷第7章李曉維2007-11-26第

7、11講存儲(chǔ)器測(cè)試與BIST第8章李曉維2007-12-03第12講存儲(chǔ)器診斷與BISR第9章李曉維2007-12-10第13講邊界掃描與SoC測(cè)試第10章李曉維2007-12-17第14講納米電路測(cè)試技術(shù)第12章李曉維2007-12-24考試課堂開卷2008-01-07EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論88q教學(xué)方式：課堂講授14次；每次講2學(xué)時(shí)/討論1學(xué)時(shí)；講義在網(wǎng)站發(fā)布；期末復(fù)習(xí)1次。q考核方式：1篇課程論文：40%1次期末考試/課堂開卷：60%教學(xué)/考核EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論99SpecificationSpecificationWafertesting網(wǎng)

8、表網(wǎng)表Technical dependentimplementationTechnical dependentimplementationLogic simulationATPGfault simulationLogicdesignWaferWaferIC chipIC chipICtestingPCBPCBLayoutSystemSystemSystemtestingPCBtestingFoundryTest dataTest dataATEprobefixtureDesign vs. TestEE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論1010Design, Verification an

9、d Test高級(jí)綜合邏輯綜合模擬故障診斷設(shè)計(jì)驗(yàn)證SynopsysMAGMACadenceMentor GraphicsASIC設(shè)計(jì)Compass EDA算法研究數(shù)值計(jì)算較少，搜索問題較多，大部分為NP完全問題;算法復(fù)雜性要求高；需要啟發(fā)式方法和經(jīng)驗(yàn)。 EDA系統(tǒng)設(shè)計(jì)、工具開發(fā)EDA系統(tǒng)占世界軟件市場(chǎng)份額的10%左右。 EDA庫開發(fā) 電路設(shè)計(jì)使用EDA工具和單元庫。針對(duì)不同工藝，開發(fā)相應(yīng)單元庫。EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論1111Verification in CPU Design邏輯描述版圖描述RTL描述C模擬器體系結(jié)構(gòu)設(shè)計(jì)RTL設(shè)計(jì)邏輯設(shè)計(jì)物理設(shè)計(jì)邏輯描述DFT設(shè)計(jì)芯片流片/

10、封裝/測(cè)試系統(tǒng)系統(tǒng)驗(yàn)證驗(yàn)證RTLRTL驗(yàn)證驗(yàn)證邏輯邏輯驗(yàn)證驗(yàn)證版圖版圖驗(yàn)證驗(yàn)證DFTDFT驗(yàn)證驗(yàn)證EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論1212Testing as Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(fail test) = lowProb(pass test) = lowMostlygoodchipsMostlybadchipsEE141VLSI測(cè)試與可測(cè)試

11、性設(shè)計(jì)課程導(dǎo)論1313Costs of TestingqDesign for testability (DFT) Chip area overhead and yield reduction Performance overheadqSoftware processes of test Test generation and fault simulation Test programming and debuggingqManufacturing test Automatic test equipment (ATE) capital cost Test center operational c

12、ost EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論1414兆 220 106 MHz MegaHz吉 230 109 GHz GigaHz千 210 103 KHz KiloHz太 240 1012 THz TeraHzmm millimetre 毫 2-10 10-3 ms millisecondm micrometre 微 2-20 10-6 s microsecond nm nerometre 納 2-30 10-9 ns nerosecomdpm picometre 皮 2-40 10-12 ps picosecond度量單位EE141VLSI測(cè)試與可測(cè)試性設(shè)計(jì)課程導(dǎo)論1515Rol

13、es of TestingqDetection: Determination whether or not the device under test (DUT) has some fault.qDiagnosis: Identification of a specific fault that is present on DUT.qDevice characterization: Determination and correction of errors in design and/or test procedure.qFailure mode analysis (FMA): Determination of manufacturing process errors that