數(shù)字邏輯課程設(shè)計(jì)---基于FPGA的簡(jiǎn)單運(yùn)算器

1、洛陽(yáng)理工學(xué)院課程設(shè)計(jì)報(bào)告課程名稱脈沖與數(shù)字電路設(shè)計(jì)題目簡(jiǎn)單運(yùn)算器專業(yè)通信工程班級(jí)學(xué)號(hào)姓名完成日期2012年06月12日課程設(shè)計(jì)任務(wù)書設(shè)計(jì)題目：基于FPGA的簡(jiǎn)單運(yùn)算器設(shè)計(jì)內(nèi)容：運(yùn)用可編程軟件設(shè)計(jì)一個(gè)簡(jiǎn)單的運(yùn)算器，首先設(shè)計(jì)原理圖，并用Quartusii完成原理圖繪制，或編寫VHDL程序，調(diào)試電路或程序，下載到實(shí)驗(yàn)箱設(shè)計(jì)要求：該運(yùn)算器能完成-7到+7的簡(jiǎn)單的加、減、與、異或四種運(yùn)算功能，并且可以對(duì)溢出的結(jié)果進(jìn)行修正。指導(dǎo)教師：2012年06月04日課程設(shè)計(jì)評(píng)語(yǔ)：成績(jī)指導(dǎo)教師：_年月日運(yùn)算器摘要設(shè)計(jì)一個(gè)簡(jiǎn)單運(yùn)算器。由頂層電路、運(yùn)算器、按鍵輸入、控制信號(hào)產(chǎn)生、修正結(jié)果、顯示等模塊構(gòu)成。用Quartus

2、 II繪制原理圖或編寫VHDL程序，然后封裝畫出電路圖，該簡(jiǎn)單運(yùn)算器可以實(shí)現(xiàn)加、減法算數(shù)運(yùn)算和與、異或邏輯運(yùn)算，且該運(yùn)算器設(shè)計(jì)完之后經(jīng)過了Quartus II軟件和FPGA實(shí)驗(yàn)板的下載驗(yàn)證。關(guān)鍵詞:運(yùn)算器，Quartus II，VHDL程序35數(shù)字邏輯課程設(shè)計(jì)報(bào)告目錄第一章系統(tǒng)原理81.1系統(tǒng)功能81.2系統(tǒng)原理圖91.3電路設(shè)計(jì)原理9第二章系統(tǒng)組成102.1按鍵模塊102.1.1按鍵模塊VHDL程序102.1.2按鍵模塊仿真波形142.1.3按鍵模塊電路封裝圖152.1.4按鍵模塊功能152.2控制信號(hào)產(chǎn)生模塊152.2.1控制模塊VHDL程序152.2.2控制模塊仿真波形182.2.3控制

3、模塊電路封裝圖182.2.4控制模塊功能192.3修正模塊192.3.1修正模塊VHDL程序192.3.2修正模塊仿真波形232.3.3修正模塊電路封裝圖232.3.4修正模塊功能242.4顯示模塊242.4.1顯示模塊VHDL程序242.4.2顯示模塊電路封裝圖272.4.3顯示模塊功能282.5運(yùn)算器模塊282.5.1運(yùn)算器模塊功能282.5.2運(yùn)算器模塊電路圖28第三章定制選擇器293.1定制選擇器293.2用VHDL符號(hào)圖畫運(yùn)算器頂層電路圖31第四章下載驗(yàn)證及調(diào)試334.1器件選擇及引腳設(shè)置334.2配置文件下載34結(jié)論35參考文獻(xiàn)36前言隨著FPGA性能的不斷完善，F(xiàn)PGA器件的種類

4、日益豐富，受到世界范圍內(nèi)電子設(shè)計(jì)人員的普遍歡迎，并占據(jù)了較大的市場(chǎng)，其生產(chǎn)廠家也由原來的Xilinx公司一家增加到Altera、Actel、lattice等十幾家公司。Altera公司的主要產(chǎn)品有：屬于FPGA的FLEX、ACEX、APEX、Mercury、Excalibur、Stratix和Cyclone等系列；屬于CPLD的MAX和Classic系列。開發(fā)工具有，被普遍認(rèn)為是最優(yōu)秀PLD 開發(fā)平臺(tái)之一的MAX+Plus II和支持APEX、Mercury、Excalibur、Stratix和Cyclone系列器件的Quartus II開發(fā)軟件。Cyclone系列器件是Altera公司推出的

5、低價(jià)位FPGA產(chǎn)品，是Stratix系列的簡(jiǎn)化版，分為Cyclone I和Cyclone II兩個(gè)系列。Cyclone I系列產(chǎn)品為基于1.5V、采用0.13um全銅SRAM工藝的低成本FPGA。Cyclone II 系列產(chǎn)品基于1.2V，采用0.09um全銅CMOS工藝，SRAM編程技術(shù)，其成本更低、容量更高、速度更快。它和高性能的Stratix II系列的FPGA是目前Altera公司主流產(chǎn)品。我的簡(jiǎn)單運(yùn)算器主要是用VHDL語(yǔ)言編寫，以Cyclone器件為依托，并下載到Altera仿真工具箱Cyclone-EP1C6Q240C8驗(yàn)證功能成功，能夠初步完成簡(jiǎn)單運(yùn)算器的雛形。隨著大規(guī)模集成電路

6、技術(shù)和計(jì)算機(jī)技術(shù)的高速發(fā)展，在涉及通信、國(guó)防、工業(yè)自動(dòng)化、計(jì)算機(jī)設(shè)計(jì)與應(yīng)用、儀器儀表等領(lǐng)域的電子系統(tǒng)設(shè)計(jì)工作中，F(xiàn)PGA技術(shù)的含量正以驚人的速度提升。電子類的新技術(shù)項(xiàng)目的開發(fā)也更多地依賴于FPGA技術(shù)的應(yīng)用，特別是隨著HDL等硬件描述語(yǔ)言綜合功能和性能的提高，計(jì)算機(jī)中許多重要的元件（包括CPU）都用硬件描述語(yǔ)言來設(shè)計(jì)和表達(dá)，許多微機(jī)CPU、硬核嵌入式系統(tǒng)（如ARM、MIPS）、軟核嵌入式系統(tǒng)（如NiosII）、大型CPU，乃至整個(gè)計(jì)算機(jī)系統(tǒng)都用FPGA來實(shí)現(xiàn)，即所謂的單片系統(tǒng)SOC或SOPC(System On a Chip、System On a Programmerable Chip)。計(jì)

7、算機(jī)和CPU的設(shè)計(jì)技術(shù)及其實(shí)現(xiàn)途徑進(jìn)入了一個(gè)全新的時(shí)代！不但如此，傳統(tǒng)的CPU結(jié)構(gòu)模式，如馮諾依曼結(jié)構(gòu)和哈佛結(jié)構(gòu)正在接受巨大的挑戰(zhàn)。例如美國(guó)Wincom Systems 公司推出一款令人驚嘆的服務(wù)器，其核心部分是由FPGA完成的超強(qiáng)功能CPU。該系統(tǒng)工作能力超過50臺(tái)DELL或IBM計(jì)算機(jī)，或SUN Microsystems 公司的服務(wù)器。該服務(wù)器的處理速度要比傳統(tǒng)服務(wù)器快50到300倍。我們知道，傳統(tǒng)的PC機(jī)及服務(wù)器通常采用諸如Intel公司的奔騰處理器或SUN公司的SPARC芯片作為中央處理單元，而Wincom Systems的這款產(chǎn)品卻沒有采用微處理器，而是由FPGA芯片驅(qū)動(dòng)。FPGA芯

8、片的運(yùn)行速度雖比奔騰處理器慢，但可并行處理多項(xiàng)任務(wù)，而微處理器一次僅能處理一項(xiàng)任務(wù)。因此，Wincom Systems的服務(wù)器只需配置幾個(gè)價(jià)格僅為2000多美元的FPGA芯片，便可擊敗SUN公司的服務(wù)器或采用Intel處理器的計(jì)算機(jī)。50多年前，匈牙利數(shù)學(xué)家馮諾依曼提出了計(jì)算機(jī)的設(shè)計(jì)構(gòu)想：通過中央處理器從儲(chǔ)存器中存取數(shù)據(jù)，并逐一處理各項(xiàng)任務(wù)。然而現(xiàn)在，卻采用FPGA取代傳統(tǒng)微處理器獲得了更高的性能，致使美國(guó)Xilinx公司的首席執(zhí)行官Willem Roelandts認(rèn)為：“由馮諾依曼提出的電腦架構(gòu)已經(jīng)走到盡頭”，“可編程芯片將掀起下一輪應(yīng)用高潮”。FPGA芯片操作靈活，可以重復(fù)擦寫無限次，而微

9、處理器均采用固定電路，只能進(jìn)行一次性設(shè)計(jì)。設(shè)計(jì)人員可通過改變FPGA中晶體管的開關(guān)狀態(tài)對(duì)電路進(jìn)行重寫，即重配置，從而盡管FPGA芯片的時(shí)鐘頻率要低于奔騰處理器，但是由于FPGA芯片可并行處理各種不同的運(yùn)算，所以可以完成許多復(fù)雜的任務(wù)。正如Willem Roelandts所說的，“我們認(rèn)為下一代超級(jí)電腦將基于可編程邏輯器件”，他聲稱，這種機(jī)器的功能比目前最大的超級(jí)電腦還要強(qiáng)大許多倍。EDA專家William Carter認(rèn)為，只要EDA開發(fā)工具的功能允許，將有無數(shù)的證據(jù)證明FPGA 具有這種神奇的能力，進(jìn)而實(shí)現(xiàn)基于FPGA的超級(jí)電腦的開發(fā)。此外，美國(guó)加州大學(xué)伯克利分校和楊百翰大學(xué)的研究人員也正在

10、設(shè)計(jì)基于FPGA的電腦，這些電腦可在運(yùn)行中實(shí)現(xiàn)動(dòng)態(tài)重配置。這對(duì)定位危險(xiǎn)目標(biāo)等軍事應(yīng)用和面容識(shí)別之類的計(jì)算密集型安全應(yīng)用十分有用。由此看來，在計(jì)算機(jī)應(yīng)用領(lǐng)域和計(jì)算機(jī)系統(tǒng)設(shè)計(jì)領(lǐng)域中，EDA技術(shù)和FPGA的應(yīng)用方興未艾！硬件描述語(yǔ)言HDL(Hardware Description Language)是EDA技術(shù)的另一重要組成部分，常見的HDL有：VHDL、Verilog HDL、System Verilog和SystemC。其中VHDL、Verilog在現(xiàn)在EDA設(shè)計(jì)中使用最多，也得到幾乎所有的主流EDA工具的支持。而后兩種HDL 語(yǔ)言尚處于完善過程中。VHDL語(yǔ)言具有很強(qiáng)的電路描述和建模能力，能從

11、多個(gè)層次對(duì)數(shù)字系統(tǒng)進(jìn)行建模和描述，從而大大簡(jiǎn)化了硬件設(shè)計(jì)任務(wù)，提高了設(shè)計(jì)效率和可靠性。VHDL具有與具體硬件電路無關(guān)和與設(shè)計(jì)平臺(tái)無關(guān)的特性，并且具有良好的電路行為描述和系統(tǒng)描述能力，在語(yǔ)言易讀性和層次化結(jié)構(gòu)設(shè)計(jì)方面表現(xiàn)了強(qiáng)大的生命力和應(yīng)用潛力。因此，VHDL支持各種模式的設(shè)計(jì)方法：自頂向下與自底向上或混合方法，在面對(duì)當(dāng)今許多電子產(chǎn)品生命周期縮短，需要多次重新設(shè)計(jì)以融入最新技術(shù)、改變工藝等方面， VHDL都表現(xiàn)了良好的適應(yīng)性。第一章系統(tǒng)原理1.1系統(tǒng)功能該系統(tǒng)是基于FPGA設(shè)計(jì)的簡(jiǎn)單運(yùn)算器，可以實(shí)現(xiàn)簡(jiǎn)單的-7到+7范圍內(nèi)的加、減、與、以及異或四則運(yùn)算。將設(shè)計(jì)好的系統(tǒng)電路圖與硬件實(shí)驗(yàn)板相連接，進(jìn)行

12、運(yùn)算驗(yàn)證。該實(shí)驗(yàn)板由一個(gè)8按鍵電路和一個(gè)32位LCD顯示器組成，通過相應(yīng)的按鍵輸入把運(yùn)算結(jié)果顯示在LCD顯示器上。1.2系統(tǒng)原理圖1.3電路設(shè)計(jì)原理該運(yùn)算器電路由按鍵輸入、控制、修正、顯示和運(yùn)算五大模塊組成，來實(shí)現(xiàn)加、減、與、異或運(yùn)算功能。首先按鍵模塊用于輸入兩個(gè)數(shù)和運(yùn)算符，通過控制模塊傳送到運(yùn)算器模塊進(jìn)行運(yùn)算，再連接到修正模塊，通過修正模塊對(duì)“溢出”的數(shù)值進(jìn)行修正，最后顯示模塊功能實(shí)現(xiàn)把運(yùn)算過程反應(yīng)到LCD顯示器上。第二章系統(tǒng)組成2.1按鍵模塊2.1.1按鍵模塊VHDL程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_

13、ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY KEY ISPORT(EN:OUT STD_LOGIC;YSF:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);RSTN,CLK:IN STD_LOGIC;KEYA,KEYB:IN STD_LOGIC;KADD,KSUB,KAND,KXOR,KEQU:IN STD_LOGIC;A,B,C,D:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);XSYSF:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);XA,XB:OUT STD_LOGIC_VEC

14、TOR(7 DOWNTO 0);END KEY;ARCHITECTURE ARCH OF KEY ISSIGNAL TKADD,TKSUB,TKAND,TKXOR,TKEQU :STD_LOGIC;SIGNAL TA,TB:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN-保存A-PROCESS (KEYA,RSTN)BEGINIF RSTN='0' THEN TA<="0000"ELSIF (KEYA'EVENT AND KEYA='1')THENTA<=TA+1;END IF;END PROCESS

15、;-保存B-PROCESS (KEYB,RSTN)BEGINIF RSTN='0' THEN TB<="0000"ELSIF(KEYB'EVENT AND KEYB='1')THENTB<=TB+1;END IF;END PROCESS;-獲取信號(hào)-PROCESS(RSTN,KADD)BEGIN IF RSTN='0' THEN TKADD<='0'ELSIF (KADD'EVENT AND KADD='1')THEN TKADD<='1'

16、END IF;END PROCESS;-PROCESS(RSTN,KSUB)BEGIN IF RSTN='0' THEN TKSUB<='0'ELSIF (KSUB'EVENT AND KSUB='1')THEN TKSUB<='1'END IF;END PROCESS;-PROCESS(RSTN,KAND)BEGIN IF RSTN='0' THEN TKAND<='0'ELSIF (KAND'EVENT AND KAND='1')THEN TKA

17、ND<='1'END IF;END PROCESS;PROCESS(RSTN,KXOR)BEGIN IF RSTN='0' THEN TKXOR<='0'ELSIF (KXOR'EVENT AND KXOR='1')THEN TKXOR<='1'END IF;END PROCESS;-PROCESS(RSTN,KEQU)BEGIN IF RSTN='0' THEN TKEQU<='0'ELSIF (KEQU'EVENT AND KEQU=

18、9;1')THEN TKEQU<='1'END IF;END PROCESS;PROCESS(RSTN,CLK,TKADD,TKSUB,TKAND,TKXOR,TKEQU,TA,TB)BEGINIF RSTN='0' THEN YSF<="00"EN<='0'XSYSF<="00100000"ELSIF(CLK'EVENT AND CLK='1') THENIF TKADD='1' THEN YSF<="00"

19、XSYSF<="00101011"A<=TA;B<=TB;END IF;IF TKSUB='1' THEN YSF<="01"XSYSF<="00101101"A<=TA;B<=TB;END IF;IF TKAND='1' THEN YSF<="10"XSYSF<="00101010"A<=TA;C<=TB;END IF;IF TKEQU='1' THEN EN<='1

20、'END IF;END IF;END PROCESS;PROCESS(TA,TB,CLK)BEGINIF(CLK'EVENT AND CLK='1')THENCASE TA ISWHEN "0000"=>XA<="00110000"WHEN "0001"=>XA<="00110001"WHEN "0010"=>XA<="00110010"WHEN "0011"=>XA<=&qu

21、ot;00110011"WHEN "0100"=>XA<="00110100"WHEN "0101"=>XA<="00110101"WHEN "0110"=>XA<="00110110"WHEN "0111"=>XA<="00110111"WHEN "1000"=>XA<="00111000"WHEN "1001&qu

22、ot;=>XA<="00111001"WHEN "1010"=>XA<="01000001"WHEN "1011"=>XA<="01000010"WHEN "1100"=>XA<="01000011"WHEN "1101"=>XA<="01000100"WHEN "1110"=>XA<="01000101"

23、WHEN "1111"=>XA<="01000110"WHEN OTHERS =>NULL;END CASE;CASE TB ISWHEN "0000"=>XB<="00110000"WHEN "0001"=>XB<="00110001"WHEN "0010"=>XB<="00110010"WHEN "0011"=>XB<="00110011

24、"WHEN "0100"=>XB<="00110100"WHEN "0101"=>XB<="00110101"WHEN "0110"=>XB<="00110110"WHEN "0111"=>XB<="00110111"WHEN "1000"=>XB<="00111000"WHEN "1001"=>XB&

25、lt;="00111001"WHEN "1010"=>XB<="01000001"WHEN "1011"=>XB<="01000010"WHEN "1100"=>XB<="01000011"WHEN "1101"=>XB<="01000110"WHEN "1110"=>XB<="01000101"WHEN "

26、1111"=>XB<="01000110"WHEN OTHERS=>NULL;END CASE;END IF;END PROCESS;END ARCH;2.1.2按鍵模塊仿真波形2.1.3按鍵模塊電路封裝圖2.1.4按鍵模塊功能實(shí)現(xiàn)對(duì)按鍵的設(shè)定及控制，得以把運(yùn)算數(shù)據(jù)輸入電路。2.2控制信號(hào)產(chǎn)生模塊2.2.1控制模塊VHDL程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CP3

27、 ISPORT(RSTN,CLK:IN STD_LOGIC; CP,CPT,CPMUX:BUFFER STD_LOGIC; SADD,SSUB,SAND,SXOR:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);END CP3;ARCHITECTURE BEHAVIORAL OF CP3 ISTYPE STATE1 IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11);SIGNAL PRES1,NXS1:STATE1;TYPE STATE2 IS(SS0,SS1,SS2,SS3);SIGNAL PRES2,NXS2:STATE2;BEGINPRO

28、CESS(CLK,RSTN)BEGINIF (RSTN='0')THEN PRES1<=S0;ELSIF(CLK'EVENT AND CLK='1')THEN PRES1<=NXS1;END IF;END PROCESS;PROCESS(PRES1)BEGINCASE PRES1 IS WHEN S0=>CP<='1'CPMUX<='0'CPT<='0'NXS1<=S1; WHEN S1=> CP<='0'CPMUX<='0

29、'CPT<='0'NXS1<=S2; WHEN S2=>CP<='0'CPMUX<='1'CPT<='0'NXS1<=S3; WHEN S3=> CP<='1'CPMUX<='1'CPT<='0'NXS1<=S4; WHEN S4=>CP<='1'CPMUX<='0'CPT<='0'NXS1<=S5; WHEN S5=>

30、CP<='0'CPMUX<='0'CPT<='0'NXS1<=S6; WHEN S6=>CP<='0'CPMUX<='1'CPT<='0'NXS1<=S7; WHEN S7=>CP<='1'CPMUX<='1'CPT<='0'NXS1<=S8; WHEN S8=> CP<='1'CPMUX<='1'CPT<=

31、9;0'NXS1<=S9; WHEN S9=>CP<='0'CPMUX<='1'CPT<='1'NXS1<=S10; WHEN S10=>CP<='0'CPMUX<='1'CPT<='1'NXS1<=S11; WHEN S11=>CP<='1'CPMUX<='1'CPT<='1'NXS1<=S11; END CASE;END PROCESS;PROC

32、ESS(CP,RSTN)BEGINIF (RSTN='0')THEN PRES2<=SS0;ELSIF(CP'EVENT AND CP='0')THEN PRES2<=NXS2;END IF;END PROCESS;PROCESS(PRES2)BEGINCASE PRES2 IS WHEN SS0=> SADD<="00"SSUB<="00"SAND<="00"SXOR<="00" NXS2<=SS1; WHEN SS1=>

33、; SADD<="01"SSUB<="00"SAND<="00"SXOR<="00" NXS2<=SS2; WHEN SS2=> SADD<="00"SSUB<="01"SAND<="10"SXOR<="11" NXS2<=SS3; WHEN SS3=> SADD<="00"SSUB<="01"SAND<=&

34、quot;10"SXOR<="11" NXS2<=SS3;END CASE;END PROCESS;END BEHAVIORAL;2.2.2控制模塊仿真波形2.2.3控制模塊電路封裝圖2.2.4控制模塊功能實(shí)現(xiàn)對(duì)電路運(yùn)算的控制。2.3修正模塊2.3.1修正模塊VHDL程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XZJG ISPORT(RSTN:IN STD_LOGIC; S:I

35、N STD_LOGIC_VECTOR(1 DOWNTO 0); CLK,OVER,COUT:IN STD_LOGIC; T:IN STD_LOGIC_VECTOR(3 DOWNTO 0); FH:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); SH,SL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END XZJG;ARCHITECTURE BEHAVIORAL OF XZJG ISSIGNAL OC:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL TH,TL:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN

36、PROCESS(RSTN,CLK,OVER,COUT)BEGINIF(CLK'EVENT AND CLK='1')THENOC<=OVER&COUT;END IF;END PROCESS;PROCESS(OC,CLK)BEGINIF(RSTN='0')THENTH<="0000"TL<="0000"ELSIF(CLK'EVENT AND CLK='1')THEN CASE OC IS WHEN"00"=>TH<="0000&

37、quot;CASE T I WHEN"0000"=>TL<="0000"FH<="00101011" WHEN"0001"=>TL<="0001"FH<="00101011" WHEN"0010"=>TL<="0010"FH<="00101011" WHEN"0011"=>TL<="0011"FH<=&qu

38、ot;00101011" WHEN"0100"=>TL<="0100"FH<="00101011" WHEN"0101"=>TL<="0101"FH<="00101011" WHEN"0110"=>TL<="0110"FH<="00101011" WHEN"0111"=>TL<="0111"FH<

39、="00101011" WHEN"1000"=>TL<="1000"FH<="01011101"WHEN"1001"=>TL<="0111"FH<="00101101" WHEN"1010"=>TL<="0110"FH<="00101101" WHEN"1011"=>TL<="0101"FH&

40、lt;="00101101" WHEN"1100"=>TL<="0100"FH<="00101101" WHEN"1101"=>TL<="0011"FH<="00101101" WHEN"1110"=>TL<="0010"FH<="00101101" WHEN"1111"=>TL<="0001"

41、;FH<="00101101" WHEN OTHERS=>NULL; END CASE;WHEN"01"=>TH<="0000"CASE T IS WHEN"0000"=>TL<="0000"FH<="00101011" WHEN"0001"=>TL<="0001"FH<="00101011" WHEN"0010"=>TL<=

42、"0010"FH<="00101011" WHEN"0011"=>TL<="0011"FH<="00101011" WHEN"0100"=>TL<="0100"FH<="00101011" WHEN"0101"=>TL<="0101"FH<="00101011" WHEN"0110"=>TL&

43、lt;="0110"FH<="00101011" WHEN"0111"=>TL<="0111"FH<="00101011" WHEN"1000"=>TL<="1000"FH<="00101101" WHEN"1001"=>TL<="0111"FH<="00101101" WHEN"1010"=>

44、;TL<="0110"FH<="00101101" WHEN"1011"=>TL<="0101"FH<="00101101" WHEN"1100"=>TL<="0100"FH<="00101101" WHEN"1101"=>TL<="0011"FH<="00101101" WHEN"1110"

45、=>TL<="0010"FH<="00101101" WHEN"1111"=>TL<="0001"FH<="00101101" WHEN OTHERS=>NULL; END CASE;WHEN"10"=>FH<="00101011" CASE T IS WHEN"1000"=>TH<="0000"TL<="1000" WHEN

46、"1001"=>TH<="0000"TL<="1001" WHEN"1010"=>TH<="0001"TL<="0000" WHEN"1011"=>TH<="0001"TL<="0001" WHEN"1100"=>TH<="0001"TL<="0010" WHEN"1101&q

47、uot;=>TH<="0001"TL<="0011" WHEN"1110"=>TH<="0001"TL<="0100" WHEN OTHERS=>NULL; END CASE;WHEN"11"=>FH<="00101101" CASE T IS WHEN"0000"=>TH<="0001"TL<="0110" WHEN&quo

48、t;0001"=>TH<="0001"TL<="0101" WHEN"0010"=>TH<="0001"TL<="0100" WHEN"0011"=>TH<="0001"TL<="0011" WHEN"0100"=>TH<="0001"TL<="0010" WHEN"0101"

49、=>TH<="0001"TL<="0001" WHEN"0110"=>TH<="0001"TL<="0000" WHEN"0111"=>TH<="0000"TL<="1001" WHEN OTHERS=>NULL; END CASE;END CASE;END IF;END PROCESS;PROCESS(RSTN,S,TH,TL,CLK)BEGINIF(RSTN='0&

50、#39;)THEN SH<="0000"SL<="0000"ELSIF(CLK'EVENT AND CLK='0')THEN CASE S IS WHEN"00"=>SH<=TH;SL<=TL;WHEN"01"=>SH<=TH;SL<=TL; WHEN"10"=>SH<="0000"SL<=T;WHEN"11"=>SH<="0000"S

51、L<=T; END CASE;END IF;END PROCESS;END BEHAVIORAL;2.3.2修正模塊仿真波形正溢出波形負(fù)溢出波形2.3.3修正模塊電路封裝圖2.3.4修正模塊功能實(shí)現(xiàn)對(duì)運(yùn)算中有超過7到7的溢出的結(jié)果進(jìn)行修正，方便讀取2.4顯示模塊2.4.1顯示模塊VHDL程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XIANSHI ISPORT(CLK:IN STD_LOGIC; R0:IN STD

52、_LOGIC_VECTOR(7 DOWNTO 0);R1,R2:IN STD_LOGIC_VECTOR(3 DOWNTO 0); R3,R4,R5:IN STD_LOGIC_VECTOR(7 DOWNTO 0);RS:BUFFER STD_LOGIC; RW:OUT STD_LOGIC; EN:OUT STD_LOGIC; CLK_OUT:BUFFER STD_LOGIC; D:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END XIANSHI;ARCHITECTURE BEHAVIORAL OF XIANSHI ISTYPE XIANSHI IS ARRAY(0

53、TO 31)OF STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL QX:XIANSHI:=(OTHERS=>"00100000");TYPE STATE IS(CLEAR,IDS,DLNF,DCB,DDRAM1,OUTDATA1,DDRAM2,OUTDATA2);SIGNAL COUNT:STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL LCLK_OUT:STD_LOGIC;SIGNAL COUNTS:INTEGER RANGE 0 TO 3000000:=0;SIGNAL CURRENT_STATE:STATE;SIG

54、NAL TEMPA:STD_LOGIC_VECTOR(4 DOWNTO 0):="00000"BEGINPROCESS(CLK_OUT,CLK)BEGINIF(RISING_EDGE(CLK)THEN COUNTS<=COUNTS+1;IF(COUNTS=3000000)THENCLK_OUT<=NOT CLK_OUT;END IF; END IF;END PROCESS;QX(2)<=R3;QX(3)<=R4;QX(4)<=R5;QX(5)<="00100000"QX(6)<=R0;QX(7)<=&quo

55、t;0011"&R1;QX(8)<="0011"&R2;PROCESS(CLK,LCLK_OUT)BEGINIF(RISING_EDGE(CLK)THEN COUNT<=COUNT+1;IF(COUNT=0)THEN LCLK_OUT<=NOT LCLK_OUT; END IF;END IF;END PROCESS;EN<=LCLK_OUT;PROCESS(LCLK_OUT,CURRENT_STATE) BEGIN IF RISING_EDGE(LCLK_OUT)THEN RS<='0'RW<=&

56、#39;0'CASE CURRENT_STATE ISWHEN CLEAR=> D<="00000001" CURRENT_STATE<=DLNF;WHEN DLNF=> D<="00111000" CURRENT_STATE<=IDS;WHEN IDS=> D<="00000110" CURRENT_STATE<=DCB; WHEN DCB=> D<="00001100" CURRENT_STATE<=DDRAM1;WHEN DDRAM1=>D<="10000000"+TEMPA(3 DOWNTO 0); CURRENT_STATE<=OUT