Xilinx-fpga-CPU架構-21-22

1、Xilinx ConfidentialXilinx-FPGA/PLD: PARWAN-1B603教室沈沛意、張亮沈沛意、張亮 西安電子科技大學-軟件學院西安電子科技大學-軟件學院Presentation Name 2圖 3. 1 自頂向下的設計輸入方式VHDL支持系統(tǒng)的層次結構設計，設計者可以由頂向下將系統(tǒng)劃分為多個層級，每個層級劃分多個子模塊，各個子模塊獨立設計、調試。子模塊設計完成后，將其互聯(lián)構成整個系統(tǒng)。層次結構的設計方法支持團隊協(xié)同工作，能夠在很大程度上提高設計效率，而且便于模塊的復用，便于系統(tǒng)的調試、維護和升級 - 可綜合的！可綜合的！Recap：層次化設計架構：層次化設計架構REC

2、AP:Finite state machine西安電子科技大學-軟件學院Presentation Name 3FSM是一般模塊工作狀態(tài)的抽象和形象的描述，它可以簡潔高效地描述模塊的工作狀態(tài)和狀態(tài)之間的轉換關系一、一、CPU-modeling for discrete design8-bit processorPublic-domain CAD toolsSenior student projectFabricated at the Massachusetts Microelectronics Center8-bit external data bus12-bit address busArit

3、hmetic and logic operations, Jump and branch instructionsDirect and indirect addressing modes西安電子科技大學-軟件學院Presentation Name 4CPU-architect1西安電子科技大學-軟件學院Presentation Name 5/wiki/List_of_CPU_architecturesSimplified block diagram over Intel 8088 (a variant of 8086); 1=main registe

4、rs; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.CPU-architect2西安電子科技大學-軟件學院Presentation Name 6/wiki/List_of_CP

5、U_architectures1.1 Parwan-entityTop level behavioral synthesizable description西安電子科技大學-軟件學院Presentation Name 7ENTITY par_central_processing_unit IS PORT( clk: IN std_logic; interrupt: IN std_logic; read-mem, write_mem: OUT std_logic; databus: INOUT byte:=zzzzzzzz; adbus: OUT twelve; halted: OUT std_

6、logic :=0, ready, grant : IN std_logic );END par_central_procesing_unit;1.2 Instruction setTwo addressing mode23 instructions including addressing modesThe main and only cpu data register: accumulator, which is used in conjunction with most instructionsFLAGS: overflow(v), carry(c), zero(z), negative

7、(n)西安電子科技大學-軟件學院Presentation Name 8Ok, how to design the instruction set ? Parwan instruction set西安電子科技大學-軟件學院Presentation Name 9Instruction MnemonicBrief DescriptionAddress BitsAdd. SchemeIndirect Add.Flags useFlags setLDA locLOAD AC w/(loc)12FULLyes-znAND locAND AC w(loc)12FULLyes-znADD locADD (lo

8、c) to AC12FULLyes-c-vcznSUB locSUB (loc) to AC12FULLyes-c-vcznJMP adrJUMP to adr 12FULLyes-STA locStore AC in loc12FULLyes-JSR tosSubroutine to tos8PAGENO-西安電子科技大學-軟件學院Presentation Name 10Instruction MnemonicBrief DescriptionAddress BitsAdd. SchemeIndirect Add.Flags useFlags setBRA_V_adrBranch to ad

9、r If V8pagenoV-BRA_C_adrBranch to adr if C8pageno-C-BRA_Z_adrBranch to adr if Z8pageno-Z-BRA_N_adrBranch to adr if N8pageno-N-NOPNo operation-noneno-CLAClear AC-noneno-CMAComplement AC-noneno-ZNCMCComp. carry-noneno-c-c-ASLArith shift left-NoneNo-VcznASRArith shift right-noneno-zn2. Parwan Bussing s

10、tructure4K memory: 16(pages)*256 vs. 4bit(pages)+8bit (locations)西安電子科技大學-軟件學院Presentation Name 11西安電子科技大學-軟件學院Presentation Name 12西安電子科技大學-軟件學院Presentation Name 13西安電子科技大學-軟件學院Presentation Name 14西安電子科技大學-軟件學院Presentation Name 15西安電子科技大學-軟件學院Presentation Name 16三、三、Next？Instruction SET: SPECIFICATI

11、ON西安電子科技大學-軟件學院Presentation Name 17Pages and offset (LOCATIONS)西安電子科技大學-軟件學院Presentation Name 18Full address; (12 bits) direct/indirectLDA, AND, ADD, SUB, JMP, STAPAGE Address, (8 bit)JSR, BRA_V, BRA_C, BRA_Z, BRA_NNO AddressNOP, CLA, CMA, CMC, ASL, ASR西安電子科技大學-軟件學院Presentation Name 19How to specify

12、 the function of the instructions?3.1 instruction opcode西安電子科技大學-軟件學院Presentation Name 20西安電子科技大學-軟件學院Presentation Name 21西安電子科技大學-軟件學院Presentation Name 22?西安電子科技大學-軟件學院Presentation Name 23Demo：西安電子科技大學-軟件學院Presentation Name 24LIBRARY cmos;USE cmos.basic_utilities.ALL;LIBRARY par_library;USE par_lib

13、rary.par_utilities.ALL;USE par_library.par_parameters.ALL;-ENTITY par_central_processing_unit is GENERIC(read_high_time,read_low_time,write_high_time,write_low_time:TIME:=2US; cycle_time :TIME := 4US); PORT(clk: IN qit; interrupt: IN qit; read_mem,write_mem: OUT qit; databus:INOUT wired_byte BUS: =

14、ZZZZZZZZ; adbus: OUT twelve);END par_central_processing_unit;西安電子科技大學-軟件學院Presentation Name 25Outline of the parwan behavioral description-ARCHITECTURE behavioral OF par_central_processing_unit ISBEGIN PROCESS IF interrupt =1 THEN HANDLE INTERRUPT; ELSE no interrupt READ FIRST BYTE INTO byte1, INCRE

15、MENT pc; IF byte1(7 downto 4) = single_byte_instructions THEN EXECUTE SINGLE_BYTE_INSTRUCTIONS ELSE TWO BYTE INSTRUCTIONS READ SECOND BYTE INTO byte2, increment pc; IF byte1(7 downto 5) = jsr THEN EXECUTE jsr INSTRUCTION, byte2 HAS ADDRESS; ELSEIF byte1(7 downto 5) = bra THEN EXECUTE bra INSTRUCTION

16、, ADDRESS IN byte2; ELSE ALL OTHER TWO-BYTE INSTRUCTIONS - END PROCESS; END behavioral;西安電子科技大學-軟件學院Presentation Name 26- ELSE ALL OTHER TWO-BYTE INSTRUCTIONS IF byte1(4) = indirect THEN USE byte1 and byte2 to get address; ENDIF; - END indirect IF byte1(7 downto 5) = imp THEN EXECUTE jmp INSTRUCTION

17、S ELSEIF byte1(7 downto 5) = sta THEN EXECUTE sta INSTRUCTIONS, WIRTE ac; ELSE READ OPERAND FOR lda, and, add, sub READ MEMORY ONTO databus; EXECUTE lda, and, add, sub; REMOVE MEMORY FROM databus; END IF; -jmp/sta/lda,and,add,sub END IF; - jsr/bra/other double-byte instructions; END IF; -SINGLE BYTE

18、 /DOUBLE BYTE END IF; - INTERRUPT / OTEHRWISEEND PROCESS; END behavioral;問題問題?如何針對指令集設計ALUPCIR等硬件COMPONENT?如何借鑒參考設計中的ALUPCIR等硬件設計指令集？尋址方式、中斷的作用是什么？對設計的影響是什么？Cache的作用是什么？西安電子科技大學-軟件學院Presentation Name 27Refs:西安電子科技大學-軟件學院Presentation Name 28VHDL: ANALYSIS AND MODELING OF DIGITAL SYSTEMSZainalabedin NAVABI, Northeastern Univ