數(shù)碼管led顯示器控制電路ppt課件

1、專題二. 經(jīng)典模塊設(shè)計(jì)LED數(shù)碼管顯示控制 電路設(shè)計(jì).數(shù)碼管顯示原理數(shù)碼管的組成：LED數(shù)碼管是由發(fā)光二極管構(gòu)成的，常用的有8段。數(shù)碼管的分類：有共陰和共陽極兩種。多個(gè)LED的陰極連在一同的為共陰極數(shù)碼管，陽極連在一同的為共陽極數(shù)碼管。共陰極數(shù)碼管的公共端接地，陽極a到h接高電平，數(shù)碼管點(diǎn)亮。共陽極數(shù)碼管的公共端接電源，陰極a到h接低，數(shù)碼管點(diǎn)亮。.數(shù)碼管的段碼和位碼數(shù)碼管的位碼就是提供應(yīng)公共端的電平。位碼的作用是控制數(shù)碼管的亮滅。數(shù)碼管的段碼就是提供應(yīng)a,b,c,d,e,f,g,h的電平。段碼的作用是控制數(shù)碼管顯示什么字符。單個(gè)數(shù)碼管需求9個(gè)端口來控制。位碼段碼.舉例：位碼和段碼例1：顯示字

2、符“1。共陰極數(shù)碼管位碼應(yīng)該接低電平。段碼按照hgfedcba的順序， 應(yīng)該為“00000110。例2：顯示字符“A。共陽極數(shù)碼管位碼應(yīng)該接高電平。段碼按照hgfedcba的順序， 應(yīng)該為“10001000。.LED數(shù)碼管顯示控制電路靜態(tài)顯示方式動(dòng)態(tài)顯示方式.1LED靜態(tài)顯示控制電路靜態(tài)顯示方式將每一個(gè)數(shù)碼管的段碼端ah銜接到CPLD/FPGA的IO端口上，公共端接地對(duì)于共陰極LED。每個(gè)數(shù)碼管需求8個(gè)IO口線，N個(gè)數(shù)碼管共需求N8條IO口線。當(dāng)CPLD/FPGA有相當(dāng)多的IO端口資源，并且顯示的位數(shù)較少時(shí)通常為12位，可以直接運(yùn)用靜態(tài)顯示的方式。.數(shù)碼管靜態(tài)顯示方式的優(yōu)點(diǎn)是連線簡單，軟件編程

3、簡單。缺陷是需求耗費(fèi)大量的IO端口資源。8N.靜態(tài)顯示的方式.CPLD/FPGA驅(qū)動(dòng)LED靜態(tài)顯示譯碼程序Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity display is -共陰極數(shù)碼管段碼譯碼 port( data: IN std_logic_vector(3 downto 0); seg: OUT std_logic_vector(6 downto 0) -gfedcba );End display;.architec

4、ture a of display isbegin process(data) begin case data is -gfedcba when 0000 = seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg = 0000000; -全滅 end case; end process;end a;.仿真結(jié)果將要顯示的數(shù)據(jù)譯成段碼在數(shù)碼管上顯示出來。.靜態(tài)顯示運(yùn)用舉例：設(shè)計(jì)一個(gè)4路獨(dú)立鍵盤輸入電路，讀取鍵盤的鍵值，并將鍵值在一位靜態(tài)共陰極LED數(shù)碼管中顯示出來。輸入為時(shí)鐘信號(hào)CLK50MHz，按鍵形狀KEY1，K

5、EY2，KEY3，KEY4。輸出為LED數(shù)碼管的段碼SEG6.0。.電路模塊 輸入信號(hào)：clk：時(shí)鐘，50MHz；reset：復(fù)位信號(hào)；key1, key2, key3, key4：按鍵信號(hào)輸入； 輸出信號(hào)：SEG6.0：靜態(tài)LED數(shù)碼管的段碼信號(hào)。.分頻模塊去抖動(dòng)模塊鍵盤掃描譯碼模塊50MHz.鍵盤掃描譯碼模塊程序1.-輸出1的段碼-輸出2的段碼-輸出3的段碼-輸出4的段碼-數(shù)碼管燈滅.鍵盤掃描譯碼模塊程序2.keyscan程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.

6、std_logic_arith.all;entity keyscan is port( clk10hz: IN std_logic; key1, key2, key3, key4: IN std_logic; keyvalue: OUT integer range 0 to 4 );end keyscan;.architecture a of keyscan isbegin process(clk10hz) -100ms begin if(clk10hzevent and clk10hz=1) then if(key1=0) then keyvalue = 1; -輸出鍵值1 elsif(ke

7、y2=0) then keyvalue = 2; -輸出鍵值2 elsif(key3=0) then keyvalue = 3; -輸出鍵值3 elsif(key4=0) then keyvalue = 4; -輸出鍵值4 else keyvalue seg seg seg seg seg scan = 11111110; data scan = 11111101; data scan = 11111011; data scan = 11110111; data scan = 11101111; data scan = 11011111; data scan = 10111111; data

8、scan = 01111111; data scan = 11111111; data seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg = 0000000; end case; end process;end a;.仿真結(jié)果以1KHz頻率動(dòng)態(tài)掃描顯示，依次輸出8個(gè)數(shù)碼管的段碼和位碼。123456.LED動(dòng)態(tài)顯示分位譯碼電路設(shè)計(jì)要求：采用動(dòng)態(tài)顯示方式，將一個(gè)兩位數(shù)用兩個(gè)數(shù)碼管顯示出來。一個(gè)數(shù)碼管顯示個(gè)位，另一個(gè)顯示十位。.頂層原理圖如上圖所示，為LED分位譯碼顯示頂層原理圖。由fdiv分頻模塊，cnt計(jì)數(shù)模塊

9、，fenwei分位模塊和dispdec顯示譯碼模塊四個(gè)模塊組成。輸入為： sysclk：50MHz系統(tǒng)時(shí)鐘。 num6.0：一個(gè)要顯示的兩位數(shù)，099。輸出為：SEG【6.0】：7位段碼輸出。SCAN【7.0】：8位位碼輸出，每一位分別控制一個(gè)數(shù)碼管的點(diǎn)亮。50MHz1KHz分位模塊.LED動(dòng)態(tài)顯示分位譯碼電路程序1. fenwei分位模塊Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;entity fenwei is port( num: IN integer range 0 to 99; numshi: OUT integer range 0 to 9; numge: OUT integer range 0 to 9 );end fenwei;architecture a of fenwei isbegin numge = num MOD 10; numshi scan = 11111110; data scan =