參考教案ni培訓(xùn)lesson adv.host integration

1、Lesson 7Synchronizing FPGA and Host Data TransfersLabVIEW FPGA and Host CommunicationSynchronizationDirect Memory Access (DMA) FIFOsLossless Data TransferInterruptsHandshakingA. LabVIEW FPGA and Host CommunicationFPGA VI and host VI are inherently asynchronousEach VI runs independent of the otherDat

2、a transfer synchronization needs to be implemented based on the application needsTo transfer large amounts of data between the target and host at high rates you must buffer the dataSynchronization and BufferingSynchronizationCausing tasks occur at the same time or in unison by using clock, triggers,

3、 or eventsBufferAn area of computer memory that stores multiple data itemsB. SynchronizationLevel of synchronization depends on the applicationSynchronization not required in some slower control applicationsFor example, if the data acquisition loop is faster than the control loop, the control loop r

4、eads the most recent valueSynchronization required to acquire and transfer lossless data at a known rateAsynchronous vs. Synchronous Asynchronous ApplicationsApplications that dont require tight synchronization for control or data processingTiming performed on the FPGA, but no synchronization to the

5、 host applicationMost recent data is okay, many control applicationsSynchronous ApplicationsSynchronization required between FPGA VI and host VISynchronous ApplicationsTiming controlTiming from the FPGA/acquisition controls the timing/loop rate of the host VI, and vice-versaSynchronized Data Transfe

6、rSynchronization transfers/streams data from acquisition to host VI for processing and loggingLossless data transferSynchronization MethodsDirect Memory Access (FIFO)InterruptsHandshakingC. Direct Memory Access (DMA) FIFOsData BufferingTo transfer larger amounts of data at high rates between the tar

7、get and the host you must buffer your data.The best way to buffer data is by using Direct Memory Access (DMA) data transfer methods. Direct Memory Access (DMA) FIFOs (continued)Transfers data from FPGA directly to memory on the RT controller through bus mastering.Streams large amounts of data.Provid

8、es better performance than using local FIFO and reading indicators.Host processes data while FPGA transfers data to host memory.Without DMA, processor must read data.Consists of two partsFIFO part and host part.FPGA writes data one element at a time to the FPGA memory.DMA engine transfers data along

9、 PCI bus to host memory.Demonstration: Target-to-Host DMA FIFOExplore how the FPGA transfers data to the host.LabVIEW FPGADemonstrationsDemonstration: Host-to-Target DMA FIFOExplore how the host transfers data to the FPGA.LabVIEW FPGADemonstrationsCreating DMA FIFOsCreate DMA FIFO the same way as FP

10、GA FIFOsRight-click targetSelect NewFIFOChoose Target to Hostor Host to Target asTypeAll DMA FIFOs are U32 data typeMust convert to and from U32.Writing Data to a Target-to-Host DMA FIFODrag FIFO from Project Explorer window.Writing Data to a Target-to-Host DMA FIFO (continued)FIFO Write FunctionEle

11、mentInputs the data element to be stored. TimeoutInputs the number of clock ticks the function waits for available space in the FIFO if the FIFO is full. The default is 0, or no wait. A value of 1 prevents the function from timing out. Timed Out?Returns True if space in the FIFO is not available bef

12、ore the function completes execution. If Timed Out? is True, the function does not add Element to the FIFO.Reading Data from a Target-to-Host DMA FIFORead a DMA FIFO in the host:Open a reference to the FPGAAdd an Invoke Method functionChoose the DMA FIFORead methodReading Data from a Target-to-Host

13、DMA FIFO (continued)Read a DMA FIFO on the host:Number of ElementsFunction completes when elements are read or timeout is reachedSame overhead regardless of the number of elements; read more elements if host is too slowTimeoutTime to wait before timeout (1 = indefinite wait; Default is 5,000 ms)DMA

14、FIFO with Blocking Implementing a DMA FIFO with blocking:User specifies number of elementsBest method when input/output rate is knownDMA FIFO with PollingImplementing a DMA FIFO with polling:Acquires as many samplesas are currently availableBest when the input/output rate isunknownWriting Multiple C

15、hannels Writing multiple channels of data to a DMA FIFO by interleavingReading Multiple Channels Reading multiple channels from a DMA FIFO in the hostD. Lossless Data TransferLossless ApplicationOverflowDMA Full?UnderflowCheck for 50400OverflowOverflowtoo many data points for buffer, may lose dataAc

16、quire data slowerIncrease number of elements to read on the hostIncrease the rate that the host reads dataIncrease buffer sizes on FPGA and hostDemonstration: Target to Host DMA FIFO OverflowExplore how overflow of the DMA FIFO occurs if theRT host VI is too complex.LabVIEW FPGADemonstrationsUnderfl

17、owUnderflownot enough data to read, FIFO read times outIncrease timeoutRead data less oftenRead smaller sets of elementsDemonstration: Target to Host DMA FIFO UnderflowExplore how underflow occurs when the DMA FIFO tries to read data before it is available.LabVIEW FPGADemonstrationsExercise 7-1: DMA

18、-Based Data Transfers Observe how DMA-based handshaking works.E. InterruptsSend a trigger from the target to the host application.Why use an interrupt?Eliminate polling Allow host to perform other operations while waiting for the Interrupt signalCommunicate over a physical hardware lineAdvantages of

19、 InterruptsAn interrupt requires execution of a low-level driver on the host, so a host can process more polling operations/s than interrupts/sComparison statistics for a Networked RIO Device:A single poll requires 10 sAn interrupt requires about 250 sUse Interrupts when FPGA sends data less often a

20、nd host must do other processingImplementing an InterruptImplementing an Interrupt (continued)Interrupt Express VIIRQ NumberSpecifies which logical interrupt (0 31) to assertDefault is 0 Wait Until ClearedSpecifies if this VI waits until the host VI acknowledges the logical interrupt Default is Fals

21、eWait Until Cleared as True causes jitter due to dependency upon the host VIHost and InterruptsHost must acknowledge interruptsUse Wait on IRQ and Acknowledge IRQ methodsIRQ Number(s)specifies the logical interrupt or array of logical interrupts for which the function waitsTimeout (ms)specifies the

22、number of milliseconds the VI waits before timing out. 1 = infinite timeoutTimed Outreturns TRUE if this method has timed out IRQ(s) Assertedreturns the asserted interrupts. Empty or 1 array indicates that no interrupts were receivedAcknowledge IRQ MethodAcknowledges and resets to the default value

23、any interrupts that occurWire after the Wait on IRQ methodIRQ Number(s) specifies the logical interrupt or array of logical interrupts for which the function waitsInterrupt ExampleDMA FIFO with InterruptsImplementing a DMA FIFO with an interruptPrevents the CPU from polling the DMA FIFO to see if el

24、ements have arrivedLeast resource intensive DMA FIFO transfer methodSlowest DMA FIFO transfer method due to IRQ delayExercise 7-2: Interrupt-Based HandshakingObserve an example of how interrupt-based handshaking works.F. HandshakingHandshakingChecks that a receiving device is ready to receive or a transmitting device is ready to transmitHandshaked synchronizationoccurs when two or more devices act in sequenceHost uses Boolean controls and indicators (data available an