仿真PowerDC直流壓降仿真指導(dǎo)書

PowerDCPDN仿真指導(dǎo)書、仿真文件格式轉(zhuǎn)換.文件轉(zhuǎn)換軟件介紹;雙擊工，」?口:，通過雙擊工，」?口:，通過SPDLinks將PCB文件轉(zhuǎn)換成Sigrity專用的仿真文件格式spd文件.轉(zhuǎn)換方法和設(shè)置;如下圖，指定好被轉(zhuǎn)換的PCB文件以及轉(zhuǎn)換后spd文件的路徑;設(shè)置好轉(zhuǎn)換文件用的相關(guān)文件路徑，記得保存設(shè)置結(jié)果。OpenT?-^)RestoreSettingsCancelOpenT?-^)RestoreSettingsCancel吊SettingsPlaneorSignalTrardateMIXSJLayerto；PlaneorSignal^■]AJIowpatchesanSigndlayers刁Digtngu如shapesf]fdifferentnetsbycolor[Addpseudoplanefs)iflackofp^neor：patdh/]Appendnetnam比toobjectsIndudeelementswithnonetnames□CreateP3「gIOctNamesbaseduponComponentPartNumber□CakuhteviaplatingusngTDril/Stotsyni?rvahes[SphtVikintosevsrail24ayefvnasTranslateantipadsasvoids~\Translateonlyvoltagenets/]TreatpadondielectriclayerasdrillUnionizetracesshorterthan:MaMnwiarclengthrephcedbySnesegnenkNameaffix：Caden?EytrjetbPath:cnvHlePatfi; 史meP^th:g:Cadence培PEL16,6\tDcfc'pcb'也怕\extrar-a.exeExtract苜程序的路徑）3.文件格式轉(zhuǎn)化;設(shè)置好相關(guān)路徑后可以啟動(dòng)文件轉(zhuǎn)換程序，待完成后可以到spd文件的路徑下獲取文件;

二、仿真設(shè)置雙擊.啟動(dòng)PowerDC軟件雙擊進(jìn)入PowerDC主界面，點(diǎn)擊 」一?；」—，一-創(chuàng)建仿真任務(wù)。選取? .」???.?.「，，小..??：「?模式，接下來導(dǎo)入仿真文件，進(jìn)行仿真設(shè)置。進(jìn)行仿真設(shè)置。.PowerDC仿真設(shè)置仿真疊層和padstack設(shè)置Pcb轉(zhuǎn)成Spd文件過程中，會(huì)將pcb的相關(guān)疊層設(shè)置一并轉(zhuǎn)換過來；因此導(dǎo)入spd文件后會(huì)直接生成相關(guān)的疊層，建議直接在allegro里面設(shè)置好疊層，避免后期重復(fù)設(shè)置。

■iW=0西口;imr■iW=0西口;imra*I”：具iiiumS-jCLAMiViaPlatingThicknessSetup:edit>padstacklibrary輸入過孔鍍銅厚度仿真網(wǎng)絡(luò)設(shè)置首先，選擇需要仿真的電源網(wǎng)絡(luò)，將其從信號(hào)網(wǎng)絡(luò)類別轉(zhuǎn)換到PowerNets類別中；將所有GND網(wǎng)絡(luò)（包含單點(diǎn)接地的GND網(wǎng)絡(luò)）轉(zhuǎn)換至UGroundNets類別中，同時(shí)將除power和GND兩類以外的網(wǎng)絡(luò)全部disable掉。^Rnw？-iCJI-O2.pdrx- IaywVire|■ puEpfl^lQnF4hW?Wei?-T?H 岬p；**-』.L 3P0?電回限J，--p-；'二同；**-』.L 3P0?電回限J，--p-；'二同」Lf聲.%x-4：、鼻邛再日、皿的xia口些 中1戶3嚴(yán)史日黎Mg小式舊“擊U.H尚"U.居皿”曲…-.0.…耳.12黑匕小,”」之.'#』.」￡...”.也…曰” 忖"Hs^er（同仿真電源網(wǎng)?旬IEnab^dL?d.NrW&Mr'M!^t?)wlEi*dajpEnriiHrTb5曲tupQ—I.IWwnnUM二.0BPifaHih、,國(guó)■NW??273<0■?Cj.lM_iJ?國(guó) gjwxK_LiaRi_in國(guó) ?厘SLI解哥臂.0■田仲■血...Q- \Q- \iT*es?啊風(fēng)：|AJIEnabhdNvgJWizard、設(shè)置仿真端口直流IRDrop仿真需設(shè)置源端和負(fù)載端，以便計(jì)算從源端到負(fù)載端通路上的直流壓降，進(jìn)而計(jì)算出通路的直流阻抗。Sourcesink選擇的原則：BUCK電源source選擇在反饋線處電容或電感處設(shè)置LDO電源source選擇在PMU出來的管腳處設(shè)置電流源端設(shè)置通常源端選用自動(dòng)生成的方式，在之前enable的網(wǎng)絡(luò)中進(jìn)行選擇；41P口腔僅-屯之.pckx 2.spdUyerView] 力氣1加M-膛"心?陽AMNW”口1i修?*1Markj噌ace fidh:VIe-yTog *WogwM[HKribuwEdiiVie*5tmpTW,懦MmHdp；JIjg0■口■」：歲。?聲一口Bl口■::!.Ejhriiled -C[4*|■*=S?3TOC\o"1-5"\h\z|Wartflow7Fnwflri>C JC*51rli.A-Bmr由P■據(jù)nyIR.PropAji,I『日■WorkifMCE i.*；LreirtENewyrgle-ElaardWcckspjceL<iadExi皿咐J^L*一段mTIN比依『中SlmuLfl^onMode g金knihlc-IRQrap.AfUiyEisMadfcl/wtinISetup qLaddaNew歸tHcrentLjv□比CMck“就七j確SetupP/GNesOpt?nal;ImpcidBerd「EkWunrMapVHlfrg。DfapAn■[戶施與Mu審 孱(比;奇一他礴I5ftupInst8nteifSetupIWNDde-eic.gEnairrUSrlup 巴SrtupE-<onj4r-Brt3電壓同一設(shè)置為1V，Tolerance不設(shè)置；以此類推將需要仿真的網(wǎng)絡(luò)全部設(shè)置好。

如自動(dòng)無法產(chǎn)生端口，可以通過手動(dòng)方式，設(shè)置電流源端口;手動(dòng)端口設(shè)置可以直接通過網(wǎng)絡(luò)選擇整體芯片自動(dòng)生成端口。2.4.2負(fù)載端設(shè)置負(fù)載端同樣采用自動(dòng)生成端口的方式，在之前enable的網(wǎng)絡(luò)中選??；電流端口選擇負(fù)載的器件，具體設(shè)置如下圖；WiHTtf XRmvwMd^fiundIwn'EGLIDA_1P&醇卷.1第WlG-LIlAjm見而匚WiHTtf XRmvwMd^fiundIwn'EGLIDA_1P&醇卷.1第WlG-LIlAjm見而匚包的民設(shè)置完成，檢查無誤后保存文件后可以開始仿真。（Model選擇注意要選擇equalvoltage,這樣兩者仿真出來的結(jié)果就跟resistancemeasurementgeneration一樣）IRDrop中的測(cè)得的壓降值得是各個(gè)pin中最壞壓降。各個(gè)pin的電壓是不相等的，通過V/I得到的R會(huì)大Resistance中port中所有的pin都是short起來的，電壓相等，結(jié)果是整體的R。將IRDrop中的sink設(shè)置成等電壓會(huì)得到理想結(jié)果EqualVoltage[fthrmodelisselected,allpackagenodesuonnccLcdwithIhcsamepinoIejSINKarcLumpedtogcLhcr.rl7ieActualVnltageoftheSINKisthevoltagedifferencebetiA'eenthe ivepin3ndthenegativepin.EqualCurrentIfdiemodelisselected,equalcurrents^illflowthroughjIJthepackagenodesconnectedwiththesamepinufaSINK.UnequalCurrentirpiickaceissclcclcd.thecurrentsflowingthroughthemodelnodesconnededwiththesamepinHESINKcanbediflerenl.UsersctininpuLthecurrentforeachpackagemodemanuallyorspeciK1thecurrentsbymatrixwhichisdehcnbcdin"IinportSINK.Curriint".ActualVoltageFarkqualandUnequalCurrentmodeLavoltacevalueiscomputedforeachpackagenode.PackagemxJcsconnectedwiththesamepinmayhavedifferentvoltages.TheActualVbltajicofLheSINKiscakulateidbasedonPass/FaillP/F)mudc.Unequalcurrent:Importcurrentmappingfileinspreadsheetformatorcreatepingroupsmanually.Hereisanexample.Thefileisabouta3*3currentarray.willHereisanexample.Thefileisabouta3*3currentarray.will如果仿真是為了看整個(gè)port的R的話，用上面的方法IRDrop/sinkmodel=equalvoltage如果仿真是為了看port中哪個(gè)pin壓降最大的話，可以sink選擇equalcurrent,p/fmodel選擇worst,這樣計(jì)算出來的就是最壞情況下的壓降P/FAverageExampleIftheP/FmodeisAveragethen,theActualVoltage二MeanofVoltagesoftheLayoutNodesofthePositivePinminustheMeanoftheVoltagesoftheLayoutNodesoftheNegativePin.P/FWorstExampleIftheP/FmodeisWorstthen,theActualVoltage=Findthelargestandlowestvoltagesotthepowerpins.Findthelargestandlowestvoltagesofthegroundpins.Calculatethevoltagedifferencebetweenpowerandgroundpinsv/iththeabovefourvalues.Findthelargestandlowestones.Comparethetwovaluesgotteninc)withthenominalvoltagecdtheSINK.Theonewithlargerdifferencefromthenominafvoltagewillbechosenastheactualvoltage.Anditi*kImdiiRArlinmarninu川「11加tinnTherearefbuiresistancemodelsLumpedicLumped—Allnodeslinkediothepositivepinareshortedideally.AllnodeslinkedtothenegativepinareshortedideallyThercsisiaiiccbetweenthepositivepinandnegativepiniscalculatedinthesimulation.LumpedtuMultiple—OnlytlienodeslinkedLothepositivepinareslioriedideally.ResistancefrointhepositivepintoeachnodelinkedtothenegativepiniscalcukitedNnodeslinkedtothenegativepinproducesNresistancevalue.MultipletoLunnpcd-Onlyullthenodeslinkedtothenegativepinarcshortedideally.ResistancefromeachnodeofthepositivepintotheIumpednegativepiniscalculatedMnodeslinkedtnthepositivepinproduceMresistancevalue.MultipletoMultiple——AnMhyNresistancematrixEachelementinthismatrixrepresentsresistancefroTronenodeinapositivepintoanothernodemanegativepin.三、仿真結(jié)果分析1.仿真結(jié)果含義根據(jù)仿真的壓降結(jié)果，結(jié)合之前步驟設(shè)置的1A電流，可以推導(dǎo)出實(shí)際的走線電阻；按照LDO電源走線+/-3%的的tolerance,結(jié)合各電源實(shí)際電壓和電流，判斷是否超標(biāo)。當(dāng)然也可以在前期仿真設(shè)置階段將電壓和電流直接寫進(jìn)去，仿真結(jié)束后會(huì)直接輸出Pass或Fail的結(jié)論。.電流分布Power-DC還可以直觀的體現(xiàn)整體電流密度情況，通過'?二口";“：二r可以觀察整體電流等參數(shù)的平面分布。HiEn?blvd*M1bIWorkflow:PowerDCC?ndIr*lriUSe&1;?SimulatijanO*?d￡工'SkirliimlriiM"indReport3叩HdhkdA.KHiEn?blvd*M1bIWorkflow:PowerDCC?ndIr*lriUSe&1;?SimulatijanO*?d￡工'SkirliimlriiM"indReport3叩HdhkdA.KGcoarii*H?p&ri修pari■mWE0iUrdaiii弓tn料leJL>HrWwwC?的?^^waiL(WFhjtasa—聲dfvwqnMHjjLva」aCHJP.jAF.」「Rh■!*taraFcwnQ'AGjWID?9-tiibuLjk>nOMOlHiiBjiIJan*|EhrMAMriJ)-0iW10746?md5?M41hc?BRewihTdtawung%.仿真結(jié)果后期處理:SetupE-constrain

CONSTRAINTSSETUPSetupeonEtraintsofsinkvoltageinterconnectcurrent,viacurrentandmetalcurrentdensityforvoltagedropanalysisSinkVoltageS^tupconstraintsofSinkvoltages.InterconnectCurrentSetupconstraintsofInterconnectcurrents.ViaCurrenVCurrentDensitySetupconstraintsotViaCurren^Cumentdensilies.WlProbesProbevoltageorcurrentandsetupconstraintsinthespecifiedlocations.PlaneCurrentDensitySetupconstraintsofPlaneCurrentdensities.TraceCurrentDensitySetupconstraintsoftracecurrentdensity.通過在SetupE-constrain設(shè)置各種約束來看仿真結(jié)果:Voltage*DropAnalytic i>jGetupURM與SetupSink^SetupInterronnerts爐及？入國(guó)順日啟taTOC\o"1-5"\h\zCcyn如aintsSetup 運(yùn).1I：SetupE-Constraints：)Siiirkilati0n / (*JClicclc：Errcrrs/y^arnings.SaveFilesStartSimulationRewIts-andRepert ③ViewE-Resull￡TablesView2IDIE-DistributionsView3DIE-DistributionsSwitdhtoNormalILayerViewGercrateReportSaveReportSave*SimulationRe&ultLeadSimulertionResultSknglfr-Board/Packag&E/TCo-SimulationMLtftr-BQard/PackageIR.DropAnalysis 弋m.?M■二 L-■—k戶reifiUrr 3tup->SinkVoltef^nJcVoltaQC|IntErremt.-Cjmcrirf^nJcVoltaQC|IntErremt.-CjmcrirIvlProce?IQ.meri-Current[lerrSTyIPhnc：ir-ir-De^fitYIFrrreCurrtrt：Zrr'J-fIncbCTldtirrtnt[lerrSTyI\jqlera-i^<J-i:叵▼ClicktheSinkVoltagetabintheConstraintsSetupmenu.SelectallSinks.Right-clickandchooseGroupEditfromthepop-upmenu設(shè)置sink的電壓和波動(dòng)幅值

EditNominalVoltage(V),UpperTolerance(+%),andLowerTolerance(%)ClickViewE-ResultsTablesintheWorkflowpane,andclicktheSinkVoltagetab.TheSinkVoltageresultsareupdatedintheResultpane.StartSimulationVifivu3DStartSimulationVifivu3DIE-Di￡tribdlion6SwfchfcoNormalLayerMsSaveReportSave5imul^iionRpsullLoadSlmulstiDnResu^SlHgla-ScidrclXPBiekagifrE/TCa-SImula^loHiMuttj-BQWcl/PmckageIRDropAnalytifBin%fh!FC嗎?4/Tk/ 麗■=1hResultsandReportSinkVoit^geVRMK日培里SirkYulLageResultsandReportSinkVoit^geVRMK日培里SirkYulLageIrtecanect匚山口式| Lot沼|ProbesMeasu-e-ftenls)Gkba冒3cLi樣口“QgmiWa匚樂團(tuán)tDe⑻“|船已仃覺討己dr「wnl卜33UP團(tuán)e￡InterconnectCurrentSetup跟Sinkvoltag約束一樣，可以看出通過電阻或電感的電流有沒有超標(biāo)V/IProbesSetupVoltageProbe：在ConstraintsSetup>voltageprobe中設(shè)置約束條件，在ViewE-ResultsTables>V/Iprobe中看voltageprobe的電壓有沒有超過約束值CurrentProbe:TheCurrentProbemeasurestheVia,scurrentSelectseveralViasintheLayoutwindow.Right-clickintheblankspaceintheV/IProbestableandchooseAddfromthepopupmenuTheCurrentProbeiscreatedautomatically可以查看你關(guān)注的流過這些過孔的電流有沒有超標(biāo)ViaCurrent/CurrentDensitySetup：分via和padstack，可以約束過孔或pad上流過的電流ConstraintsSetup>ViaCurrent/CurrentDensity設(shè)置過孔或pad的電流和電流密度約束值ViewE-ResultsTables>GlobalViaCurrent/GlobalViaCurrentDensity顯示超過這些約束值的過孔或padPlaneCurrentDensitySetup:可以對(duì)平面電流密度設(shè)置全局約束也可以對(duì)特定的電源平面設(shè)置局部約束ConstraintsSetup>PlaneCurrentDensity設(shè)置平面電流密度約束ViewE-ResultsTables>GlobalPlaneCu