并串串并轉(zhuǎn)換設(shè)計(jì)

并串/串并轉(zhuǎn)換電路設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康模河胿erilog語言設(shè)計(jì)一個(gè)8:1的并串轉(zhuǎn)換電路、設(shè)計(jì)一個(gè)1:8的串并轉(zhuǎn)換電路。二、 實(shí)驗(yàn)原理：實(shí)現(xiàn)8位的并行數(shù)據(jù)轉(zhuǎn)換為串行的數(shù)據(jù)：并行轉(zhuǎn)串行，只要把每個(gè)輸入按從高到低的順序輸出即可。即每個(gè)時(shí)鐘脈沖輸出一個(gè)數(shù)據(jù)。實(shí)現(xiàn)8位的串行數(shù)據(jù)轉(zhuǎn)換為并行的數(shù)據(jù)：8位串行數(shù)據(jù)轉(zhuǎn)換為并行數(shù)據(jù)，需要一個(gè)模為8的計(jì)數(shù)器，當(dāng)計(jì)到8個(gè)時(shí)鐘脈沖時(shí)，把之前的8個(gè)數(shù)據(jù)全部輸出，然后從新接收。三、 實(shí)驗(yàn)內(nèi)容：用verilog實(shí)現(xiàn)8位的并行數(shù)據(jù)轉(zhuǎn)換為串行的數(shù)據(jù)：modulebingchuan(out,in,rst,clk);outputout;regout;input[7:0]in;inputrst,clk;integeri=0;always@(posedgeclk)beginif(rst)out<=0;elsebeginif(i==8)beginout<=0;endelseout<=in[i];i<=i+1;endendendmodulemoduletextbingchuan;reg[7:0]in;regrst,clk;wireout;bingchuanbc(out,in,rst,clk);initialclk=1;always#5clk=~clk;initialbeginrst=1;#100rst=0;in=8'b11101110;endendmodule仿真后的波形：modulechuanbing(out,in,rst,clk);output[7:0]out;reg[7:0]out;inputin,rst,clk;reg[7:0]temout;reg[2:0]cd;always@(posedgeclk)beginif(rst)cd=3'b111;elsebegintemout[cd]<=in;cd<=cd-1'b1;if(cd==3'b111)beginout<=temout;endelseout<=8'bz;endendendmodulemoduletextchuanbing;regrst,clk,in;wire[7:0]out;chuanbingch(out,in,rst,clk);initialclk=0;always#5clk=~clk;initialbeginrst=1;#10rst=0;in=1;#10in=0;#10in=1;#10in=1;#10in=0;#10in=1;#10in=0;#10in=1