Intel MAX 10 FPGA系列低成本開(kāi)發(fā)方案大合集

IntelMAX10FPGA系列低成本開(kāi)發(fā)方案大合集Intel公司的MAX10FPGA系列采用TSMC55nmNOR閃存技術(shù),容量從2K到50K邏輯單元(LE),采用單個(gè)或雙核電源電壓和小尺寸3x3mm和高I/O引腳數(shù)封裝;器件具有全特性FPGA功能,支持NiosII軟核嵌入處理器,數(shù)字信號(hào)處理(DSP)區(qū)塊以及軟DDR3存儲(chǔ)器控制器,內(nèi)部存儲(chǔ)雙配置閃存,用戶(hù)閃存存儲(chǔ)器,集成了模數(shù)轉(zhuǎn)換器(ADC).主要用在系統(tǒng)管理,I/O擴(kuò)展,通信控制,工業(yè)應(yīng)用,汽車(chē)電子和消費(fèi)類(lèi)電子.本文介紹了Intel?MAX?10FPGA系列主要優(yōu)勢(shì),器件平面布局圖以及MAX10FPGA開(kāi)發(fā)套件主要特性和電路圖.

Intel?MAX?10FPGAsrevolutionizenon-volatileintegrationbydeliveringadvancedprocessingcapabilitiesinalow-cost,singlechipsmallformfactorprogrammablelogicdevice.BuildinguponthesinglechipheritageofpreviousMAXdevicefamilies,densitiesrangefrom2K–50KLEs,usingeithersingleordual-corevoltagesupplies.TheMAX10FPGAfamilyencompassesbothadvancedsmallwaferscalepackaging(3mmx3mm)andhighI/Opincountpackagesofferings.

MAX10FPGAsarebuiltonTSMC’s55nmembeddedNORflashtechnology,enablinginstant-onfunctionality.Integratedfeaturesincludeanalog-to-digitalconverters(ADCs)anddualconfigurationflashallowingyoutostoreanddynamicallyswitchbetweentwoimagesonasinglechip.UnlikeCPLDs,MAX10FPGAsalsoincludefull-featuredFPGAcapabilities,suchasNios?IIsoftcoreembeddedprocessorsupport,digitalsignalprocessing(DSP)blocks,andsoftDDR3memorycontrollers.

Intel?MAX?10devicesaresingle-chip,non-volatilelow-costprogrammablelogicdevices(PLDs)tointegratetheoptimalsetofsystemcomponents.

ThehighlightsoftheIntelMAX10devicesinclude:

?Internallystoreddualconfigurationflash

?Userflashmemory

?Instantonsupport

?Integratedanalog-to-digitalconverters(ADCs)

?Single-chipNiosIIsoftcoreprocessorsupport

TheMAX?10devicesconsistofthefollowing:

?Logicarrayblocks(LABs)

?Analog-to-digitalconverter(ADC)

?Userflashmemory(UFM)

?Embeddedmultiplierblocks

?Embeddedmemoryblocks(M9K)

?Clocksandphase-lockedloops(PLL)

?GeneralpurposeI/O

?High-speedLVDSI/O

?Externalmemoryinterfaces

?Configurationflashmemory(CFM)

IntelMAX10devicesaretheidealsolutionforsystemmanagement,I/Oexpansion,

communicationcontrolplanes,industrial,automotive,andconsumerapplications.

Intel?MAX?10FPGA系列主要優(yōu)勢(shì):

圖1.Intel?MAX?10FPGA器件平面布局圖

MAX10FPGA開(kāi)發(fā)套件

TheMAX?10FPGAdevelopmentboardprovidesahardwareplatformforevaluatingtheperformanceandfeaturesoftheAltera?MAX10device.

ThedevelopmentkitincludesaRoHS-andCE-compliantMAX10FPGADevelopmentboardwiththefollowingcomponents:

?FeaturedDevices:

?MAX10FPGA(10M50D,dualsupply,F484package)

?Enpirion?EN2342QI4APowerSoCVoltage-ModeSynchronousStep-DownConverterwithIntegratedInductorEnpirion

?EN6337QI3AHigh-EfficiencyPowerSoCDC-DCStep-DownConverterswithIntegratedInductor

?EnpirionEP5358xUI600mAPowerSoCDC-DCStep-DownConverterswithIntegratedInductor

?MAXIICPLD–EPM1270M256C4N(On-boardUSB-Blaster?II)

?ProgrammingandConfiguration:

?EmbeddedUSB-BlasterII(JTAG)

?OptionalJTAGdirectvia10-pinheader

?MemoryDevices:

?64-Mx161GbDDR3SDRAMwithsoftmemorycontroller

?128-Mx81GbDDR3SDRAMwithsoftmemorycontroller

?512-MbQuadserialperipheralinterface(quadSPI)flash

?CommunicationPorts:

?TwoGigabitEthernet(GbE)RJ-45ports

?EthernetPortA(Bottom)

?EthernetPortB(Top)

?Onemini-USB2.0UART

?Onehigh-definitionmultimediainterface(HDMI)videooutput

?Oneuniversalhigh-speedmezzaninecard(HSMC)connector

?Two12-pinDigilentPmod?compatibleconnectors

?Analog:

?TwoMAX10FPGAanalog-to-digitalconverter(ADC)SMAinputs

?2x10ADCheader

?PotentiometerinputtoADC

?Oneexternal16bitdigital-to-analogconverter(DAC)devicewithSMAoutput

?Clocking

?25MHzsingle-ended,externaloscillatorclocksource

?SiliconlabsclockgeneratorwithprogrammablefrequencyGUI

?Mini-USBcableforon-boardUSB-Blaster?II

?2APowerSupplyandcord

?FreeQuartus?IIWebEditiondesignsoftware(downloadsoftwareandlicensefromwebsite)

?Completedocumentation

?Usermanual,billofmaterials,schematic,andboardfiles

圖2.MAX10FPGA開(kāi)發(fā)板正面元件圖

圖3.MAX10FPGA開(kāi)發(fā)板背面元件圖

圖4.MAX10FPGA開(kāi)發(fā)板系統(tǒng)框圖

圖5.MAX10FPGA開(kāi)發(fā)板時(shí)鐘框圖

圖6.MAX10FPGA開(kāi)發(fā)板電路圖(1)

圖7.MAX10FPGA開(kāi)發(fā)板電路圖(2)

圖8.MAX10FPGA開(kāi)發(fā)板電路圖(3)

圖9.MAX10FPGA開(kāi)發(fā)板電路圖(4)

圖10.MAX10FPGA開(kāi)發(fā)板電路圖(5)

圖11.MAX10FPGA開(kāi)發(fā)板電路圖(6)

圖12.MAX10FPGA開(kāi)發(fā)板電路圖(7)

圖13.MAX10FPGA開(kāi)發(fā)板電路圖(8)

圖14.MAX10FPGA開(kāi)發(fā)板電路圖(9)

圖15.MAX10FPGA開(kāi)發(fā)板電路圖(10)

圖16.MAX10FPGA開(kāi)發(fā)板電路圖(11)

圖17.MAX10FPGA開(kāi)發(fā)板電路圖(12)

圖18.MAX10FPGA開(kāi)發(fā)板電路圖(13)

圖19.MAX10FPGA開(kāi)發(fā)板電路圖(14)

圖20.MAX10FPGA開(kāi)發(fā)板電路圖(15)

圖21.MAX10FPGA開(kāi)發(fā)板電路圖(16)

圖22.MAX10FPGA開(kāi)發(fā)板電路圖(17)

圖23.MAX10FPGA開(kāi)發(fā)板電路圖(18)

圖24.MAX10FPGA開(kāi)發(fā)板電路圖(19)

圖25.MAX10FPGA開(kāi)發(fā)板電路圖(20)

圖26.MAX10FPGA開(kāi)發(fā)板電路圖(21)

圖27.MAX10FP