Digital Logic Circuits 數(shù)字邏輯電路智慧樹知到課后章節(jié)答案2023年下南京理工大學

DigitalLogicCircuits數(shù)字邏輯電路智慧樹知到課后章節(jié)答案2023年下南京理工大學南京理工大學

第一章測試

Thenumberofvaluesthatcanbeassignedtoabitare(

)

A:one

B:three

C:two

D:ten

答案:two

Comparedtoanalogsystems,digitalsystems(

)

A:arelesspronetonoise

B:

canrepresentaninfinitenumberofvalues

C:

alloftheabove

D:canhandlemuchhigherpower

答案:arelesspronetonoise

Thetermbitmeans(

)

A:

bothanswers(b)and(c)

B:asmallamountofdata

C:a1ora0

D:binarydigit

答案:

bothanswers(b)and(c)

Aquantityhascontinuousvalueis(

)

A:ananalogquantity

B:abinaryquantity

C:adigitalquantity

D:anaturalquantity

答案:ananalogquantity

VerilogHDLisa(

)

A:programminglogicdevice

B:computerlanguage

C:

hardware

D:logicdevice

答案:computerlanguage

Acategoryofdigitalintegratedcircuitshavingfunctionsthatcanbealteredisknownasfixed-functionlogic.

A:對B:錯

答案:錯

Dataareinformationonlyinnumeric.

A:錯B:對

答案:錯

Twobroadtypesofdigitalintegratedcircuitsarefixed-functionandprogrammble.

A:對B:錯

答案:對

Thenonrecurringengineering(NRE)costforanASICdesignisnormallylow.

A:對B:錯

答案:錯

Thereisan“invalid”regionbetweentheinputrangesforlogic0andlogic1

A:對B:錯

答案:對

第二章測試

Forthebinarynumber10000,theweightofthecolumnwiththe1is(

)

A:8B:10C:

4

D:16

答案:16

The2’scomplementof1000is(

)

A:1001B:0111C:1000D:1010

答案:1000

Thefractionalbinarynumber0.11hasadecimalvalueof(

)

A:

?

B:

?

C:noneoftheabove

D:?

答案:?

Thenumber1100inBCDis(

)

A:equaltodecimaltwelve

B:invalid

C:

equaltodecimaleight

D:equaltodecimalten

答案:invalid

Anexampleofanunweightedcodeis(

)

A:BCD

B:decimal

C:Graycode

D:binary

答案:Graycode

Anexampleofanalphanumericcodeis(

)

A:ASCII

B:BCD

C:CRC

D:hexadecimal

答案:ASCII

Theoverflowoccurswhenaddingthefollowing8-bittwo’scomplementnumber:01011101+00110001

A:錯B:對

答案:對

TheoverflowdoesNOToccurwhenaddingthefollowing8-bittwo’scomplementnumber:10111111+11011111

A:錯B:對

答案:對

Ingeneral,weneedatmostbitstoexpresstheproductwhenmultiplyingann-bitnumberbyanm-bitnumber.

A:錯B:對

答案:錯

Anadditionoverflowsiftheaddends’signsarethesamebutthesum’ssignisdifferentfromtheaddends’.

A:錯B:對

答案:對

第三章測試

TheBooleanexpressionA

.

1isequalto(

).

A:1B:BC:0D:A

答案:A

TheBooleanexpressionA

+1isequalto(

).

A:BB:AC:0D:1

答案:1

TheBooleanequationAB+AC=A(B+C)illustrates(

)

A:

thecommutativelaw

B:

theassociativelaw

C:DeMorgan’stheorem

D:thedistributionlaw

答案:thedistributionlaw

Theassociativelawforadditionisnormallywrittenas(

)

A:A+B=B+A

B:AB=BA

C:

(A+B)+C

=A

+(B+C)

D:A+AB=A

答案:

(A+B)+C

=A

+(B+C)

ABooleanexpressionthatisinstandardSOPformis(

)

A:containsonlyoneproductterm

B:noneoftheabove

C:haseveryvariableinthedomainineveryterm

D:theminimumlogicexpression

答案:haseveryvariableinthedomainineveryterm

AdjacentcellsonaKarnaughmapdifferfromeachotherby

A:answerdependsonthesizeofthemap

B:twovariables

C:threevariables

D:

onevariable

答案:

onevariable

SOPstandardformisusefulforconstructingtruthtablesorforimplementinglogicinPLDs.

A:對B:錯

答案:對

LogicsimplificationisstillusefulinnowadaysFPGAdesigns.

A:錯B:對

答案:錯

Insynthesis,anetlistwillbegeneratedtodescribethecircuitcompletely.

A:對B:錯

答案:對

InFPGAdesign,thestepthat“maps”thedesignfromthenetlisttofitittoatargetdeviceisknownas"programming".

A:對B:錯

答案:錯

第四章測試

The74138decodercanalsobeusedas(

).

A:

aMUX

B:

anencoder

C:aDEMUX

D:noneoftheabove

答案:aDEMUX

Assumeyouwanttodecodethebinarynumber0011withanactive-LOWdecoder.Themissinggateshouldbe(

).

A:aNANDgate

B:anORgate

C:

anANDgate

D:aNORgate

答案:aNANDgate

Toexpanda2-bitparalleladdertoa4-bitparalleladder,youmust(

).

A:usetwo2-bitaddersandconnectthesumoutputsofonetothebitinputsoftheother

B:usetwo2-bitadderswiththecarryoutputofoneconnectedtothecarryinputoftheother

C:usefour2-bitadderswithnointerconnections

D:usetwo2-bitadderswithnointerconnections

答案:usetwo2-bitadderswiththecarryoutputofoneconnectedtothecarryinputoftheother

Ifanhex-to-binarypriorityencoderhasits0,3,6,and14inputsattheactivelevel,theactive-HIGHbinaryoutputis(

).

A:0000

B:0011

C:0110

D:1110

答案:1110

ThecontinuousassignmentassignOUT=

select?A:B;specifiestheconditionthatOUT=

()

ifselect=

1,elseOUT=

()

ifselect=

0.

A:

A,B

B:1,0

C:B,A

D:

0,1

答案:

A,B

Considertheinitial

blockinthefollowing:initialbeginA=0;B=0;#10A=1;#20A=0;B=1;EndThenatt=30,Ais

changedto(

)andBto(

).

A:

1,1

B:0,1

C:1,0

D:0,0

答案:0,1

Theinitialstatementexecutesonlyonce,startingfrom

simulationtime0,andmaycontinuewithanyoperationsthataredelayedbyagiven

numberoftimeunits.

A:錯B:對

答案:對

InVerilogHDL,thedefinitionsofmodulesareallowedtobenested.

A:對B:錯

答案:錯

ThevaluezrepresentsanunknownlogicvalueinVerilogHDL.

A:對B:錯

答案:錯

InVerilogHDL,~(1010)is(0101),and!(1010)is0.

A:錯B:對

答案:對

第五章測試

TheoutputofaDlatchwillnotchangeif(

).

A:DisLOW

B:

theoutputisLOW

C:Enableisnotactive

D:alloftheabove

答案:Enableisnotactive

TheDflip-flopshownwill(

).

A:resetonthenextclockpulse

B:toggleonthenextclockpulse

C:setonthenextclockpulse

D:latchonthenextclockpulse

答案:toggleonthenextclockpulse

FortheJ-Kflip-flopshown,thenumberofinputsthatareasynchronousis(

).

A:3B:2C:1D:4

答案:2

AssumetheoutputisinitiallyHIGHonaleadingedgetriggeredJ-Kflipflop.Fortheinputsshown,theoutputwillgofromHIGHtoLOWonwhichclockpulse?

A:3B:2C:4D:1

答案:3

Thetimeintervalillustratediscalled(

).

A:holdtime

B:set-uptime

C:tPHL

D:tPLH

答案:tPLH

TheadvantageofdynamicRAMoverstaticRAMisthat(

).

A:alloftheaboveB:itissimplerandcheaperC:itismuchfasterD:itdoesnotrequirerefreshing

答案:itissimplerandcheaper

Anasynchronous

resetsignalwilloverridetheclockonaFF.

A:對B:錯

答案:對

InVerilogHDL,aninitialbehavioralstatementexecutesonlyonce.

A:錯B:對

答案:對

InaMoore

model,theoutputsofthesequentialcircuitarenotsynchronizedwiththe

clock.

A:對B:錯

答案:錯

TheoutputoftheMealy

machineisthevaluethatispresentimmediatelybeforethe

activeedgeoftheclock.

A:錯B:對

答案:對

第六章測試

TocauseaDflip-floptotoggle,connectthe(

).

A:clocktotheD

input

B:clocktothepresetinput

C:

Q

outputtotheD

input

D:

答案:

A4-bitbinarycounterhasaterminalcountof(

).

A:16B:15C:10D:4

答案:15

Assumetheclockfora4-bitbinarycounteris80kHz.Theoutputfrequencyofthefourthstage(Q3)is(

).

A:320kHz

B:10kHz

C:20kHz

D:5kHz

答案:5kHz

A4-bitparallel-in/parallel-outshiftregisterwillstoredatafor(

).

A:2clockperiods

B:3clockperiods

C:1clockperiod

D:4clockperiods

答案:1clockperiod

AnadvantageofaringcounteroveraJohnsoncounteristhattheringcounter(

).

A:isclearedaftereachcycle

B:allowsonlyonebittochangeatatime

C:isself-decoding

D:hasmorepossiblestatesforagivennumberofflip-flops

答案:isself-decoding

Apossiblesequencefora4-bitringcounteris(

).

A:…1111,1110,1101…

B:…0000,0001,0010…

C:

…1000,0100,0010…

D:

…0001,0011,0111…

答案:

…1000,0100,0010…

Adivide‐by‐N-counterisacounterthatgoesthrougharepeated

sequenceofNstates,anditisalsoknownasamodulo‐Ncounter.

A:錯B:對

答案:對

Forcounterswithunusedstates,itisnecessarytoensurethatthecircuiteventuallygoesintooneofthevalidstatessothatitcanresumenormaloperation.

A:錯B:對

答案:對

Fortransmission,datafromaUARTissentin

synchronousparallelform.

A:錯B:對

答案:錯

Themaximummodulusofacounteris,

wherenisthenumberofstages(flip-flops)inthecounter.

A:對B:錯

答案:錯

第七章測試

StaticRAMis(

).

A:volatilereadonlymemory

B:

nonvolatileread/writememory

C:volatileread/writememory

D:nonvolatilereadonlymemory

答案:volatileread/writememory

Anonvolatilememoryisonethat(

)

A:mustberefreshedregularly

B:

retainsdatawithoutpowerapplied

C:

requiresaclock

D:alloftheabove

答案:

retainsdatawithoutpowerapplied

TheadvantageofdynamicRAMoverstaticRAMisthat(

).

A:itissimplerandcheaper

B:itdoesnotrequirerefreshing

C:alloftheabove

D:itismuchfaster

答案:itissimplerandcheaper

A4-bitparallel-in/parallel-outshiftregisterwillstoredatafor(

).

A:3clockperiodB:2clockperiodC:4clockperiodD:1clockperiod

答案:1clockperiod

WhendataisreadfromRAM,thememorylocationis(

).

A:unchanged

B:settoall1’safterthereadoperation

C:destroyed

D:clearedafterthereadoperation

答案:unchanged

Thefirststepinareadorwriteoperationforarandomaccessmemoryisto(

).

A:placeavalidaddressontheaddressbus

B:enablethememory

C:

sendorobtainthedata

D:startarefreshcycle

答案:placeavalidaddressontheaddressbus

AddressmultiplexingcanreducethenumberofpinsintheICpackage.

A:錯B:對

答案:對

OneofthemajorapplicationsofSRAMsisincachememoriesincomputers.

A:對B:錯

答案:對

RAMisusedinacomputerto

storetheBIOS(BasicInput/Output

System.

A:錯B:對

答案:錯

Memoryexpansion

isaccomplishedbyaddinganappropriatenumberofmemorychipstotheaddress,data,

andcontrolbuses.

A:對B:錯

答案:對

第八章測試

Thenumberofcomparatorsrequiredina10-bitflashADCis(

).

A:511

B:1023

C:255

D:4095

答案:1023

Ifananti-aliasingfilterisnotusedindigitizingasignaltherecoveryprocess(

)

A:alloftheabove

B:isslowed

C:willhav