AT89C2051介紹中英文對照外文翻譯文獻

自動售貨機畢業(yè)論文PAGE28PAGE29中英文資料對照外文翻譯附錄A：IntroduceofAT89C20511DescriptioncommonlyDescriptionTheAT89C2051isalow-voltage,high-performanceCMOS8-bitmicrocomputerwith2KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standardMCS-51instructionset.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C2051isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89C2051providesthefollowingstandardfeatures:2KbytesofFlash,128bytesofRAM,15I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,aprecisionanalogcomparator,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C2051isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.Thepower-downmodesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.1.2Features?CompatiblewithMCS-51?Products?2KBytesofReprogrammableFlashMemory–Endurance:1,000Write/EraseCycles?0Vto6VOperatingRange?FullyStaticOperation:0Hzto24MHz?Two-levelProgramMemoryLock?128x8-bitInternalRAM?15ProgrammableI/OLines?Two16-bitTimer/Counters?SixInterruptSources?ProgrammableSerialUARTChannel?DirectLEDDriveOutputs?On-chipAnalogComparator?Low-powerIdleandPower-downModespinconfiguration1.4PinDescriptionVCCSupplyvoltage.GNDGround.Port1Port1isan8-bitbi-irectionalI/Oport.PortpinsP1.2toP1.7provideinternalpullups.P1.0andP1.1requireexternalpullups.P1.0andP1.1alsoserveasthepositiveinput(AIN0)andthenegativeinput(AIN1),respectively,oftheon-chipprecisionanalogcomparator.ThePort1outputbufferscansink20mAandcandriveLEDdisplaysdirectly.When1sarewrittentoPort1pins,theycanbeusedasinputs.WhenpinsP1.2toP1.7areusedasinputsandareexternallypulledlow,theywillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivescodedataduringFlashprogrammingandverification.Port3Port3pinsP3.0toP3.5,P3.7aresevenbi-irectionalI/Opinswithinternalpullups.P3.6ishard-wiredasaninputtotheoutputoftheon-chipcomparatorandisnotaccessibleasageneralpurposeI/Opin.ThePort3outputbufferscansink20mA.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C2051aslistedbelow:Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.RSTResetinput.AllI/Opinsareresetto1sassoonasRSTgoeshigh.HoldingtheRSTpinhighfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.VCCSupplyvoltage.GNDGround.Eachmachinecycletakes12oscillatororclockcycles.XTAL1Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.XTAL2Outputfromtheinvertingoscillatoramplifier.1.5OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.2RestrictionsonCertainInstructionsTheAT89C2051andisaneconomicalandcost-effectivememberofAtmel’sgrowingfamilyofmicrocontrollers.Itcontains2Kbytesofflashprogrammemory.ItisfullycompatiblewiththeMCS-51architecture,andcanbeprogrammedusingtheMCS-51instructionset.However,thereareafewconsiderationsonemustkeepinmindwhenutilizingcertaininstructionstoprogramthisdevice.Alltheinstructionsrelatedtojumpingorbranchingshouldberestrictedsuchthatthedestinationaddressfallswithinthephysicalprogrammemoryspaceofthedevice,whichis2KfortheAT89C2051.Thisshouldbetheresponsibilityofthesoftwareprogrammer.Forexample,LJMP7E0HwouldbeavalidinstructionfortheAT89C2051(with2Kofmemory),whereasLJMP900Hwouldnot.2.1Branchinginstructions:LCALL,LJMP,ACALL,AJMP,SJMP,JMP@A+DPTRTheseunconditionalbranchinginstructionswillexecutecorrectlyaslongastheprogrammerkeepsinmindthatthedestinationbranchingaddressmustfallwithinthephysicalboundariesoftheprogrammemorysize(locations00H7FFHforthe89C2051).Violatingthephysicalspacelimitsmaycauseunknownprogrambehavior.CJNE[...],DJNZ[...],JB,JNB,JC,JNC,JBC,JZ,JNZWiththeseconditionalbranchinginstructionsthesameruleaboveapplies.Again,violatingthememoryboundariesmaycauseerraticexecution.Forapplicationsinvolvinginterruptsthenormalinterruptserviceroutineaddresslocationsofthe80C51familyarchitecturehavebeenpreserved.2.2MOVX-relatedinstructions,DataMemory:TheAT89C2051contains128bytesofinternaldatamemory.Thus,intheAT89C2051thestackdepthislimitedto128bytes,theamountofavailableRAM.ExternalDATAmemoryaccessisnotsupportedinthisdevice,norisexternalPROGRAMmemoryexecution.Therefore,noMOVX[...]instructionsshouldbeincludedintheprogram.Atypical80C51assemblerwillstillassembleinstructions,eveniftheyarewritteninviolationoftherestrictionsmentionedabove.Itistheresponsibilityofthecontrollerusertoknowthephysicalfeaturesandlimitationsofthedevicebeingusedandadjusttheinstructionsusedcorrespondingly.2.3ProgramMemoryLockBitsOnthechiparetwolockbitswhichcanbeleftunprogrammed(U)orcanbeprogrammed(P)toobtaintheadditionalfeatureslistedinthetablebelow:3TowmodeIdleModeandPowerDownMode3.1IdleModeInidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.P1.0andP1.1shouldbesetto“0”ifnoexternalpullupsareused,orsetto“1”ifexternalpullupsareused.Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.3.2Power-downModeInthepowerdownmodetheoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.4ProgrammingTheFlashTheAT89C2051isshippedwiththe2Kbytesofon-chipPEROMcodememoryarrayintheerasedstate(i.e.,contents=FFH)andreadytobeprogrammed.Thecodememoryarrayisprogrammedonebyteatatime.Oncethearrayisprogrammed,tore-programanynon-blankbyte,theentirememoryarrayneedstobeerasedelectrically.thenextcyclemaybegin.DataPollingmaybeginanytimeafterawritecyclehasbeeninitiated.4.1InternalAddressCounterTheAT89C2051containsaninternalPEROMaddresscounterwhichisalwaysresetto000HontherisingedgeofRSTandisadvancedbyapplyingapositivegoingpulsetopinXTAL1.4.2ProgrammingAlgorithmToprogramtheAT89C2051,thefollowingsequenceisrecommended.(1).Power-upsequence:ApplypowerbetweenVCCandGNDpinsSetRSTandXTAL1toGND(2).SetpinRSTto“H”SetpinP3.2to“H”(3).Applytheappropriatecombinationof“H”or“L”logiclevelstopinsP3.3,P3.4,P3.5,P3.7toselectoneoftheprogrammingoperationsshowninthePEROMProgrammingModestable.ToProgramandVerifytheArray:(4).ApplydataforCodebyteatlocation000HtoP1.0toP1.7.(5).RaiseRSTto12Vtoenableprogramming.(6).PulseP3.2oncetoprogramabyteinthePEROMarrayorthelockbits.Thebyte-writecycleisself-timedandtypicallytakes1.2ms.(7).Toverifytheprogrammeddata,lowerRSTfrom12Vtologic“H”levelandsetpinsP3.3toP3.7totheappropiatelevels.OutputdatacanbereadattheportP1pins.(8).Toprogramabyteatthenextaddresslocation,pulseXTAL1pinoncetoadvancetheinternaladdresscounter.ApplynewdatatotheportP1pins.(9).Repeatsteps5through8,changingdataandadvancingtheaddresscounterfortheentire2Kbytesarrayoruntiltheendoftheobjectfileisreached.10.Power-offsequence:setXTAL1to“L”setRSTto“L”TurnVCCpoweroff4.3DataPollingTheAT89C2051featuresDataPollingtoindicatetheendofawritecycle.Duringawritecycle,anattemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendataonP1.7.Oncethewritecyclehasbeencompleted,truedataisvalidonalloutputs,andthenextcyclemaybegin.DataPollingmaybeginanytimeafterawritecyclehasbeeninitiated.4.4ProgramVerifyIflockbitsLB1andLB2havenotbeenprogrammedcodedatacanbereadbackviathedatalinesforverification:1.Resettheinternaladdresscounterto000HbybringingRSTfrom“L”to“H”.2.ApplytheappropriatecontrolsignalsforReadCodedataandreadtheoutputdataattheportP1pins.3.PulsepinXTAL1oncetoadvancetheinternaladdresscounter.4.ReadthenextcodedatabyteattheportP1pins.5.Repeatsteps3and4untiltheentirearrayisread.4.5ReadingtheSignatureBytesThesignaturebytesarereadbythesameprocedureasanormalverificationoflocations000H,001H,and002H,exceptthatP3.5andP3.7mustbepulledtoalogiclow.Thevaluesreturnedareasfollows.(000H)=1EHindicatesmanufacturedbyAtmel(001H)=21Hindicates89C2051附錄B：AT89C2051介紹1概述1.1功能特性概述AT89C2051是一個有2k字節(jié)可編程EPROM的高性能的微控制器。本器件與工業(yè)標(biāo)準(zhǔn)MCS-51TM的指令組和引腳兼容。ATMEL半導(dǎo)體公司的AT89C2051是一種功能強大的微控制器，它對很多嵌入式控制應(yīng)用提供了一個高度靈活的有效的解決方案。AT89C2051有以下特點：2k字節(jié)EPROM、128字節(jié)RAM、15根I/O線、二個16位定時/計數(shù)器、五個向量二級的中斷結(jié)構(gòu)、一個全雙向的串行口、一個精密的模擬比較器、片內(nèi)振蕩器和時鐘電路。此外，AT89C2051支持二種軟件可選的電源節(jié)約方式。空閑方式停止CPU而讓RAM、定時/計數(shù)器、串行口和中斷系統(tǒng)繼續(xù)有效。掉電方式保存RAM的內(nèi)容但振蕩器停振以禁止芯片所有的其它功能直到下一次硬件復(fù)位。1.2主要性能參數(shù)與MCS-51TM產(chǎn)品兼容2k字節(jié)可編程EPROM1000次寫周期※2.7V至6V電壓工作范圍※0MHz/24MHz工作頻率※具有加密陣列的二級程序存儲器加鎖※128字節(jié)SRAM※15根可編程I/O線※二個16位定時/計數(shù)器※可編程的串行USART※五個中斷源※輸出可直接驅(qū)動LED※片內(nèi)模擬比較器※低功耗空閑和掉電方式1.3引腳配置1.4引腳說明Vcc電源電壓。GND地。Port1口1是一個8位雙向I/O口?？谝_P1.2至P1.7提供內(nèi)部上拉。P1.0和P1.1需要外部上拉。P1.0和P1.1也可以分別用作片內(nèi)精密模擬比較器的正輸入端（AIN0）和負輸入端（AIN1）?？?的輸出緩沖器能吸入20mA電流并能直接驅(qū)動LED顯示。當(dāng)“1”引腳時，它們可被用作輸入腳。當(dāng)引腳P1.2至P1.7被用作輸入并被外部拉低時，由于內(nèi)部上拉它們將供出電流（IIL）。當(dāng)EPROM編程時和編程檢驗時Port1也接收代碼數(shù)據(jù)。Port3口3的引腳P3.0至P3.5、P3.7是7個帶有內(nèi)部上拉的雙向I/O引腳。P3.6是片內(nèi)比較器的輸出腳而不能作為普通的I/O腳訪問。Port3的輸出緩沖器可吸入20mA。當(dāng)“1”寫入Port3引腳時，它們被內(nèi)部的上拉拉高并被用作輸入。作為輸入口，被外部拉低的Port3引腳將因為上拉而供出電流（TIL）。Port3也能用作如下表所列AT89C2051的各種特殊功能：引腳引腳功能P3.0RXD（串行輸入口）P3.1TXD(串行輸出口)P3.2INT0(外部中斷0)P3.3INT1(外部中斷1)P3.4T0(定時器0外部輸入端)P3.5T1(定時器1外部輸入端)Port3在EPROM編程時和編程檢驗時也接收某些控制信號。RST復(fù)位輸入。只要RST一變高，所有的I/O引腳都復(fù)位為“1”。在振蕩器工作時，保持RST腳為高電位經(jīng)二個機器周期，器件即復(fù)位。這個引腳在EPROM編程時，也接收12.75V編程電源電壓（Vpp）。XTAL1反相振蕩器的放大器輸入端和內(nèi)部時鐘工作電路的輸入端。XTAL2反相振蕩器的放大器輸出端。1.5推薦的振蕩器電路XTAL1和XTAL2各為內(nèi)部放大器的輸入和輸出端，如下圖所示意的那樣。可采用石英晶體或陶瓷震蕩器組成時鐘震蕩器，如需從外部輸入時鐘驅(qū)動AT89C2051，時鐘信號從XTAL1輸入，XTAL2應(yīng)懸空。由于輸入到內(nèi)部電路是經(jīng)過一個2分頻觸發(fā)器，所以輸入的外部時鐘信號無需特殊要求，但它必須符合電平的最大和最小及時序規(guī)范。石英晶體時：C1，C2=30pF+（—石英晶體時：C1，C2=30pF+（—）10pF陶瓷濾波器：C1，C2=40pF+（—）10pF內(nèi)部震蕩電路圖22關(guān)于某些指令的限制AT89C2051是AT89C2051是經(jīng)濟型低價位的控制器，它有2k字節(jié)的Flash閃存程序存儲器。它與MCS-51結(jié)構(gòu)完全兼容，并能用MCS-51指令組編程。但是當(dāng)利用某些指令來對此器件編程時，有少數(shù)是必須考慮的。和跳轉(zhuǎn)或分支有關(guān)的指令有一定的空間約束，使目的地址能安全落在AT89C2051的2K字節(jié)的物理程存儲器空間內(nèi)，程序員必須注意這一點。對于2K字字存儲器的AT89C2051來說，LJMP7E0H是一條有效指令，而LJMP900H則為無效指令2.1分支指令對于LCALL、LJMP、ACALL、AJMP、SJMP、JMP@A+DPTR這些無條件分支指令只有在編程者注意到分支的目的地址必須落在程序存儲器的物理邊界之內(nèi)對AT89C2051地址是000H至7FFH）才能正確地執(zhí)行。違反物理空間限制將引起不知道的程序運行情況。CJNE[.]、DJNZ[.]、JB、JNB、JC、JNC、JBC、JZ、JNZ對這些條件分支指令也適用上述同樣的規(guī)則。超出存儲器邊界將引起錯誤的執(zhí)行。對涉及中斷的應(yīng)用，80C51規(guī)定的中斷服務(wù)子程序的地址位都已經(jīng)保存。2.2與MOVX有關(guān)的指令，數(shù)據(jù)存儲器AT89C2051有128字節(jié)內(nèi)部數(shù)據(jù)存儲器。這樣，在AT89C20511中堆棧深度被限制為128字節(jié)，即所有RAM的數(shù)量。該器件不支持外部DATA存儲器的訪問，也不支持外部程序存儲器的執(zhí)行。所以，程序中不能包含MOVX指令。一個典型的80C51匯編器仍可用來匯編指令，即使它們違反了上面所說的限制?？刂破饔脩舻呢?zé)任是知道所用器件的物理特點和限制并相應(yīng)地調(diào)整所用的指令。2.3程序存儲器的加密AT89C2051可使用對于芯片上的兩個加密進行編程（P）或不編程（U）來得到如下表的功能：程序加密位LB1LB2保護類型1UU無程序加密功能2PU禁止進一步進行FLASH閃速編程3PP同方式2同時禁止效驗3省電方式有兩種省電方式可供使用，即空閑方式（IdleMode）和掉電方式（PowerDownMode）。3.1空閑方式在空閑方式，CPU讓自己睡眠而所有片內(nèi)的外圍都保持激活。這種方式由軟件調(diào)用。在本方式時片內(nèi)RAM和所有的特殊功能寄存器的內(nèi)容都不改變。空閑方式可由任何使能的中斷或一次硬件復(fù)位來終止。如果不使用外部上拉則P1.0和P1.1必須被置為“0”，如果使用外部上拉則置為“1”。當(dāng)空閑方式由一次硬件復(fù)位終止時，必須注意，這時器件通常要恢復(fù)程序的執(zhí)行，在內(nèi)部的復(fù)位規(guī)則起作用以前，它要停止等待兩個機器周期。在這時，片內(nèi)硬件禁止訪問內(nèi)部RAM，但不禁止訪問端口引腳。當(dāng)空閑方式由復(fù)位終止時，為了消除對端口引腳不希望的寫入的可能性，在調(diào)用空閑方式指令后面的指令必須不是向端口引腳或外部存儲器寫入的指令。3.2掉電方式在掉電模式下，震蕩器停止工作，進入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退