如何在IP和SOC設(shè)計(jì)中保證ESD的健壯性

EnsuringESDRobustnessforIPsand

SoCsChallengesinESD

DesignSystematicESDverificationisamusttoensurefirstsilicon

successPower/GroundislandsUniqueESD

requirementsHigher

pin-countsHigher

IntegrationStacked

DIEHBM,Memory

CubeSystemin

PackageEvolving

TechnologiesThinneroxidesThinner

InterconnectsSmaller

devicesDesignwindowTechnology

node(nm)ShrinkingDesign

Margins2July31,

2017ANSYSPathFinder?:SoCandIPESD

IntegrityTargetAnalysisPin2PinESD

ConnectivityResistance

ChecksCurrentDensity

ChecksLayout

(DEF/GDS)TechnologyClamp

ModelsESD

rulesPG+Signal

ExtractionClamp

Modeling3July31,

2017AnalogixusepathfinderforESD

sign-off4July31,

2017ESDconnectivity

checkDowehaveunconnectedClampInstance

？DowehavebumpsisolatedfromClamps

?DowehaveproperstageofESDconnectivityforeachnet-pair

?RulebasedResistance

checkIsourESDpath’sresistancesmallenoughtoprotectfunctioncircuit

?RulebasedCurrentDensity

checkIsourESDpath’sroutingstrongenoughtobearbigESDdischargecurrent

?Analogcase

overviewProcessTSMC

28HPC+Size6350umx4770umNo.of

Bumps259Bumps-14Power16Ground65Signal5July31,

2017HowtorecognizeESD

cell？DrawingcorrespondingGDSmarklayeronESDcell

（clamp/diode）MarklayercanbeusedforBoththeESDanddeviceidentificationpurposesin

GDS2DBDefinedifferentlayernumberinGDSlayermaptoidentifydifferentESDcells6July31,

2017HowtomodelESD

cell？1. UseR-ON/R-OFFmodeltodefineeachtypeofESD

cellDefineslegalESDdischargepathandresistancevaluesforbothcurrentdischargedirectionsResistancevalueis0.1Ωwhenclamp

ison,Whencurrentfromgndtopwr,clampis

off7July31,

2017HowtomodelESD

cell？2. UseIV-CurvetodefineeachtypeofESD

cellAllclampcellsaremodeledasresistorswithIV

curve8July31,

2017

VDD VDDVDDVDDGNDGNDGND

AGNDAGND

AGNDR1

R2FullSoC

CapacityMulti-threaded

solveSimpleandcustomizablerulesIsolatedBumps/Clamps

ChecksPin2PinESDConnectivity

ChecksPin2PinResistance

ChecksLayout-based

DebugPass/FailReportandResistanceBottleneck

IdentificationReffSIGSignalI/OSIGSignalI/O9July31,

2017PowerclampsESDConnectivityandRule

ChecksESDConnectivity

CheckListofBumpsIsolatedfrom

ClampsBumpsdoesn'thaveconnectionstoclampcellwillbereported

asshown,includesbumpname/location/layer/net

name10July31,

2017ESDConnectivity

CheckNet-PairESD

connectivityReportsthemin/maxESDstagebetweenESDnetpairMinimum2stagesandupto4stagesESDconnectionbetweenAVDD10_CKandAVDD18_TXasshown11July31,

2017S1C1D1D3D2D4D5D6VDD1VSSVSS1 2VDD2C2Resistancecheckrule

:B2B(PowerpadtoGroundpad)<1

OhmB2B(SignalpadtoPowerpad)<1

OhmB2B(GroundpadtoSignalpad)<1

OhmB2B(Ground1padtoGround2pad)<1

OhmC2C(DiodetoClamp)<1

OhmPower2GroundSignal2PowerGroud2SignalGround2GroundDiode2Clamp(PowerBus)RuleBasedRES

Check12July31,

2017AnalogixRCheck

CaseMin-resarcforthisBumphave3.2ohmres,biggerthantheB2C_Rthreshold0.5ohmThelongroutingfromBumptoClamp

causehigh

resistanceR↑AP=>

M1Useshortpathtrace(SPT)utilitytohighlightthemin-respathfromtheBumptotheselectedclamp13July31,

2017Bump(AP)Clamp(M1)S1C1D1D3D2D4D5D6VSS1VSS2VDD2C2CurrentDensitycheckrule

:1.Bump2Clampcheck:fromAllpadto

correspondingClamp/Diodezap1.3A

current1.3A1.3A1.3AVDD114July31,

2017RuleBasedCD

CheckAnalogixCDCheck

CaseBadM1connectioncause

theEMviolationMaxEMinthisnetis188%,biggerthanthethreshold100%15July31,

2017STAGEWALLTIMEMEMORY

USAGE(GB)GDS2DB42mins49SetupDesign+

Extraction2hour56

mins73ResistanceCheckBumptoBumpCheck(AllARCs

)3hour10

mins79ClamptoClamp

Check(DiodetoClamp

)CurrentDensityCheckBumptoClampCheck(AllARCs

)2hour20

mins10316July31,

2017*thisperformancearegotwithoutanyreductionindesignormetal

geometries.Performance

SummaryESDIntegrityVerificationandSign-offwith

PathFinderToplevelESDPlanningP2P

ResistanceCoreClamp

ChecksCurrentDensity

CheckIO/IPESD

PlanningESDBus

ResistanceCurrent

DensityCross-Domain

CheckSOClevelESD

Sign-offESD

ConnectivityIPIntegration

ChecksPackageLevel

ChecksSystemleve