計(jì)算機(jī)專業(yè)英語chapter2

ComputerEnglish

Chapter2Organizationof

Computers

Chapter1TheHistoryandFutureofComputers

Keypoints:

usefultermsandorganization

ofcomputers.H

Difficultpoints:

describingtheorganizationof

computers

計(jì)算機(jī)專業(yè)英語1-42

Chapter1TheHistoryandFutureofComputers

Requiremeiits:

1.Termsofcomputerhardware

2.Organizationofcomputersandtheirfunctions

3.掌握專業(yè)詞匯的構(gòu)成規(guī)律，特別是常用詞綴及復(fù)合詞

的構(gòu)成

計(jì)算機(jī)專業(yè)英語1-43

Chapter1TheHistoryandFutureofComputers

2.1BasicOrganizationofComputers

NewWords&Expressions:

instructioncycle指令周期decodevt.解碼，譯解

busu?總線pinsn.插腳，管腳

uppermostadj?最高的；adv.在最上addressbus地址總線

databus數(shù)據(jù)總線viaprep?經(jīng)，通過，經(jīng)由

multibit多位bidirectional雙向的

unidirectional單向的hierarchyn?層次，層級(jí)

microprocessorn?微處理器registern?寄存器

timingn.定時(shí)；時(shí)序；時(shí)間選擇synchronizevt?使…同步

assertvt.主張，發(fā)出deassertvt.撤銷

triggervt?引發(fā)，引起，觸發(fā)mapv?映射

portn?端口

Abbreviations:

CPU(CentralProcessingUnit)中央處理器

I/O(Input/Output)輸入輸出(設(shè)備)

計(jì)算機(jī)專業(yè)英語1-44

Chapter1TheHistoryandFutureofComputers

2.1BasicOrganizationofComputers

Memory

Subsystem

Fig.2-1Genericcomputerorganization

計(jì)算機(jī)專業(yè)英語1-45

Chapter1TheHistoryandFutureofComputers

2.1BasicOrganizationofComputers

Mostcomputersystems,fromtheembeddedcontrollersfoundin

automobilesandconsumerappliancestopersonalcomputers

andmainframes,havethesamebasicorganization.This

organizationhasthreemaincomponents:theCPU,thememory

subsystem,andtheI/Osubsystem.Thegenericorganizationof

thesecomponentsisshowninFigure2-1.

大多數(shù)計(jì)算機(jī)系統(tǒng)，從汽車和日用電器中的嵌入式控制器到

個(gè)人計(jì)算機(jī)和大型主機(jī)，都具有相同的基本組成。其基本組

成包括三個(gè)主要部件：CPU、存儲(chǔ)器子系統(tǒng)和I/O子系統(tǒng)。這

些部件的一般組成如圖24所示。

計(jì)算機(jī)專業(yè)英語1-46

Chapter1TheHistoryandFutureofComputers

2.1.1SystemBuses

Physically,abusisasetofwires.Thecomponentsofthecomputerare

connectedtothebuses.Tosendinformationfromonecomponentto

another,thesourcecomponentoutputsdataontothebus.Thedestination

componenttheninputsthisdatafromthebus.Asthecomplexityofa

computersystemincreases,itbecomesmoreefficient(intermsof

minimizingconnections)atusingbusesratherthandirectconnections

betweeneverypairofdevices.Busesuselessspaceonacircuitboardand

requirelesspowerthanalargenumberofdirectconnections.Theyalso

requirefewerpinsonthechiporchipsthatcomprisetheCPU.

從物理上來說，總線就是一組導(dǎo)線。計(jì)算機(jī)的部件就是連在總線上的。為了將信息從

一個(gè)部件傳到另一個(gè)部件，源部件先將數(shù)據(jù)輸出到總線上，然后目標(biāo)部件再?gòu)目偩€上

接受這些數(shù)據(jù)。隨著計(jì)算機(jī)系統(tǒng)復(fù)雜性的不斷增長(zhǎng)，使用總線比每個(gè)設(shè)備對(duì)之間直接

連接要有效得多(就減少連接數(shù)量而言)。與大量的直接連接相比，總線使用較少的

電路板空間，耗能更少，并且在芯片或組成CPU的芯片組上需要較少的引腳。

計(jì)算機(jī)專業(yè)英語1-47

Chapter1TheHistoryandFutureofComputers

2.1.1SystemBuses

ThesystemshowninFigure2-1hasthreebuses.Theuppermostbusinthisfigure

istheaddressbus.WhentheCPUreadsdataorinstructionsfromorwritesdatato

memory,itmustspecifytheaddressofthememorylocationitwishestoaccess.It

outputsthisaddresstotheaddressbus;memoryinputsthisaddressfromthe

addressbusanduseittoaccessthepropermemorylocation.EachI/Odevices,

suchasakeyboard,monitor,ordiskdrive,hasauniqueaddressaswell.When

accessinganI/Odevice,theCPUplacestheaddressofthedeviceontheaddress

bus.Eachdevicecanreadtheaddressoffofthebusanddeterminewhetheritis

thedevicebeingaccessedbytheCPU.Unliketheotherbuses,theaddressbus

alwaysreceivesdatafromtheCPU;theCPUneverreadstheaddressbus.

圖2”所示的系統(tǒng)包括三組總線。最上面的是地址總線。當(dāng)CPU從存儲(chǔ)器讀取數(shù)據(jù)或

指令，或?qū)憯?shù)據(jù)到存儲(chǔ)器時(shí)，它必須指明將要訪問的存儲(chǔ)器單元地址。CPU將地址

輸出到地址總線上，而存儲(chǔ)器從地址總線上讀取地址，并且用它來訪問正確的存儲(chǔ)單

元。每個(gè)I/O設(shè)備，比如鍵盤、顯示器或者磁盤，同樣都有一個(gè)唯一的地址。當(dāng)訪問

某個(gè)I/O設(shè)備時(shí)，CPU將此設(shè)備的地址放到地址總線上。每一個(gè)設(shè)備均從總線上讀取

地址并且判斷自己是否就是CPU正要訪問的設(shè)備。與其他總線不同，地址總線總是

從CPU上接收信息，而CPU從不讀取地址總線。

計(jì)算機(jī)專業(yè)英語1-48

Chapter1TheHistoryandFutureofComputers

2.1.1SystemBuses

Dataistransferredviathedatabus.WhentheCPUfetchesdata

frommemory,itfirstoutputsthememoryaddressonitsaddress

bus.Thenmemoryoutputsthedataontothedatabus;theCPUcan

thenreadthedatafromthedatabus.Whenwritingdatatomemory,

theCPUfirstoutputstheaddressontotheaddressbus,then

outputsthedataontothedatabus.Memorythenreadsandstores

thedataattheproperlocation.Theprocessesforreadingdatafrom

andwritingdatatotheI/Odevicesaresimilar.

數(shù)據(jù)是通過數(shù)據(jù)總線傳送的。當(dāng)CPU從存儲(chǔ)器中取數(shù)據(jù)時(shí)，它首先把存儲(chǔ)器

地址輸出到地址總線上，然后存儲(chǔ)器將數(shù)據(jù)輸出到數(shù)據(jù)總線上，這樣CPU就

可以從數(shù)據(jù)總線上讀取數(shù)據(jù)了。當(dāng)CPU向存儲(chǔ)器中寫數(shù)據(jù)時(shí)，它首先將地址

輸出到地址總線上，然后把數(shù)據(jù)輸出到數(shù)據(jù)總線上，這樣存儲(chǔ)器就可以從數(shù)

據(jù)總線上讀取數(shù)據(jù)并將它存儲(chǔ)到正確的單元中。對(duì)I/O設(shè)備讀寫數(shù)據(jù)的過程

與此類似。

計(jì)算機(jī)專業(yè)英語1-49

Chapter1TheHistoryandFutureofComputers

2.1.1SystemBuses

Thecontrolbusisdifferentfromtheothertwobuses.Theaddressbusconsistsof

nlines,whichcombinetotransmitonen-bitaddressvalue.Similarly,thelinesof

thedatabusworktogethertotransmitasinglemultibitvalue.Incontrast,the

controlbusisacollectionofindividualcontrolsignals.Thesesignalsindicate

whetherdataistobereadintoorwrittenoutoftheCPU,whethertheCPUis

accessingmemoryoranI/Odevice,andwhethertheI/Odeviceormemoryis

readytotransferdata.AlthoughthisbusisshownasbidirectionalinFigure2-1,it

isreallyacollectionof（mostly）unidirectionalsignals.Mostofthesesignalsare

outputfromtheCPUtothememoryandI/Osubsystems,althoughafeware

outputbythesesubsystemstotheCPU.Weexaminethesesignalsinmoredetail

whenwelookattheinstructioncycleandthesubsysteminterface.

控制總線與以上兩種總線都不相同。地址總線由n根線構(gòu)成，n根線聯(lián)合傳送一個(gè)n位

的地址值。類似地，數(shù)據(jù)總線的各條線合起來傳輸一個(gè)單獨(dú)的多位值。相反，控制總

線是單根控制信號(hào)的集合。這些信號(hào)用來指示數(shù)據(jù)是要讀入CPU還是要從CPU寫出，

CPU是要訪問存儲(chǔ)器還是要訪問DO設(shè)備，是I/O設(shè)備還是存儲(chǔ)器已就緒要傳送數(shù)據(jù)等

等。雖然圖2?1所示的控制總線看起來是雙向的，但它實(shí)際上（主要）是單向（大多

數(shù)都是）信號(hào)的集合。大多數(shù)信號(hào)是從CPU輸出到存儲(chǔ)器與I/O子系統(tǒng)的，只有少數(shù)

是從這些子系統(tǒng)輸出到CPU的。在介紹指令周期和子系統(tǒng)接口時(shí)，我們將詳細(xì)地討論

這些信號(hào)。計(jì)算機(jī)專業(yè)英語1-50

Chapter1TheHistoryandFutureofComputers

2.1.1SystemBuses

Asystemmayhaveahierarchyofbuses.Forexample,itmayuse

itsaddress,data,andcontrolbusestoaccessmemory,andanI/O

controller.TheI/Ocontroller,inturn,mayaccessallI/Odevices

usingasecondbus,oftencalledanI/Obusoralocalbus.

一個(gè)系統(tǒng)可能具有分層次的總線。例如，它可能使用地址、數(shù)

據(jù)和控制總線來訪問存儲(chǔ)器和I/O控制器。I/O控制器可能依次

使用第二級(jí)總線來訪問所有的I/O設(shè)備，第二級(jí)總線通常稱為

I/O總線或者局部總線。

計(jì)算機(jī)專業(yè)英語1-51

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Theinstructioncycleistheprocedureamicroprocessorgoesthroughtoprocess

aninstruction.Firstthemicroprocessorfetches,orreads,theinstructionfrom

memory.Thenitdecodestheinstruction,determiningwhichinstructionithas

fetched.Finally,itperformstheoperationsnecessarytoexecutetheinstruction.

(Somepeoplealsoincludeanadditionalelementintheinstructioncycletostore

results.Here,weincludethatoperationaspartoftheexecutefunction.)Eachof

thesefunctions—fetch,decode,andexecute—consistsofasequenceofoneor

moreoperations.

指令周期是微處理器完成一條指令處理的步驟。首先，微處理器從存儲(chǔ)器讀

取指令，然后將指令譯碼，辯明它取的是哪一條指令。最后，它完成必要的

操作來執(zhí)行指令(有人認(rèn)為在指令周期中還要包括一個(gè)附加的步驟來存儲(chǔ)結(jié)

果，這里我們把該操作當(dāng)作執(zhí)行功能的一部分)。每一個(gè)功能——讀取、譯

碼和執(zhí)行都包括一個(gè)或多個(gè)操作。

計(jì)算機(jī)專業(yè)英語1-52

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Let'sstartwherethecomputerstarts,withthemicroprocessor

fetchingtheinstructionfrommemory.First,themicroprocessor

placestheaddressoftheinstructionontotheaddressbus.The

memorysubsysteminputsthisaddressanddecodesittoaccessthe

siredmemorylocation.(Welookathowthisdecodingoccurs

whenweexaminethememorysubsysteminmoredetaillaterin

thischapter.)

我們從微處理器從存儲(chǔ)器中取指令開始講述。首先，微處理器

把指令的地址放到地址總線上，然后，存儲(chǔ)器子系統(tǒng)從總線上

輸入該地址并予以譯碼，去訪問指定的存儲(chǔ)單元。(譯碼是如

何進(jìn)行的，我們將在后面的章節(jié)中介紹存儲(chǔ)器子系統(tǒng)是更為詳

細(xì)的討論。)

計(jì)算機(jī)專業(yè)英語1-53

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Afterthemicroprocessorallowssufficienttimeformemorytodecodethe

addressandaccesstherequestedmemorylocation,themicroprocessorassertsa

READcontrolsignal.TheREADsignalisasignalonthecontrolbuswhichthe

microprocessorassertswhenitisreadytoreaddatafrommemoryoranI/O

device.(Someprocessorshaveadifferentnameforthissignal,butall

microprocessorshaveasignaltoperformthisfunction.)Dependingonthe

microprocessor,theREADsignalmaybeactivehigh(asserted-1)oractivelow

(asserted-0).

當(dāng)微處理器為存儲(chǔ)器留出充足的時(shí)間來對(duì)地址譯碼和訪問所需的存儲(chǔ)單元之

后，微處理器發(fā)出一個(gè)讀（READ）控制信號(hào)。當(dāng)微處理器準(zhǔn)備好可以從存

儲(chǔ)器或是I/O設(shè)備讀數(shù)據(jù)時(shí)，它就在控制總線上發(fā)一個(gè)讀信號(hào)。（一些處理器

對(duì)于這個(gè)信號(hào)有不同的名字，但所有處理器都有這樣的信號(hào)來執(zhí)行這個(gè)功

能。）根據(jù)微處理器的不同，讀信號(hào)可能是高電平有效（信號(hào)=1）,也可能

是低電平有效（信號(hào)=0）。

計(jì)算機(jī)專業(yè)英語1-54

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

WhentheREADsignalisasserted,thememorysubsystemplaces

theinstructioncodetobefetchedontothecomputersystem'sdata

bus,Themicroprocessortheninputsthisdatafromthebusand

storesitinoneofitsinternalregisters.Atthispoint,the

microprocessorhasfetchedtheinstruction.

讀信號(hào)發(fā)出后，存儲(chǔ)器子系統(tǒng)就把要取的指令碼放到計(jì)算機(jī)的

數(shù)據(jù)總線上，微處理器就從數(shù)據(jù)總線上輸入該數(shù)據(jù)并且將它存

儲(chǔ)在其內(nèi)部的某個(gè)寄存器中。至此，微處理器已經(jīng)取得了指令。

計(jì)算機(jī)專業(yè)英語1-55

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Next,themicroprocessordecodestheinstruction.Eachinstruction

mayrequireadifferentsequenceofoperationstoexecutethe

instruction.Whenthemicroprocessordecodestheinstruction,it

determineswhichinstructionitisinordertoselectthecorrect

sequenceofoperationstoperform.Thisisdoneentirelywithinthe

microprocessor;itdoesnotusethesystembuses.

接下來，微處理器對(duì)這條指令譯碼。每一條指令可能要有不同

的操作序列來執(zhí)行。當(dāng)微處理器對(duì)該指令譯碼是，它確定處理

的是哪一條指令以便選擇正確的操作序列去執(zhí)行。這一步完全

在微處理器內(nèi)完成，不需要使用系統(tǒng)總線。

計(jì)算機(jī)專業(yè)英語1-56

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Finally,themicroprocessorexecutestheinstruction.Thesequenceofoperations

toexecutetheinstructionvariesfrominstructiontoinstruction.Theexecute

routinemayreaddatafrommemory,writedatatomemory,readdatafromor

writedatatoanI/Odevice,performonlyoperationswithintheCPU,orperform

somecombinationoftheseoperations.Wenowlookathowthecomputer

performstheseoperationsfromasystemperspective.

最后，微處理器執(zhí)行該指令。指令不同，執(zhí)行的操作序列也不

同。執(zhí)行過程可以是從存儲(chǔ)器讀取數(shù)據(jù)，寫數(shù)據(jù)到存儲(chǔ)器，讀

或?qū)憯?shù)據(jù)到I/O設(shè)備，執(zhí)行CPU內(nèi)部操作或者執(zhí)行多個(gè)上述操作

的組合。下面我們從系統(tǒng)的角度來看計(jì)算機(jī)是怎樣執(zhí)行這些操

作的。

計(jì)算機(jī)專業(yè)英語1-57

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Toreaddatafrommemory,themicroprocessorperformsthesame

sequenceofoperationsitusestofetchaninstructionfrommemory.

Afterall,fetchinganinstructionissimplyreadingitfrommemory.

Figure2-2(a)showsthetimingoftheoperationstoreaddatafrom

memory.

微處理器從存儲(chǔ)器讀取數(shù)據(jù)所執(zhí)行的操作序列，同從存儲(chǔ)器中

去一條指令是一樣的。畢竟取指令就是簡(jiǎn)單地從存儲(chǔ)器中讀取

它。圖2?2(a)顯示了從存儲(chǔ)器中讀取數(shù)據(jù)的操作時(shí)序。

計(jì)算機(jī)專業(yè)英語1-58

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

InFigure2-2,noticethetopsymbol,CLK.Thisisthecomputersystemclock;the

microprocessorusesthesystemclocktosynchronizeitsoperations.The

microprocessorplacestheaddressontothebusatthebeginningofaclockcycle,a

0/1sequenceofthesystemclock.Oneclockcyclelater,toallowtimeformemory

todecodetheaddressandaccessitsdata,themicroprocessorassertstheREAD

Signal.Thiscausesmemorytoplaceitsdataontothesystemdatabus.Duringthis

clockcycle,themicroprocessorreadsthedataoffthesystembusandstoresitin

oneofitsregisters.Attheendoftheclockcycleitremovestheaddressfromthe

addressbusanddeassertstheREADsignal.Memorythenremovesthedatafrom

thedatabus,completingthememoryreadoperation.

在圖2?2中，注意最上面的符號(hào)CLK,它是計(jì)算機(jī)的系統(tǒng)時(shí)鐘，微處理器用系統(tǒng)時(shí)鐘

使其操作同步。在一個(gè)時(shí)鐘周期（系統(tǒng)時(shí)鐘的0/1序列）的開始位置，微處理器將地

址放到總線上。一個(gè)時(shí)鐘周期（允許存儲(chǔ)器對(duì)地址譯碼和訪問數(shù)據(jù)的時(shí)間）之后，微

處理器才發(fā)出讀信號(hào)。這使得存儲(chǔ)器將數(shù)據(jù)放到數(shù)據(jù)總線上。在這個(gè)時(shí)鐘周期之內(nèi)，

微處理器從系統(tǒng)總線上讀取數(shù)據(jù)，并存儲(chǔ)到它的某個(gè)寄存器中。在這個(gè)時(shí)鐘周期結(jié)束

時(shí)，微處理器撤消地址總線上的地址，并撤消讀信號(hào)。然后存儲(chǔ)器從數(shù)據(jù)總線上撤消

數(shù)據(jù)，也就完成了存儲(chǔ)器的讀操作。

計(jì)算機(jī)專業(yè)英語1-59

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

ThetimingofthememorywriteoperationisshowninFigure2-2(b).The

processorplacestheaddressanddataontothesystembusesduringthefirst

clockcycle.ThemicroprocessorthenassertsaWRITEcontrolsignal(orits

equivalent)atthestartofthesecondclockcycle.JustastheREADsignalcauses

memorytoreaddata,theWRITEsignaltriggersmemorytostoredata.Some

timeduringthiscycle,memorywritesthedataonthedatabustothememory

locationwhoseaddressisontheaddressbus.Attheendofthiscycle,the

processorcompletesthememorywriteoperationbyremovingtheaddressand

datafromthesystembusesanddeassertingtheWRITEsignal.

存儲(chǔ)器寫操作的時(shí)序如圖2?2(b)所示。在第一個(gè)時(shí)鐘周期，處理器將地址和

數(shù)據(jù)放到總線上，然后在第二個(gè)時(shí)鐘周期開始時(shí)發(fā)出一個(gè)寫(WRITE)控

制信號(hào)(或與之等價(jià)的信號(hào))。像讀信號(hào)促使存儲(chǔ)器讀取數(shù)據(jù)一樣，寫信號(hào)

促使存儲(chǔ)器存儲(chǔ)數(shù)據(jù)。在這個(gè)時(shí)鐘周期的某個(gè)時(shí)刻，存儲(chǔ)器將數(shù)據(jù)總線上的

數(shù)據(jù)寫入地址總線指示的存儲(chǔ)單元內(nèi)。當(dāng)這個(gè)時(shí)鐘周期結(jié)束，微處理器從系

統(tǒng)總線上撤消地址、數(shù)據(jù)及寫信號(hào)后，就完成了存儲(chǔ)器的寫操作。

計(jì)算機(jī)專業(yè)英語1-60

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

TheI/Oreadandwriteoperationsaresimilartothememoryreadandwrite

operations.AprocessormayuseeithermemorymappedI/OorisolatedI/O.Ifthe

processorsupportsmemorymappedI/O,itfollowsthesamesequencesof

operationstoinputoroutputdataastoreaddatafromorwritedatatomemory,

thesequencesshowninFigure2-2.(Remember,inmemorymappedI/O,the

processortreatsanI/Oportasamemorylocation,soitisreasonabletotreatan

I/Odataaccessthesameasamemoryaccess.)ProcessorsthatuseisolatedI/O

followthesameprocessbuthaveasecondcontrolsignaltodistinguishbetween

I/Oandmemoryaccesses.(CPUsthatuseisolatedI/Ocanhaveamemory

locationandanI/Oportwiththesameaddress,whichmakesthisextrasignal

necessary.)

I/O的讀寫操作與存儲(chǔ)器的讀寫操作類似。處理器可以使用存儲(chǔ)器影射I/O或者是單獨(dú)

I/Oo如果處理器支持存儲(chǔ)器影射I/O,則它遵循從存儲(chǔ)器讀寫數(shù)據(jù)同樣的操作順序，

該順序如圖2?2所示(記住，在存儲(chǔ)器影射I/O中，處理器把一個(gè)I/O端口當(dāng)作某個(gè)存

儲(chǔ)單元，當(dāng)然I/O的數(shù)據(jù)訪問同存儲(chǔ)器的數(shù)據(jù)訪問一樣的)。使用單獨(dú)I/O的處理器遵

循同樣的處理過程，但是另有一個(gè)控制信號(hào)用以區(qū)別是I/O訪問還是存儲(chǔ)器訪問(使

用單獨(dú)I/O的CPU允許一個(gè)存儲(chǔ)單元和某個(gè)I/O端口具有相同的地址，因此需要這一額

外的信號(hào)加以區(qū)分)。

計(jì)算機(jī)專業(yè)英語1-61

Chapter1TheHistoryandFutureofComputers

2.1.2InstructionCycle

Finally,considerinstructionsthatareexecutedentirelywithinthe

microprocessor.TheINACinstructionoftheRelativelySimple

CPU,andtheMOVrl,r2instructionofthe8085microprocessor,

canbeexecutedwithoutaccessingmemoryorI/Odevices.As

withinstructiondecoding,theexecutionoftheseinstructionsdoes

notmakeuseofthesystembuses.

最后，考慮一下完全在微處理器內(nèi)部執(zhí)行的指令。相對(duì)簡(jiǎn)單

CPU的INAC指令和8085的MOVrl,r2指令的執(zhí)行都不要訪問

存儲(chǔ)器和I/O設(shè)備。按照指令譯碼的結(jié)果，這些指令的執(zhí)行不會(huì)

用到系統(tǒng)總線。

計(jì)算機(jī)專業(yè)英語1-62

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

NewWords&Expressions:

latch閉鎖，鎖存programcounter程序計(jì)數(shù)器

instructionregister指令寄存器operandn?操作數(shù)

incrementn?增量，加1flagregister標(biāo)志寄存器

pipelinen?流水線microsequenced微層序的

localbus局部總線

Abbreviations:

ALU(ArithmeticLogicUnit)算術(shù)邏輯單元

計(jì)算機(jī)專業(yè)英語1-63

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

TheCPUcontrolsthecomputer.Itfetchesinstructionsfrommemory,

supplyingtheaddressandcontrolsignalsneededbymemorytoaccessits

data.TheCPUdecodestheinstructionandcontrolstheexecutionprocedure.

Itperformssomeoperationsinternally,andsuppliestheaddress,data,and

controlsignalsneededbymemoryandI/Odevicestoexecutetheinstruction.

NothinghappensinthecomputerunlesstheCPUcausesittohappen.

CPU控制整個(gè)計(jì)算機(jī)。它從存儲(chǔ)器中取指令，提供存儲(chǔ)器需要

的地址和控制信號(hào)。CPU對(duì)指令譯碼并且控制整個(gè)執(zhí)行過程。

它執(zhí)行一些內(nèi)部操作，并且為存儲(chǔ)器和I/O設(shè)備執(zhí)行指令提供必

要的地址、數(shù)據(jù)和控制信號(hào)。除非CPU激發(fā)，否則，計(jì)算機(jī)什

么事情都不會(huì)發(fā)生。

計(jì)算機(jī)專業(yè)英語1-64

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

Internally,theCPUhasthreesections,asshowninFigure2-3.Theregister

sections,asitsnameimplies,includesasetofregistersandabusorother

communicationmechanism.Theregistersinaprocessorsinstructionset

architecturearefoundinthissectionoftheCPU.Thesystemaddressanddata

busesinteractwiththissectionoftheCPU.Theregistersectionalsocontains

otherregistersthatarenotdirectlyaccessiblebytheprogrammer.Therelatively

simpleCPUincludesregisterstolatchtheaddressbeingaccessedinmemoryand

atemporarystorageregister,aswellasotherregistersthatarenotapartofits

instructionsetarchitecture.

CPU內(nèi)部有三大分區(qū)，如圖2?3所示。寄存器區(qū)，顧名思義，它包括一組寄存

器、一條總線或其他通信機(jī)制。微處理器指令集結(jié)構(gòu)中的寄存器就屬于CPU

的這一分區(qū)。系統(tǒng)的地址和數(shù)據(jù)總線與寄存器交互。此分區(qū)還包括程序員不

能直接訪問的一些寄存器。相對(duì)簡(jiǎn)單CPU含有寄存器用以鎖存正在訪問的存

儲(chǔ)器地址，還有暫存器以及指令集結(jié)構(gòu)中沒有的其他寄存器等。

計(jì)算機(jī)專業(yè)英語1-65

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

Duringthefetchportionoftheinstructioncycle,theprocessorfirstoutputsthe

addressoftheinstructionontotheaddressbus.Theprocessorhasaregister

calledtheprogramcounter;theCPUkeepstheaddressofthenextinstructionto

befetchedinthisregister.BeforetheCPUoutputstheaddressontothesystem's

addressbus,itretrievestheaddressfromtheprogramcounterregister.Atthe

endoftheinstructionfetch,theCPUreadstheinstructioncodefromthesystem

databus.Itstoresthisvalueinaninternalregister,usuallycalledtheinstruction

registerorsomethingsimilar.

在指令周期的取指階段，處理器首先將指令的地址輸出到地址總線上。處理

器有一個(gè)寄存器叫做程序計(jì)數(shù)器，CPU將下一條要取的指令的地址存放在程

序計(jì)數(shù)器中。在CPU將地址輸出到系統(tǒng)的地址總線之前，必須從程序計(jì)數(shù)器

中取出該地址。在指令結(jié)束前，CPU從系統(tǒng)時(shí)局總線上讀取指令碼，它把該

指令碼存儲(chǔ)在某個(gè)內(nèi)部寄存器中，該寄存器通常稱作指令寄存器或其他相似

的名字。

計(jì)算機(jī)專業(yè)英語1-66

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

ThearithmeticlogicunitorALUperformsmostarithmeticandlogical

operations,suchasaddingorADDingvalues.Itreceivesitsoperandsfrom

theregistersectionoftheCPUandstoresitsresultsbackintheregister

section.SincetheALUmustcompleteitsoperationswithinasingleclock

cycle,itisconstructedusingonlycombinatoriallogic.TheADD

instructionsintherelativelysimpleCPUandthe8085microprocessoruse

theALUduringtheirexecutions.

算術(shù)邏輯單元執(zhí)行大部分的算術(shù)邏輯運(yùn)算，如加法、邏輯與等

運(yùn)算。它從CPU的寄存器取得操作數(shù)，然后將運(yùn)算結(jié)果再存回

到寄存器區(qū)。由于必須在一個(gè)時(shí)鐘周期內(nèi)完成操作，因此ALU

只采用組合邏輯構(gòu)造而成。相對(duì)簡(jiǎn)單CPU和8085微處理器中的

ADD指令在執(zhí)行中都有使用ALU。

計(jì)算機(jī)專業(yè)英語1-67

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

JustastheCPUcontrolsthecomputer(inadditiontoitsotherfunctions),the

controlunitcontrolstheCPU.Thisunitgeneratestheinternalcontrolsignalsthat

causeregisterstoloaddata,incrementorcleartheircontents,andoutputtheir

contents,aswellascausetheALUtoperformthecorrectfunction.Thesesignals

areshownascontrolsignalsinFigure2-3.Thecontrolunitreceivessomedata

valuesfromtheregisterunit,whichitusestogeneratethecontrolsignals.This

dataincludestheinstructioncodeandthevaluesofsomeflagregisters.

同CPU控制整個(gè)計(jì)算機(jī)(除了其他功能外)一樣，控制單元控制著CPU。這

個(gè)單元產(chǎn)生內(nèi)部控制信號(hào)，促使寄存器裝載數(shù)據(jù)，自動(dòng)加1或清零，輸出它

的內(nèi)容，使得ALU完成正確的操作等等。這些信號(hào)作為控制信號(hào)顯示在圖2?

3中?？刂茊卧獜募拇嫫鲄^(qū)取得一些數(shù)據(jù)用以產(chǎn)生控制信號(hào)，這些數(shù)據(jù)包括

指令碼和某些標(biāo)志寄存器的值。

計(jì)算機(jī)專業(yè)英語1-68

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

Thecontrolunitalsogeneratesthesignalsforthesystemcontrol

bus,suchastheREAD,WRITE,andsignals.Amicroprocessor

typicallyperformsasequenceofoperationstofetch,decode,and

executeaninstruction.Byassertingtheseinternalandexternal

controlsignalsinthepropersequence,thecontrolunitcausesthe

CPUandtherestofthecomputertoperformtheoperations

neededtocorrectlyprocessinstructions.

控制單元也產(chǎn)生系統(tǒng)控制總線上的信號(hào)，例如READ,WRATE,

信號(hào)等。典型的一個(gè)微處理器執(zhí)行取指令、譯指令和執(zhí)行指令

等一系列的操作。通過以正確的順序激發(fā)這些內(nèi)部或外部控制

信號(hào)，控制單元使CPU和計(jì)算機(jī)的其余部分完成正確處理指令

所需要的操作。

計(jì)算機(jī)專業(yè)英語1-69

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

ThisdescriptionoftheCPUisincomplete.Currentprocessors

havemorecomplexfeaturesthatimprovetheirperformance.One

suchmechanism,theinstructionpipeline,allowstheCPUtofetch

oneinstructionwhilesimultaneouslyexecutinganotherinstruction.

以上對(duì)CPU的描述并不完整。現(xiàn)在的處理器擁有更加復(fù)雜的特

征以提高其性能。這些機(jī)制中有一種是指令流水線技術(shù)，它允

許CPU在執(zhí)行一條指令的同時(shí)取出另一條指令。

計(jì)算機(jī)專業(yè)英語1-70

Chapter1TheHistoryandFutureofComputers

2.2CPUORGANIZATION

InthissectionwehaveintroducedtheCPUfromasystem

perspective,butwehavenotdiscusseditsinternaldesign.We

examinetheregisters,datapaths,andcontrolunit,allofwhich

acttogethertocausetheCPUtoproperlyfetch,decode,and

executeinstructions.MicrosequencedCPUshavethesame

registers,ALUsanddatapathsashardwiredCPUs,but

completelydifferentcontrolunits.

本節(jié)我們從系統(tǒng)的角度介紹了CPU,但我們還沒有討論它的內(nèi)

部設(shè)計(jì)。我們描述了CPU的寄存器、數(shù)據(jù)通路、控制單元等，

所有部件一起工作使CPU正確地讀取、譯碼和執(zhí)行指令。微層

序CPU具有同硬連線CPU一樣的寄存器、ALU和數(shù)據(jù)通路，但

二者控制單元完全不同。

計(jì)算機(jī)專業(yè)英語1-71

Chapter1TheHistoryandFutureofComputers

2.3MemorySubsystemOrganizationandInterfacing

NewWords&Expressions:

multibyten.多字節(jié)MBn.兆字節(jié)

shutoffn.切斷，關(guān)閉enablen??使能

tri-state三態(tài)tri-stated高阻態(tài)

dimensionn?尺度，維(數(shù))configurationn?構(gòu)造,結(jié)構(gòu)，配置

asfaras盡；就；至于high-order高位

low-order低位interleavingn?交叉，交錯(cuò)

contiguousadj,鄰近的，接近的assignvt?分配，指派

bigendian高位優(yōu)先littleendian代位優(yōu)先

hexadecimaladj.十六進(jìn)制的；n?十六進(jìn)制alignmentn?對(duì)齊方式

leftmostadj.最左邊的rightmostadj.最右邊的，最右面的

consecutiveadj.連續(xù)的，聯(lián)貫的cachen.高速緩沖

virtualmemory虛擬存儲(chǔ)器buffern.緩沖器

ROM(ReadOnlyMemory)只讀存儲(chǔ)器

RAM(RandomAccessMemory)隨機(jī)存取存貯器

RISC(ReducedInstructionSetComputer)精簡(jiǎn)指令集計(jì)算機(jī)

計(jì)算機(jī)專業(yè)英語1-72

Chapter1TheHistoryandFutureofComputers

2.3MemorySubsystemOrganizationandInterfacing

Inthissectionweexaminetheconstructionandfunctionsofthe

memorysubsystemofacomputer.Wereviewthedifferenttypesof

physicalmemoryandtheinternalorganizationoftheirchips.We

discusstheconstructionofthememorysubsystem,aswellas

multibytewordorganizationsandadvancedmemoryorganizations.

本節(jié)我們將討論計(jì)算機(jī)中存儲(chǔ)器子系統(tǒng)的結(jié)構(gòu)和功能。我們將

會(huì)回顧不同類型的物理存儲(chǔ)器及其芯片的內(nèi)部組成，討論存儲(chǔ)

器子系統(tǒng)的結(jié)構(gòu)，以及多字節(jié)的組織和高級(jí)存儲(chǔ)器的組成。

計(jì)算機(jī)專業(yè)英語1-73

Chapter1TheHistoryandFutureofComputers

2.3.1TypesofMemory

TheinternalorganizationsofROMandRAMchipsaresimilar.To

illustratethesimplestorganization,alinearorganization,consideran

8x2ROMchip.Forsimplicity,programmingcomponentsarenot

shown.Thischiphasthreeaddressinputsandtwodataoutputs,and

16bitsofinternalstoragearrangedaseight2-bitlocations.

存儲(chǔ)器芯片有兩種類型：只讀存儲(chǔ)器（ROM）和隨機(jī)存取存儲(chǔ)器

（RAM）o只讀存儲(chǔ)器芯片是為數(shù)據(jù)（此數(shù)據(jù)可包括程序的指令）只讀

的應(yīng)用而設(shè)計(jì)的。這些芯片在加入系統(tǒng)之前，就已經(jīng)被某個(gè)外部編程器而

裝好數(shù)據(jù)了。這個(gè)工作一旦完成，其數(shù)據(jù)通常不再改變。ROM芯片總是

保存有數(shù)據(jù)，甚至在芯片斷電以后。例如，一個(gè)微波爐的嵌入式控制器可

以連續(xù)運(yùn)行一個(gè)不變的程序。這個(gè)程序就存儲(chǔ)在一片ROM上。

計(jì)算機(jī)專業(yè)英語1-74

Chapter1TheHistoryandFutureofComputers

2.3.1TypesofMemory

RandomAccessMemory(RAM),alsocalledread/writememory,

canbeusedtostoredatathatchanges.Thisisthetypeofmemory

referredtoasXMBofmemoryinadsforPCs.UnlikeROM,RAM

chipslosetheirdataoncepowerisshutoffManycomputersystems,

includingpersonalcomputers,includebothROMandRAM.

隨機(jī)訪問存儲(chǔ)器也稱為讀寫存儲(chǔ)器，用來存儲(chǔ)可以改變的數(shù)

據(jù)。這就是我們?cè)趥€(gè)人電腦廣告上經(jīng)?？吹降腦XMB的內(nèi)

存所指的那種類型。不像ROM,RAM芯片一旦掉電，數(shù)據(jù)

就會(huì)丟失。許多計(jì)算機(jī)系統(tǒng)，包括個(gè)人電腦，都同時(shí)擁有

ROM和RAM。

計(jì)算機(jī)專業(yè)英語1-75

Chapter1TheHistoryandFutureofComputers

2?3.2InternalChipOrganization

TheinternalorganizationsofROMandRAMchipsaresimilar.To

illustratethesimplestorganization,alinearorganization,consider

an8x2ROMchip.Forsimplicity,programmingcomponentsare

notshown.Thischiphasthreeaddressinputsandtwodataoutputs,

and16bitsofinternalstoragearrangedaseight2-bitlocations.

ROM和RAM芯片的內(nèi)部組成是相似的。為了說明一個(gè)最簡(jiǎn)

單的組成——線性組成，我們來考慮一個(gè)8x2的ROM芯片。

為了簡(jiǎn)化，編成器件沒有畫出來。這個(gè)芯片有三個(gè)地址輸入

端和兩個(gè)數(shù)據(jù)輸出端，以及16位的內(nèi)部存儲(chǔ)元件，它排列成

8個(gè)單元，每個(gè)單元2位。

計(jì)算機(jī)專業(yè)英語1-76

Chapter1TheHistoryandFutureofComputers

2.3.2InternalChipOrganization

Thethreeaddressbitsaredecodedtoselectoneoftheeight

locations,butonlyifthechipenableisactive.IfCEM),the

decoderisdisabledandnolocationisselected.Thetri-state

buffersforthatlocation^cellsareenabled,allowingdatatopass

totheoutputbuffers.IfbothCEandOEsetto19thesebuffers

areenabledandthedataisoutputfromthechip;otherwisethe

outputsaretri-stated.

三個(gè)地址位經(jīng)過譯碼，可以選擇8個(gè)中的一個(gè)，但只有芯片的使能端要有

效才行。如果CE=0,譯碼器被禁止，則不選擇任何單元。該單元上的三

態(tài)緩沖器是有效的，允許數(shù)據(jù)輸出到緩沖器中。如果CE=1且OE=L則這

些緩沖器有效，數(shù)據(jù)從芯片中輸出；否則，輸出是高阻態(tài)。

計(jì)算機(jī)專業(yè)英語1-77

Chapter1TheHistoryandFutureofComputers

2.3.2InternalChipOrganization

Asthenumberoflocationsincreases,thesizeoftheaddressdecoder

neededinalinearorganizationbecomesprohibitivelylarge.To

remedythisproblem,thememorychipcanbedesignedusing

multipledimensionsofdecoding.

隨著單元數(shù)量的增加，線性組成中地址譯碼器的規(guī)模變得相

當(dāng)